35#ifndef _EPIPHANY_CPU_H
36#define _EPIPHANY_CPU_H
64#define CPU_ISR_PASSES_FRAME_POINTER TRUE
66#define CPU_HARDWARE_FP FALSE
68#define CPU_SOFTWARE_FP FALSE
70#define CPU_ALL_TASKS_ARE_FP FALSE
72#define CPU_IDLE_TASK_IS_FP FALSE
74#define CPU_USE_DEFERRED_FP_SWITCH FALSE
76#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
87#define CPU_STACK_GROWS_UP FALSE
90#define CPU_CACHE_LINE_BYTES 64
92#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
101#define CPU_MODES_INTERRUPT_MASK 0x00000001
190 volatile bool is_executing;
194#define _CPU_Context_Get_SP( _context ) \
206#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
214#define CPU_STACK_MINIMUM_SIZE 4096
222#define CPU_ALIGNMENT 8
228#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
251#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
263#define CPU_STACK_ALIGNMENT 8
265#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
277#define _CPU_Initialize_vectors()
285static inline uint32_t epiphany_interrupt_disable(
void )
288 __asm__ __volatile__ (
"movfs %[sr], status \n" : [sr]
"=r" (sr):);
289 __asm__ __volatile__(
"gid \n");
293static inline void epiphany_interrupt_enable(uint32_t level)
295 __asm__ __volatile__(
"gie \n");
296 __asm__ __volatile__ (
"movts status, %[level] \n" :: [level]
"r" (level):);
299#define _CPU_ISR_Disable( _level ) \
300 _level = epiphany_interrupt_disable()
309#define _CPU_ISR_Enable( _level ) \
310 epiphany_interrupt_enable( _level )
320#define _CPU_ISR_Flash( _level ) \
322 if ( (_level & 0x2) != 0 ) \
323 _CPU_ISR_Enable( _level ); \
324 epiphany_interrupt_disable(); \
329 return ( level & 0x2 ) != 0;
383#define EPIPHANY_GCC_RED_ZONE_SIZE 128
404 void *stack_area_begin,
405 size_t stack_area_size,
407 void (*entry_point)(
void ),
423#define _CPU_Context_Restart_self( _the_context ) \
424 _CPU_Context_restore( (_the_context) )
439#define _CPU_Fatal_halt(_source, _error ) \
440 printk("Fatal Error %d.%" PRIu32 " Halted\n",_source, _error); \
441 asm("trap 3" :: "r" (_error)); \
446#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
457#define CPU_SIZEOF_POINTER 4
458#define CPU_EXCEPTION_FRAME_SIZE 260
460#define CPU_MAXIMUM_PROCESSORS 32
534 void **fp_context_ptr
545 void **fp_context_ptr
569static inline unsigned int CPU_swap_u32(
573 uint32_t byte1, byte2, byte3, byte4, swapped;
575 byte4 = (value >> 24) & 0xff;
576 byte3 = (value >> 16) & 0xff;
577 byte2 = (value >> 8) & 0xff;
578 byte1 = value & 0xff;
580 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
584#define CPU_swap_u16( value ) \
585 (((value&0xff) << 8) | ((value >> 8)&0xff))
593static inline CPU_Counter_ticks _CPU_Counter_difference(
594 CPU_Counter_ticks second,
595 CPU_Counter_ticks first
598 return second - first;
Interface to Kernel Print Methods.
#define RTEMS_NO_RETURN
Definition: basedefs.h:102
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:66
void _CPU_ISR_Set_level(uint32_t level)
Sets the hardware interrupt level by the level value.
Definition: cpu.c:57
bool _CPU_ISR_Is_enabled(uint32_t level)
Returns true if interrupts are enabled in the specified ISR level, otherwise returns false.
Definition: cpu.h:375
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uintptr_t CPU_Uint32ptr
Definition: cpu.h:662
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
void _CPU_Context_restore(Context_Control *new_context) RTEMS_NO_RETURN
Definition: cpu_asm.c:111
uint32_t _CPU_ISR_Get_level(void)
Definition: cpu.c:88
void _CPU_Context_Initialize(Context_Control *context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
Initializes the CPU context.
Definition: epiphany-context-initialize.c:40
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
Provide printf() PRIxxx Constante Beyond Standards.
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1210
#define _CPU_Context_restore_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:904
#define _CPU_Context_save_fp(_fp_context_ptr)
Nothing to do due to the synchronous or lazy floating point switch.
Definition: cpu.h:898
The set of registers that specifies the complete processor state.
Definition: cpu.h:629
Interrupt stack frame (ISF).
Definition: cpu.h:191
Thread register context.
Definition: cpu.h:194
Definition: deflate.c:115
unsigned context
Definition: tlb.h:1