cpu.h

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/*
 *  COPYRIGHT (c) 1989-2011.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.rtems.org/license/LICENSE.
 */

#ifndef _RTEMS_SCORE_CPU_H
#define _RTEMS_SCORE_CPU_H

#ifdef __cplusplus
extern "C" {
#endif

#include <rtems/score/types.h>
#include <rtems/score/sparc.h>

/* conditional compilation parameters */

#if defined(RTEMS_SMP)
  /*
   * The SPARC ABI is a bit special with respect to the floating point context.
   * The complete floating point context is volatile.  Thus from an ABI point
   * of view nothing needs to be saved and restored during a context switch.
   * Instead the floating point context must be saved and restored during
   * interrupt processing.  Historically the deferred floating point switch is
   * used for SPARC and the complete floating point context is saved and
   * restored during a context switch to the new floating point unit owner.
   * This is a bit dangerous since post-switch actions (e.g. signal handlers)
   * and context switch extensions may silently corrupt the floating point
   * context.  The floating point unit is disabled for interrupt handlers.
   * Thus in case an interrupt handler uses the floating point unit then this
   * will result in a trap.
   *
   * On SMP configurations the deferred floating point switch is not
   * supported in principle.  So use here a safe floating point support.  Safe
   * means that the volatile floating point context is saved and restored
   * around a thread dispatch issued during interrupt processing.  Thus
   * post-switch actions and context switch extensions may safely use the
   * floating point unit.
   */
  #define SPARC_USE_SAFE_FP_SUPPORT
#endif

#define CPU_INLINE_ENABLE_DISPATCH       TRUE

#define CPU_HAS_SOFTWARE_INTERRUPT_STACK   TRUE

#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE

#define CPU_HAS_HARDWARE_INTERRUPT_STACK  FALSE

#define CPU_ALLOCATE_INTERRUPT_STACK      TRUE

#define CPU_ISR_PASSES_FRAME_POINTER 0

#if ( SPARC_HAS_FPU == 1 ) && !defined(SPARC_USE_SAFE_FP_SUPPORT)
  #define CPU_HARDWARE_FP     TRUE
#else
  #define CPU_HARDWARE_FP     FALSE
#endif

#define CPU_SOFTWARE_FP     FALSE

#define CPU_ALL_TASKS_ARE_FP     FALSE

#define CPU_IDLE_TASK_IS_FP      FALSE

#if defined(SPARC_USE_SAFE_FP_SUPPORT)
  #define CPU_USE_DEFERRED_FP_SWITCH FALSE
#else
  #define CPU_USE_DEFERRED_FP_SWITCH TRUE
#endif

#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE

#define CPU_STACK_GROWS_UP               FALSE

#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (32)))

#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE

#define CPU_BIG_ENDIAN                           TRUE

#define CPU_LITTLE_ENDIAN                        FALSE

#define CPU_MODES_INTERRUPT_MASK   0x0000000F

#ifndef ASM

typedef struct {
  uint32_t    l0;
  uint32_t    l1;
  uint32_t    l2;
  uint32_t    l3;
  uint32_t    l4;
  uint32_t    l5;
  uint32_t    l6;
  uint32_t    l7;
  uint32_t    i0;
  uint32_t    i1;
  uint32_t    i2;
  uint32_t    i3;
  uint32_t    i4;
  uint32_t    i5;
  uint32_t    i6_fp;
  uint32_t    i7;
  void       *structure_return_address;

  /*
   * The following are for the callee to save the register arguments in
   * should this be necessary.
   */
  uint32_t    saved_arg0;
  uint32_t    saved_arg1;
  uint32_t    saved_arg2;
  uint32_t    saved_arg3;
  uint32_t    saved_arg4;
  uint32_t    saved_arg5;
  uint32_t    pad0;
}  CPU_Minimum_stack_frame;

#endif /* ASM */

#define CPU_STACK_FRAME_L0_OFFSET             0x00

#define CPU_STACK_FRAME_L1_OFFSET             0x04

#define CPU_STACK_FRAME_L2_OFFSET             0x08

#define CPU_STACK_FRAME_L3_OFFSET             0x0c

#define CPU_STACK_FRAME_L4_OFFSET             0x10

#define CPU_STACK_FRAME_L5_OFFSET             0x14

#define CPU_STACK_FRAME_L6_OFFSET             0x18

#define CPU_STACK_FRAME_L7_OFFSET             0x1c

#define CPU_STACK_FRAME_I0_OFFSET             0x20

#define CPU_STACK_FRAME_I1_OFFSET             0x24

#define CPU_STACK_FRAME_I2_OFFSET             0x28

#define CPU_STACK_FRAME_I3_OFFSET             0x2c

#define CPU_STACK_FRAME_I4_OFFSET             0x30

#define CPU_STACK_FRAME_I5_OFFSET             0x34

#define CPU_STACK_FRAME_I6_FP_OFFSET          0x38

#define CPU_STACK_FRAME_I7_OFFSET             0x3c

#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET   0x40

#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET     0x44

#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET     0x48

#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET     0x4c

#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET     0x50

#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET     0x54

#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET     0x58

#define CPU_STACK_FRAME_PAD0_OFFSET           0x5c

#define CPU_MINIMUM_STACK_FRAME_SIZE          0x60

#if ( SPARC_HAS_FPU == 1 )
  #define CPU_PER_CPU_CONTROL_SIZE 8
#else
  #define CPU_PER_CPU_CONTROL_SIZE 4
#endif

#define SPARC_PER_CPU_ISR_DISPATCH_DISABLE 0

#if ( SPARC_HAS_FPU == 1 )

  #define SPARC_PER_CPU_FSR_OFFSET 4
#endif

#ifndef ASM

typedef struct {
  uint32_t isr_dispatch_disable;

#if ( SPARC_HAS_FPU == 1 )

  uint32_t fsr;
#endif
} CPU_Per_CPU_control;

typedef struct {
  uint32_t   g5;
  uint32_t   g7;

  double     l0_and_l1;
  uint32_t   l2;
  uint32_t   l3;
  uint32_t   l4;
  uint32_t   l5;
  uint32_t   l6;
  uint32_t   l7;

  uint32_t   i0;
  uint32_t   i1;
  uint32_t   i2;
  uint32_t   i3;
  uint32_t   i4;
  uint32_t   i5;
  uint32_t   i6_fp;
  uint32_t   i7;

  uint32_t   o6_sp;
  uint32_t   o7;

  uint32_t   psr;
  uint32_t   isr_dispatch_disable;

#if defined(RTEMS_SMP)
  volatile uint32_t is_executing;
#endif
} Context_Control;

#define _CPU_Context_Get_SP( _context ) \
  (_context)->o6_sp

#ifdef RTEMS_SMP
  static inline bool _CPU_Context_Get_is_executing(
    const Context_Control *context
  )
  {
    return context->is_executing;
  }

  static inline void _CPU_Context_Set_is_executing(
    Context_Control *context,
    bool is_executing
  )
  {
    context->is_executing = is_executing;
  }
#endif

#endif /* ASM */

/*
 *  Offsets of fields with Context_Control for assembly routines.
 */

#define G5_OFFSET    0x00

#define G7_OFFSET    0x04

#define L0_OFFSET    0x08

#define L1_OFFSET    0x0C

#define L2_OFFSET    0x10

#define L3_OFFSET    0x14

#define L4_OFFSET    0x18

#define L5_OFFSET    0x1C

#define L6_OFFSET    0x20

#define L7_OFFSET    0x24

#define I0_OFFSET    0x28

#define I1_OFFSET    0x2C

#define I2_OFFSET    0x30

#define I3_OFFSET    0x34

#define I4_OFFSET    0x38

#define I5_OFFSET    0x3C

#define I6_FP_OFFSET 0x40

#define I7_OFFSET    0x44

#define O6_SP_OFFSET 0x48

#define O7_OFFSET    0x4C

#define PSR_OFFSET   0x50

#define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x54

#if defined(RTEMS_SMP)
  #define SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x58
#endif

#ifndef ASM

typedef struct {
  double      f0_f1;
  double      f2_f3;
  double      f4_f5;
  double      f6_f7;
  double      f8_f9;
  double      f10_f11;
  double      f12_f13;
  double      f14_f15;
  double      f16_f17;
  double      f18_f19;
  double      f20_f21;
  double      f22_f23;
  double      f24_f25;
  double      f26_f27;
  double      f28_f29;
  double      f30_f31;
  uint32_t    fsr;
} Context_Control_fp;

#endif /* ASM */

/*
 *  Offsets of fields with Context_Control_fp for assembly routines.
 */

#define FO_F1_OFFSET     0x00

#define F2_F3_OFFSET     0x08

#define F4_F5_OFFSET     0x10

#define F6_F7_OFFSET     0x18

#define F8_F9_OFFSET     0x20

#define F1O_F11_OFFSET   0x28

#define F12_F13_OFFSET   0x30

#define F14_F15_OFFSET   0x38

#define F16_F17_OFFSET   0x40

#define F18_F19_OFFSET   0x48

#define F2O_F21_OFFSET   0x50

#define F22_F23_OFFSET   0x58

#define F24_F25_OFFSET   0x60

#define F26_F27_OFFSET   0x68

#define F28_F29_OFFSET   0x70

#define F3O_F31_OFFSET   0x78

#define FSR_OFFSET       0x80

#define CONTEXT_CONTROL_FP_SIZE 0x84

#ifndef ASM

typedef struct {
  CPU_Minimum_stack_frame  Stack_frame;
  uint32_t                 psr;
  uint32_t                 pc;
  uint32_t                 npc;
  uint32_t                 g1;
  uint32_t                 g2;
  uint32_t                 g3;
  uint32_t                 g4;
  uint32_t                 g5;
  uint32_t                 reserved_for_alignment;
  uint32_t                 g7;
  uint32_t                 i0;
  uint32_t                 i1;
  uint32_t                 i2;
  uint32_t                 i3;
  uint32_t                 i4;
  uint32_t                 i5;
  uint32_t                 i6_fp;
  uint32_t                 i7;
  uint32_t                 y;
  uint32_t                 tpc;
} CPU_Interrupt_frame;

#endif /* ASM */

/*
 *  Offsets of fields with CPU_Interrupt_frame for assembly routines.
 */

#define ISF_PSR_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x00

#define ISF_PC_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x04

#define ISF_NPC_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x08

#define ISF_G1_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c

#define ISF_G2_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x10

#define ISF_G3_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x14

#define ISF_G4_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x18

#define ISF_G5_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c

#define ISF_G7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x24

#define ISF_I0_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x28

#define ISF_I1_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c

#define ISF_I2_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x30

#define ISF_I3_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x34

#define ISF_I4_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x38

#define ISF_I5_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c

#define ISF_I6_FP_OFFSET       CPU_MINIMUM_STACK_FRAME_SIZE + 0x40

#define ISF_I7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x44

#define ISF_Y_OFFSET           CPU_MINIMUM_STACK_FRAME_SIZE + 0x48

#define ISF_TPC_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c

#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE \
        CPU_MINIMUM_STACK_FRAME_SIZE + 0x50

#ifndef ASM

SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT;

typedef struct {
  uint32_t     mov_psr_l0;
  uint32_t     sethi_of_handler_to_l4;
  uint32_t     jmp_to_low_of_handler_plus_l4;
  uint32_t     mov_vector_l3;
} CPU_Trap_table_entry;

extern const CPU_Trap_table_entry _CPU_Trap_slot_template;

#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )

#endif

#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024

#define CPU_INTERRUPT_NUMBER_OF_VECTORS     256

#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511

#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK     0x100

#define SPARC_ASYNCHRONOUS_TRAP( _trap )    (_trap)

#define SPARC_SYNCHRONOUS_TRAP( _trap )     ((_trap) + 256 )

#define SPARC_REAL_TRAP_NUMBER( _trap )     ((_trap) % 256)

#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE

#define CPU_STACK_MINIMUM_SIZE  (1024*4)

#define CPU_SIZEOF_POINTER 4

#define CPU_ALIGNMENT      8

#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT

#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT

#define CPU_STACK_ALIGNMENT        16

#ifndef ASM

/*
 *  ISR handler macros
 */

#define _CPU_Initialize_vectors()

#define _CPU_ISR_Disable( _level ) \
  (_level) = sparc_disable_interrupts()

#define _CPU_ISR_Enable( _level ) \
  sparc_enable_interrupts( _level )

#define _CPU_ISR_Flash( _level ) \
  sparc_flash_interrupts( _level )

#define _CPU_ISR_Set_level( _newlevel ) \
   sparc_enable_interrupts( _newlevel << 8)

uint32_t   _CPU_ISR_Get_level( void );

/* end of ISR handler macros */

/* Context handler macros */

void _CPU_Context_Initialize(
  Context_Control  *the_context,
  uint32_t         *stack_base,
  uint32_t          size,
  uint32_t          new_level,
  void             *entry_point,
  bool              is_fp,
  void             *tls_area
);

#define _CPU_Context_Initialization_at_thread_begin() \
  do { \
    __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \
  } while (0)

#define _CPU_Context_Restart_self( _the_context ) \
   _CPU_Context_restore( (_the_context) );

#define _CPU_Context_Fp_start( _base, _offset ) \
   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )

#define _CPU_Context_Initialize_fp( _destination ) \
  do { \
   *(*(_destination)) = _CPU_Null_fp_context; \
  } while (0)

/* end of Context handler macros */

/* Fatal Error manager macros */

extern void _CPU_Fatal_halt(uint32_t source, uint32_t error)
  RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;

/* end of Fatal Error manager macros */

/* Bitfield handler macros */

#if ( SPARC_HAS_BITSCAN == 0 )

  #define CPU_USE_GENERIC_BITFIELD_CODE TRUE

  #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
#else
  #error "scan instruction not currently supported by RTEMS!!"
#endif

/* end of Bitfield handler macros */

/* functions */

void _CPU_Initialize(void);

void _CPU_ISR_install_raw_handler(
  uint32_t    vector,
  proc_ptr    new_handler,
  proc_ptr   *old_handler
);

void _CPU_ISR_install_vector(
  uint32_t    vector,
  proc_ptr    new_handler,
  proc_ptr   *old_handler
);

void _CPU_Context_switch(
  Context_Control  *run,
  Context_Control  *heir
);

void _CPU_Context_restore(
  Context_Control *new_context
) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;

register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__( "g6" );

#define _CPU_Get_current_per_CPU_control() ( _SPARC_Per_CPU_current )

#if defined(RTEMS_SMP)
  uint32_t _CPU_SMP_Initialize( void );

  bool _CPU_SMP_Start_processor( uint32_t cpu_index );

  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );

  void _CPU_SMP_Prepare_start_multitasking( void );

  #if defined(__leon__) && !defined(RTEMS_PARAVIRT)
    static inline uint32_t _CPU_SMP_Get_current_processor( void )
    {
      return _LEON3_Get_current_processor();
    }
  #else
    uint32_t _CPU_SMP_Get_current_processor( void );
  #endif

  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );

  static inline void _CPU_SMP_Processor_event_broadcast( void )
  {
    __asm__ volatile ( "" : : : "memory" );
  }

  static inline void _CPU_SMP_Processor_event_receive( void )
  {
    __asm__ volatile ( "" : : : "memory" );
  }
#endif

void _CPU_Context_save_fp(
  Context_Control_fp **fp_context_ptr
);

void _CPU_Context_restore_fp(
  Context_Control_fp **fp_context_ptr
);

void _CPU_Context_volatile_clobber( uintptr_t pattern );

void _CPU_Context_validate( uintptr_t pattern );

typedef struct {
  uint32_t trap;
  CPU_Interrupt_frame *isf;
} CPU_Exception_frame;

void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );

static inline uint32_t CPU_swap_u32(
  uint32_t value
)
{
  uint32_t   byte1, byte2, byte3, byte4, swapped;

  byte4 = (value >> 24) & 0xff;
  byte3 = (value >> 16) & 0xff;
  byte2 = (value >> 8)  & 0xff;
  byte1 =  value        & 0xff;

  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
  return( swapped );
}

#define CPU_swap_u16( value ) \
  (((value&0xff) << 8) | ((value >> 8)&0xff))

typedef uint32_t CPU_Counter_ticks;

typedef CPU_Counter_ticks (*SPARC_Counter_difference)(
  CPU_Counter_ticks second,
  CPU_Counter_ticks first
);

/*
 * The SPARC processors supported by RTEMS have no built-in CPU counter
 * support.  We have to use some hardware counter module for this purpose.  The
 * BSP must provide a 32-bit register which contains the current CPU counter
 * value and a function for the difference calculation.  It can use for example
 * the GPTIMER instance used for the clock driver.
 */
typedef struct {
  volatile const CPU_Counter_ticks *counter_register;
  SPARC_Counter_difference counter_difference;
} SPARC_Counter;

extern SPARC_Counter _SPARC_Counter;

/*
 * Returns always a value of one regardless of the parameters.  This prevents
 * an infinite loop in rtems_counter_delay_ticks().  Its only a reasonably safe
 * default.
 */
CPU_Counter_ticks _SPARC_Counter_difference_default(
  CPU_Counter_ticks second,
  CPU_Counter_ticks first
);

static inline bool _SPARC_Counter_is_default( void )
{
  return _SPARC_Counter.counter_difference
    == _SPARC_Counter_difference_default;
}

static inline void _SPARC_Counter_initialize(
  volatile const CPU_Counter_ticks *counter_register,
  SPARC_Counter_difference counter_difference
)
{
  _SPARC_Counter.counter_register = counter_register;
  _SPARC_Counter.counter_difference = counter_difference;
}

static inline CPU_Counter_ticks _CPU_Counter_read( void )
{
  return *_SPARC_Counter.counter_register;
}

static inline CPU_Counter_ticks _CPU_Counter_difference(
  CPU_Counter_ticks second,
  CPU_Counter_ticks first
)
{
  return (*_SPARC_Counter.counter_difference)( second, first );
}

#endif /* ASM */

#ifdef __cplusplus
}
#endif

#endif