RTEMS CPU Kit with SuperCore  4.11.2
threaddispatch.h
Go to the documentation of this file.
1 
5 /*
6  * COPYRIGHT (c) 1989-2009.
7  * On-Line Applications Research Corporation (OAR).
8  *
9  * The license and distribution terms for this file may be
10  * found in the file LICENSE in this distribution or at
11  * http://www.rtems.org/license/LICENSE.
12  */
13 
14 #ifndef _RTEMS_SCORE_THREADDISPATCH_H
15 #define _RTEMS_SCORE_THREADDISPATCH_H
16 
17 #include <rtems/score/percpu.h>
18 #include <rtems/score/isrlock.h>
19 #include <rtems/score/profiling.h>
20 
21 #ifdef __cplusplus
22 extern "C" {
23 #endif /* __cplusplus */
24 
25 #if defined(RTEMS_HEAVY_STACK_DEBUG) || \
26  defined(RTEMS_HEAVY_MALLOC_DEBUG)
27  #define __THREAD_DO_NOT_INLINE_DISABLE_DISPATCH__
28 #endif
29 
30 #if defined(RTEMS_SMP) || \
31  (CPU_INLINE_ENABLE_DISPATCH == FALSE) || \
32  (__RTEMS_DO_NOT_INLINE_THREAD_ENABLE_DISPATCH__ == 1)
33  #define __THREAD_DO_NOT_INLINE_ENABLE_DISPATCH__
34 #endif
35 
51 {
52  bool enabled;
53 
54 #if defined(RTEMS_SMP)
55  ISR_Level level;
56 
57  _ISR_Disable_without_giant( level );
58 #endif
59 
60  enabled = _Thread_Dispatch_disable_level == 0;
61 
62 #if defined(RTEMS_SMP)
63  _ISR_Enable_without_giant( level );
64 #endif
65 
66  return enabled;
67 }
68 
75 {
76  return _Thread_Dispatch_disable_level;
77 }
78 
85 {
86  _Thread_Dispatch_disable_level = 1;
87 }
88 
89 #if defined(RTEMS_SMP)
90 
105  void _Giant_Acquire( Per_CPU_Control *cpu_self );
106 
117  void _Giant_Release( Per_CPU_Control *cpu_self );
118 
128  void _Giant_Drop( Per_CPU_Control *cpu_self );
129 
136 
143 #else /* RTEMS_SMP */
144 
150  {
151  uint32_t disable_level = _Thread_Dispatch_disable_level;
152 #if defined( RTEMS_PROFILING )
153  ISR_Level level;
154 
155  _ISR_Disable( level );
156  _Profiling_Thread_dispatch_disable( _Per_CPU_Get(), disable_level );
157 #endif
158 
159  ++disable_level;
160  _Thread_Dispatch_disable_level = disable_level;
161 
162 #if defined( RTEMS_PROFILING )
163  _ISR_Enable( level );
164 #endif
165 
166  return disable_level;
167  }
168 
175  {
176  uint32_t disable_level = _Thread_Dispatch_disable_level;
177 #if defined( RTEMS_PROFILING )
178  ISR_Level level;
179 
180  _ISR_Disable( level );
181 #endif
182 
183  --disable_level;
184  _Thread_Dispatch_disable_level = disable_level;
185 
186 #if defined( RTEMS_PROFILING )
187  _Profiling_Thread_dispatch_enable( _Per_CPU_Get(), disable_level );
188  _ISR_Enable( level );
189 #endif
190 
191  return disable_level;
192  }
193 
194  RTEMS_INLINE_ROUTINE void _Giant_Acquire( Per_CPU_Control *cpu_self )
195  {
196  (void) cpu_self;
197  }
198 
199  RTEMS_INLINE_ROUTINE void _Giant_Release( Per_CPU_Control *cpu_self )
200  {
201  (void) cpu_self;
202  }
203 #endif /* RTEMS_SMP */
204 
222 void _Thread_Dispatch( void );
223 
237 void _Thread_Do_dispatch( Per_CPU_Control *cpu_self, ISR_Level level );
238 
251  const ISR_lock_Context *lock_context
252 )
253 {
254  Per_CPU_Control *cpu_self;
255  uint32_t disable_level;
256 
257  cpu_self = _Per_CPU_Get();
258  disable_level = cpu_self->thread_dispatch_disable_level;
259  _Profiling_Thread_dispatch_disable_critical(
260  cpu_self,
261  disable_level,
262  lock_context
263  );
264  cpu_self->thread_dispatch_disable_level = disable_level + 1;
265 
266  return cpu_self;
267 }
268 
277 {
278  Per_CPU_Control *cpu_self;
279  ISR_lock_Context lock_context;
280 
281 #if defined( RTEMS_SMP ) || defined( RTEMS_PROFILING )
282  _ISR_lock_ISR_disable( &lock_context );
283 #endif
284 
285  cpu_self = _Thread_Dispatch_disable_critical( &lock_context );
286 
287 #if defined( RTEMS_SMP ) || defined( RTEMS_PROFILING )
288  _ISR_lock_ISR_enable( &lock_context );
289 #endif
290 
291  return cpu_self;
292 }
293 
304 {
305  uint32_t disable_level = cpu_self->thread_dispatch_disable_level;
306 
307  if ( disable_level == 1 ) {
308  ISR_Level level;
309 
310  _ISR_Disable_without_giant( level );
311 
312  if ( cpu_self->dispatch_necessary ) {
313  _Thread_Do_dispatch( cpu_self, level );
314  } else {
315  cpu_self->thread_dispatch_disable_level = 0;
316  _Profiling_Thread_dispatch_enable( cpu_self, 0 );
317  }
318 
319  _ISR_Enable_without_giant( level );
320  } else {
321  cpu_self->thread_dispatch_disable_level = disable_level - 1;
322  }
323 }
324 
328 #if defined ( __THREAD_DO_NOT_INLINE_DISABLE_DISPATCH__ )
329 void _Thread_Disable_dispatch( void );
330 #else
332 {
335 }
336 #endif
337 
338 RTEMS_INLINE_ROUTINE void _Thread_Enable_dispatch_body( void )
339 {
340  Per_CPU_Control *cpu_self = _Per_CPU_Get();
341 
342  _Giant_Release( cpu_self );
343  _Thread_Dispatch_enable( cpu_self );
344 }
345 
351 #if defined ( __THREAD_DO_NOT_INLINE_ENABLE_DISPATCH__ )
352  void _Thread_Enable_dispatch( void );
353 #else
354  /* inlining of enable dispatching must be true */
356  {
358  _Thread_Enable_dispatch_body();
359  }
360 #endif
361 
369 {
372 }
373 
376 #ifdef __cplusplus
377 }
378 #endif /* __cplusplus */
379 
380 #endif /* _RTEMS_SCORE_THREADDISPATCH_H */
RTEMS_INLINE_ROUTINE uint32_t _Thread_Dispatch_get_disable_level(void)
Gets thread dispatch disable level.
Definition: threaddispatch.h:75
RTEMS_INLINE_ROUTINE bool _Thread_Dispatch_is_enabled(void)
Indicates if the executing thread is inside a thread dispatch critical section.
Definition: threaddispatch.h:51
#define RTEMS_INLINE_ROUTINE
The following (in conjunction with compiler arguments) are used to choose between the use of static i...
Definition: basedefs.h:135
RTEMS_INLINE_ROUTINE void _Thread_Dispatch_enable(Per_CPU_Control *cpu_self)
Enables thread dispatching.
Definition: threaddispatch.h:304
RTEMS_INLINE_ROUTINE uint32_t _Thread_Dispatch_decrement_disable_level(void)
Decrease thread dispatch disable level.
Definition: threaddispatch.h:175
void _Thread_Dispatch(void)
Performs a thread dispatch if necessary.
Definition: threaddispatch.c:152
RTEMS_INLINE_ROUTINE Per_CPU_Control * _Thread_Dispatch_disable(void)
Disables thread dispatching.
Definition: threaddispatch.h:277
void _Thread_Enable_dispatch(void)
Enables thread dispatching and releases the Giant lock.
RTEMS_INLINE_ROUTINE void _Thread_Disable_dispatch(void)
Disables thread dispatching and acquires the Giant lock.
Definition: threaddispatch.h:332
This include file defines the per CPU information required by RTEMS.
#define _ISR_lock_ISR_disable(_context)
Disables interrupts and saves the previous interrupt state in the ISR lock context.
Definition: isrlock.h:337
uint32_t ISR_Level
The following type defines the control block used to manage the interrupt level portion of the status...
Definition: isrlevel.h:42
RTEMS_INLINE_ROUTINE void _Thread_Dispatch_initialization(void)
Thread dispatch initialization.
Definition: threaddispatch.h:85
#define _ISR_lock_ISR_enable(_context)
Restores the saved interrupt state of the ISR lock context.
Definition: isrlock.h:358
Per CPU Core Structure.
Definition: percpu.h:233
RTEMS_INLINE_ROUTINE void _Thread_Unnest_dispatch(void)
Enables thread dispatching and releases the Giant lock.
Definition: threaddispatch.h:369
RTEMS_INLINE_ROUTINE uint32_t _Thread_Dispatch_increment_disable_level(void)
Increase thread dispatch disable level.
Definition: threaddispatch.h:150
volatile bool dispatch_necessary
This is set to true when this processor needs to run the dispatcher.
Definition: percpu.h:308
#define _ISR_Enable(_level)
Enables interrupts on this processor.
Definition: isrlevel.h:76
volatile uint32_t thread_dispatch_disable_level
The thread dispatch critical section nesting counter which is used to prevent context switches at ino...
Definition: percpu.h:266
RTEMS_INLINE_ROUTINE Per_CPU_Control * _Thread_Dispatch_disable_critical(const ISR_lock_Context *lock_context)
Disables thread dispatching inside a critical section (interrupts disabled).
Definition: threaddispatch.h:251
Local ISR lock context for acquire and release pairs.
Definition: isrlock.h:65
void _Thread_Do_dispatch(Per_CPU_Control *cpu_self, ISR_Level level)
Performs a thread dispatch on the current processor.
Definition: threaddispatch.c:63
ISR Locks.
#define _ISR_Disable(_level)
Disables interrupts on this processor.
Definition: isrlevel.h:58
#define RTEMS_COMPILER_MEMORY_BARRIER()
The following macro is a compiler specific way to ensure that memory writes are not reordered around ...
Definition: basedefs.h:146
Profiling Support API.