RTEMS CPU Kit with SuperCore  4.11.2
cpu.h
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1 
5 /*
6  * This include file contains information pertaining to the Moxie
7  * processor.
8  *
9  * Copyright (c) 2013 Anthony Green
10  *
11  * Based on code with the following copyright..
12  * COPYRIGHT (c) 1989-2006, 2010.
13  * On-Line Applications Research Corporation (OAR).
14  *
15  * The license and distribution terms for this file may be
16  * found in the file LICENSE in this distribution or at
17  * http://www.rtems.org/license/LICENSE.
18  */
19 
20 #ifndef _RTEMS_SCORE_CPU_H
21 #define _RTEMS_SCORE_CPU_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 #include <rtems/score/types.h>
28 #include <rtems/score/moxie.h> /* pick up machine definitions */
29 
30 #include <rtems/bspIo.h> /* printk */
31 
32 /* conditional compilation parameters */
33 
34 /*
35  * Should the calls to _Thread_Enable_dispatch be inlined?
36  *
37  * If TRUE, then they are inlined.
38  * If FALSE, then a subroutine call is made.
39  *
40  * Basically this is an example of the classic trade-off of size
41  * versus speed. Inlining the call (TRUE) typically increases the
42  * size of RTEMS while speeding up the enabling of dispatching.
43  * [NOTE: In general, the _Thread_Dispatch_disable_level will
44  * only be 0 or 1 unless you are in an interrupt handler and that
45  * interrupt handler invokes the executive.] When not inlined
46  * something calls _Thread_Enable_dispatch which in turns calls
47  * _Thread_Dispatch. If the enable dispatch is inlined, then
48  * one subroutine call is avoided entirely.]
49  *
50  * MOXIE Specific Information:
51  *
52  * XXX
53  */
54 #define CPU_INLINE_ENABLE_DISPATCH FALSE
55 
56 /*
57  * Should this target use 16 or 32 bit object Ids?
58  *
59  */
60 #define RTEMS_USE_32_BIT_OBJECT
61 
62 /*
63  * Does RTEMS manage a dedicated interrupt stack in software?
64  *
65  * If TRUE, then a stack is allocated in _ISR_Handler_initialization.
66  * If FALSE, nothing is done.
67  *
68  * If the CPU supports a dedicated interrupt stack in hardware,
69  * then it is generally the responsibility of the BSP to allocate it
70  * and set it up.
71  *
72  * If the CPU does not support a dedicated interrupt stack, then
73  * the porter has two options: (1) execute interrupts on the
74  * stack of the interrupted task, and (2) have RTEMS manage a dedicated
75  * interrupt stack.
76  *
77  * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
78  *
79  * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
80  * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
81  * possible that both are FALSE for a particular CPU. Although it
82  * is unclear what that would imply about the interrupt processing
83  * procedure on that CPU.
84  *
85  * MOXIE Specific Information:
86  *
87  * XXX
88  */
89 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
90 
91 /*
92  * Does the CPU follow the simple vectored interrupt model?
93  *
94  * If TRUE, then RTEMS allocates the vector table it internally manages.
95  * If FALSE, then the BSP is assumed to allocate and manage the vector
96  * table
97  *
98  * MOXIE Specific Information:
99  *
100  * XXX document implementation including references if appropriate
101  */
102 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
103 
104 /*
105  * Does this CPU have hardware support for a dedicated interrupt stack?
106  *
107  * If TRUE, then it must be installed during initialization.
108  * If FALSE, then no installation is performed.
109  *
110  * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
111  *
112  * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
113  * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is
114  * possible that both are FALSE for a particular CPU. Although it
115  * is unclear what that would imply about the interrupt processing
116  * procedure on that CPU.
117  *
118  * MOXIE Specific Information:
119  *
120  * XXX
121  */
122 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
123 
124 /*
125  * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
126  *
127  * If TRUE, then the memory is allocated during initialization.
128  * If FALSE, then the memory is allocated during initialization.
129  *
130  * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
131  *
132  * MOXIE Specific Information:
133  *
134  * XXX
135  */
136 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
137 
138 /*
139  * Does the CPU have hardware floating point?
140  *
141  * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
142  * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
143  *
144  * If there is a FP coprocessor such as the i387 or mc68881, then
145  * the answer is TRUE.
146  *
147  * The macro name "MOXIE_HAS_FPU" should be made CPU specific.
148  * It indicates whether or not this CPU model has FP support. For
149  * example, it would be possible to have an i386_nofp CPU model
150  * which set this to false to indicate that you have an i386 without
151  * an i387 and wish to leave floating point support out of RTEMS.
152  *
153  * MOXIE Specific Information:
154  *
155  * XXX
156  */
157 #define CPU_HARDWARE_FP FALSE
158 
159 /*
160  * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
161  *
162  * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
163  * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
164  *
165  * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
166  *
167  * MOXIE Specific Information:
168  *
169  * XXX
170  */
171 #define CPU_ALL_TASKS_ARE_FP FALSE
172 
173 /*
174  * Should the IDLE task have a floating point context?
175  *
176  * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
177  * and it has a floating point context which is switched in and out.
178  * If FALSE, then the IDLE task does not have a floating point context.
179  *
180  * Setting this to TRUE negatively impacts the time required to preempt
181  * the IDLE task from an interrupt because the floating point context
182  * must be saved as part of the preemption.
183  *
184  * MOXIE Specific Information:
185  *
186  * XXX
187  */
188 #define CPU_IDLE_TASK_IS_FP FALSE
189 
190 /*
191  * Should the saving of the floating point registers be deferred
192  * until a context switch is made to another different floating point
193  * task?
194  *
195  * If TRUE, then the floating point context will not be stored until
196  * necessary. It will remain in the floating point registers and not
197  * disturned until another floating point task is switched to.
198  *
199  * If FALSE, then the floating point context is saved when a floating
200  * point task is switched out and restored when the next floating point
201  * task is restored. The state of the floating point registers between
202  * those two operations is not specified.
203  *
204  * If the floating point context does NOT have to be saved as part of
205  * interrupt dispatching, then it should be safe to set this to TRUE.
206  *
207  * Setting this flag to TRUE results in using a different algorithm
208  * for deciding when to save and restore the floating point context.
209  * The deferred FP switch algorithm minimizes the number of times
210  * the FP context is saved and restored. The FP context is not saved
211  * until a context switch is made to another, different FP task.
212  * Thus in a system with only one FP task, the FP context will never
213  * be saved or restored.
214  *
215  * MOXIE Specific Information:
216  *
217  * XXX
218  */
219 #define CPU_USE_DEFERRED_FP_SWITCH TRUE
220 
221 /*
222  * Does this port provide a CPU dependent IDLE task implementation?
223  *
224  * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
225  * must be provided and is the default IDLE thread body instead of
226  * _Internal_threads_Idle_thread_body.
227  *
228  * If FALSE, then use the generic IDLE thread body if the BSP does
229  * not provide one.
230  *
231  * This is intended to allow for supporting processors which have
232  * a low power or idle mode. When the IDLE thread is executed, then
233  * the CPU can be powered down.
234  *
235  * The order of precedence for selecting the IDLE thread body is:
236  *
237  * 1. BSP provided
238  * 2. CPU dependent (if provided)
239  * 3. generic (if no BSP and no CPU dependent)
240  *
241  * MOXIE Specific Information:
242  *
243  * XXX
244  * The port initially called a BSP dependent routine called
245  * IDLE_Monitor. The idle task body can be overridden by
246  * the BSP in newer versions of RTEMS.
247  */
248 #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
249 
250 /*
251  * Does the stack grow up (toward higher addresses) or down
252  * (toward lower addresses)?
253  *
254  * If TRUE, then the grows upward.
255  * If FALSE, then the grows toward smaller addresses.
256  *
257  * MOXIE Specific Information:
258  *
259  * XXX
260  */
261 #define CPU_STACK_GROWS_UP FALSE
262 
263 /*
264  * The following is the variable attribute used to force alignment
265  * of critical RTEMS structures. On some processors it may make
266  * sense to have these aligned on tighter boundaries than
267  * the minimum requirements of the compiler in order to have as
268  * much of the critical data area as possible in a cache line.
269  *
270  * The placement of this macro in the declaration of the variables
271  * is based on the syntactically requirements of the GNU C
272  * "__attribute__" extension. For example with GNU C, use
273  * the following to force a structures to a 32 byte boundary.
274  *
275  * __attribute__ ((aligned (32)))
276  *
277  * NOTE: Currently only the Priority Bit Map table uses this feature.
278  * To benefit from using this, the data must be heavily
279  * used so it will stay in the cache and used frequently enough
280  * in the executive to justify turning this on.
281  *
282  * MOXIE Specific Information:
283  *
284  * XXX
285  */
286 #define CPU_STRUCTURE_ALIGNMENT
287 
288 #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
289 #define CPU_TIMESTAMP_USE_INT64 FALSE
290 #define CPU_TIMESTAMP_USE_INT64_INLINE FALSE
291 
292 /*
293  * Define what is required to specify how the network to host conversion
294  * routines are handled.
295  */
296 #define CPU_BIG_ENDIAN TRUE
297 #define CPU_LITTLE_ENDIAN FALSE
298 
299 /*
300  * The following defines the number of bits actually used in the
301  * interrupt field of the task mode. How those bits map to the
302  * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
303  *
304  * MOXIE Specific Information:
305  *
306  * XXX
307  */
308 #define CPU_MODES_INTERRUPT_MASK 0x00000001
309 
310 #define CPU_PER_CPU_CONTROL_SIZE 0
311 
312 /*
313  * Processor defined structures required for cpukit/score.
314  *
315  * MOXIE Specific Information:
316  *
317  * XXX
318  */
319 
320 /* may need to put some structures here. */
321 
322 /*
323  * Contexts
324  *
325  * Generally there are 2 types of context to save.
326  * 1. Interrupt registers to save
327  * 2. Task level registers to save
328  *
329  * This means we have the following 3 context items:
330  * 1. task level context stuff:: Context_Control
331  * 2. floating point task stuff:: Context_Control_fp
332  * 3. special interrupt level context :: Context_Control_interrupt
333  *
334  * On some processors, it is cost-effective to save only the callee
335  * preserved registers during a task context switch. This means
336  * that the ISR code needs to save those registers which do not
337  * persist across function calls. It is not mandatory to make this
338  * distinctions between the caller/callee saves registers for the
339  * purpose of minimizing context saved during task switch and on interrupts.
340  * If the cost of saving extra registers is minimal, simplicity is the
341  * choice. Save the same context on interrupt entry as for tasks in
342  * this case.
343  *
344  * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
345  * care should be used in designing the context area.
346  *
347  * On some CPUs with hardware floating point support, the Context_Control_fp
348  * structure will not be used or it simply consist of an array of a
349  * fixed number of bytes. This is done when the floating point context
350  * is dumped by a "FP save context" type instruction and the format
351  * is not really defined by the CPU. In this case, there is no need
352  * to figure out the exact format -- only the size. Of course, although
353  * this is enough information for RTEMS, it is probably not enough for
354  * a debugger such as gdb. But that is another problem.
355  *
356  * MOXIE Specific Information:
357  *
358  * XXX
359  */
360 
361 #define nogap __attribute__ ((packed))
362 
363 typedef struct {
364  void *fp nogap;
365  void *sp nogap;
366  uint32_t r0 nogap;
367  uint32_t r1 nogap;
368  uint32_t r2 nogap;
369  uint32_t r3 nogap;
370  uint32_t r4 nogap;
371  uint32_t r5 nogap;
372  uint32_t r6 nogap;
373  uint32_t r7 nogap;
374  uint32_t r8 nogap;
375  uint32_t r9 nogap;
376  uint32_t r10 nogap;
377  uint32_t r11 nogap;
378  uint32_t r12 nogap;
379  uint32_t r13 nogap;
381 
382 #define _CPU_Context_Get_SP( _context ) \
383  (_context)->sp
384 
385 typedef struct {
386  double some_float_register[2];
388 
389 typedef struct {
390  uint32_t special_interrupt_register;
392 
393 /*
394  * This variable is optional. It is used on CPUs on which it is difficult
395  * to generate an "uninitialized" FP context. It is filled in by
396  * _CPU_Initialize and copied into the task's FP context area during
397  * _CPU_Context_Initialize.
398  *
399  * MOXIE Specific Information:
400  *
401  * XXX
402  */
404 
405 /*
406  * Nothing prevents the porter from declaring more CPU specific variables.
407  *
408  * MOXIE Specific Information:
409  *
410  * XXX
411  */
412 
413 /*
414  * The size of the floating point context area. On some CPUs this
415  * will not be a "sizeof" because the format of the floating point
416  * area is not defined -- only the size is. This is usually on
417  * CPUs with a "floating point save context" instruction.
418  *
419  * MOXIE Specific Information:
420  *
421  * XXX
422  */
423 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
424 
425 /*
426  * Amount of extra stack (above minimum stack size) required by
427  * system initialization thread. Remember that in a multiprocessor
428  * system the system intialization thread becomes the MP server thread.
429  *
430  * MOXIE Specific Information:
431  *
432  * It is highly unlikely the MOXIE will get used in a multiprocessor system.
433  */
434 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
435 
436 /*
437  * This defines the number of entries in the ISR_Vector_table managed
438  * by RTEMS.
439  *
440  * MOXIE Specific Information:
441  *
442  * XXX
443  */
444 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 64
445 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER \
446  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
447 
448 /*
449  * This is defined if the port has a special way to report the ISR nesting
450  * level. Most ports maintain the variable _ISR_Nest_level.
451  */
452 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
453 
454 /*
455  * Should be large enough to run all RTEMS tests. This ensures
456  * that a "reasonable" small application should not have any problems.
457  *
458  * MOXIE Specific Information:
459  *
460  * XXX
461  */
462 #define CPU_STACK_MINIMUM_SIZE (1536)
463 
471 #define CPU_SIZEOF_POINTER 4
472 
473 /*
474  * CPU's worst alignment requirement for data types on a byte boundary. This
475  * alignment does not take into account the requirements for the stack.
476  *
477  * MOXIE Specific Information:
478  *
479  * XXX
480  */
481 #define CPU_ALIGNMENT 8
482 
483 /*
484  * This number corresponds to the byte alignment requirement for the
485  * heap handler. This alignment requirement may be stricter than that
486  * for the data types alignment specified by CPU_ALIGNMENT. It is
487  * common for the heap to follow the same alignment requirement as
488  * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
489  * then this should be set to CPU_ALIGNMENT.
490  *
491  * NOTE: This does not have to be a power of 2. It does have to
492  * be greater or equal to than CPU_ALIGNMENT.
493  *
494  * MOXIE Specific Information:
495  *
496  * XXX
497  */
498 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
499 
500 /*
501  * This number corresponds to the byte alignment requirement for memory
502  * buffers allocated by the partition manager. This alignment requirement
503  * may be stricter than that for the data types alignment specified by
504  * CPU_ALIGNMENT. It is common for the partition to follow the same
505  * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict
506  * enough for the partition, then this should be set to CPU_ALIGNMENT.
507  *
508  * NOTE: This does not have to be a power of 2. It does have to
509  * be greater or equal to than CPU_ALIGNMENT.
510  *
511  * MOXIE Specific Information:
512  *
513  * XXX
514  */
515 #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
516 
517 /*
518  * This number corresponds to the byte alignment requirement for the
519  * stack. This alignment requirement may be stricter than that for the
520  * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT
521  * is strict enough for the stack, then this should be set to 0.
522  *
523  * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
524  *
525  * MOXIE Specific Information:
526  *
527  * XXX
528  */
529 #define CPU_STACK_ALIGNMENT 0
530 
531 /*
532  * ISR handler macros
533  */
534 
535 /*
536  * Support routine to initialize the RTEMS vector table after it is allocated.
537  */
538 #define _CPU_Initialize_vectors()
539 
540 /*
541  * Disable all interrupts for an RTEMS critical section. The previous
542  * level is returned in _level.
543  *
544  * MOXIE Specific Information:
545  *
546  * TODO: As of 7 October 2014, this method is not implemented.
547  */
548 #define _CPU_ISR_Disable( _isr_cookie ) \
549  do { \
550  (_isr_cookie) = 0; \
551  } while (0)
552 
553 /*
554  * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
555  * This indicates the end of an RTEMS critical section. The parameter
556  * _level is not modified.
557  *
558  * MOXIE Specific Information:
559  *
560  * TODO: As of 7 October 2014, this method is not implemented.
561  */
562 #define _CPU_ISR_Enable( _isr_cookie ) \
563  do { \
564  (_isr_cookie) = (_isr_cookie); \
565  } while (0)
566 
567 /*
568  * This temporarily restores the interrupt to _level before immediately
569  * disabling them again. This is used to divide long RTEMS critical
570  * sections into two or more parts. The parameter _level is not
571  * modified.
572  *
573  * MOXIE Specific Information:
574  *
575  * TODO: As of 7 October 2014, this method is not implemented.
576  */
577 #define _CPU_ISR_Flash( _isr_cookie ) \
578  do { \
579  _CPU_ISR_Enable( _isr_cookie ); \
580  _CPU_ISR_Disable( _isr_cookie ); \
581  } while (0)
582 
583 /*
584  * Map interrupt level in task mode onto the hardware that the CPU
585  * actually provides. Currently, interrupt levels which do not
586  * map onto the CPU in a generic fashion are undefined. Someday,
587  * it would be nice if these were "mapped" by the application
588  * via a callout. For example, m68k has 8 levels 0 - 7, levels
589  * 8 - 255 would be available for bsp/application specific meaning.
590  * This could be used to manage a programmable interrupt controller
591  * via the rtems_task_mode directive.
592  *
593  * MOXIE Specific Information:
594  *
595  * TODO: As of 7 October 2014, this method is not implemented.
596  */
597 #define _CPU_ISR_Set_level( _new_level ) \
598  { \
599  if (_new_level) asm volatile ( "nop\n" ); \
600  else asm volatile ( "nop\n" ); \
601  }
602 
603 uint32_t _CPU_ISR_Get_level( void );
604 
605 /* end of ISR handler macros */
606 
607 /* Context handler macros */
608 
609 /*
610  * Initialize the context to a state suitable for starting a
611  * task after a context restore operation. Generally, this
612  * involves:
613  *
614  * - setting a starting address
615  * - preparing the stack
616  * - preparing the stack and frame pointers
617  * - setting the proper interrupt level in the context
618  * - initializing the floating point context
619  *
620  * This routine generally does not set any unnecessary register
621  * in the context. The state of the "general data" registers is
622  * undefined at task start time.
623  *
624  * NOTE: This is_fp parameter is TRUE if the thread is to be a floating
625  * point thread. This is typically only used on CPUs where the
626  * FPU may be easily disabled by software such as on the SPARC
627  * where the PSR contains an enable FPU bit.
628  *
629  * MOXIE Specific Information:
630  *
631  * TODO: As of 7 October 2014, this method does not ensure that the context
632  * is set up with interrupts disabled/enabled as requested.
633  */
634 #define CPU_CCR_INTERRUPTS_ON 0x80
635 #define CPU_CCR_INTERRUPTS_OFF 0x00
636 
637 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
638  _isr, _entry_point, _is_fp, _tls_area ) \
639  /* Locate Me */ \
640  do { \
641  uintptr_t _stack; \
642  \
643  (void) _is_fp; /* avoid warning for being unused */ \
644  (void) _isr; /* avoid warning for being unused */ \
645  _stack = ((uintptr_t)(_stack_base)) + (_size) - 8; \
646  *((proc_ptr *)(_stack)) = (_entry_point); \
647  _stack -= 4; \
648  (_the_context)->fp = (void *)_stack; \
649  (_the_context)->sp = (void *)_stack; \
650  } while (0)
651 
652 
653 /*
654  * This routine is responsible for somehow restarting the currently
655  * executing task. If you are lucky, then all that is necessary
656  * is restoring the context. Otherwise, there will need to be
657  * a special assembly routine which does something special in this
658  * case. Context_Restore should work most of the time. It will
659  * not work if restarting self conflicts with the stack frame
660  * assumptions of restoring a context.
661  *
662  * MOXIE Specific Information:
663  *
664  * XXX
665  */
666 #define _CPU_Context_Restart_self( _the_context ) \
667  _CPU_Context_restore( (_the_context) );
668 
669 /*
670  * The purpose of this macro is to allow the initial pointer into
671  * a floating point context area (used to save the floating point
672  * context) to be at an arbitrary place in the floating point
673  * context area.
674  *
675  * This is necessary because some FP units are designed to have
676  * their context saved as a stack which grows into lower addresses.
677  * Other FP units can be saved by simply moving registers into offsets
678  * from the base of the context area. Finally some FP units provide
679  * a "dump context" instruction which could fill in from high to low
680  * or low to high based on the whim of the CPU designers.
681  *
682  * MOXIE Specific Information:
683  *
684  * XXX
685  */
686 #define _CPU_Context_Fp_start( _base, _offset ) \
687  ( (void *) (_base) + (_offset) )
688 
689 /*
690  * This routine initializes the FP context area passed to it to.
691  * There are a few standard ways in which to initialize the
692  * floating point context. The code included for this macro assumes
693  * that this is a CPU in which a "initial" FP context was saved into
694  * _CPU_Null_fp_context and it simply copies it to the destination
695  * context passed to it.
696  *
697  * Other models include (1) not doing anything, and (2) putting
698  * a "null FP status word" in the correct place in the FP context.
699  *
700  * MOXIE Specific Information:
701  *
702  * XXX
703  */
704 #define _CPU_Context_Initialize_fp( _destination ) \
705  { \
706  *(*(_destination)) = _CPU_Null_fp_context; \
707  }
708 
709 /* end of Context handler macros */
710 
711 /* Fatal Error manager macros */
712 
713 /*
714  * This routine copies _error into a known place -- typically a stack
715  * location or a register, optionally disables interrupts, and
716  * halts/stops the CPU.
717  *
718  * MOXIE Specific Information:
719  *
720  * XXX
721  */
722 #define _CPU_Fatal_halt( _source, _error ) \
723  printk("Fatal Error %d.%d Halted\n",_source,_error); \
724  for(;;)
725 
726 /* end of Fatal Error manager macros */
727 
728 /* Bitfield handler macros */
729 
730 /*
731  * This routine sets _output to the bit number of the first bit
732  * set in _value. _value is of CPU dependent type Priority_Bit_map_control.
733  * This type may be either 16 or 32 bits wide although only the 16
734  * least significant bits will be used.
735  *
736  * There are a number of variables in using a "find first bit" type
737  * instruction.
738  *
739  * (1) What happens when run on a value of zero?
740  * (2) Bits may be numbered from MSB to LSB or vice-versa.
741  * (3) The numbering may be zero or one based.
742  * (4) The "find first bit" instruction may search from MSB or LSB.
743  *
744  * RTEMS guarantees that (1) will never happen so it is not a concern.
745  * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
746  * _CPU_Priority_bits_index(). These three form a set of routines
747  * which must logically operate together. Bits in the _value are
748  * set and cleared based on masks built by _CPU_Priority_mask().
749  * The basic major and minor values calculated by _Priority_Major()
750  * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
751  * to properly range between the values returned by the "find first bit"
752  * instruction. This makes it possible for _Priority_Get_highest() to
753  * calculate the major and directly index into the minor table.
754  * This mapping is necessary to ensure that 0 (a high priority major/minor)
755  * is the first bit found.
756  *
757  * This entire "find first bit" and mapping process depends heavily
758  * on the manner in which a priority is broken into a major and minor
759  * components with the major being the 4 MSB of a priority and minor
760  * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
761  * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next
762  * to the lowest priority.
763  *
764  * If your CPU does not have a "find first bit" instruction, then
765  * there are ways to make do without it. Here are a handful of ways
766  * to implement this in software:
767  *
768  * - a series of 16 bit test instructions
769  * - a "binary search using if's"
770  * - _number = 0
771  * if _value > 0x00ff
772  * _value >>=8
773  * _number = 8;
774  *
775  * if _value > 0x0000f
776  * _value >=8
777  * _number += 4
778  *
779  * _number += bit_set_table[ _value ]
780  *
781  * where bit_set_table[ 16 ] has values which indicate the first
782  * bit set
783  *
784  * MOXIE Specific Information:
785  *
786  * XXX
787  */
788 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
789 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
790 
791 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
792 
793 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \
794  { \
795  (_output) = 0; /* do something to prevent warnings */ \
796  }
797 
798 #endif
799 
800 /* end of Bitfield handler macros */
801 
802 /*
803  * This routine builds the mask which corresponds to the bit fields
804  * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion
805  * for that routine.
806  *
807  * MOXIE Specific Information:
808  *
809  * XXX
810  */
811 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
812 
813 #define _CPU_Priority_Mask( _bit_number ) \
814  ( 1 << (_bit_number) )
815 
816 #endif
817 
818 /*
819  * This routine translates the bit numbers returned by
820  * _CPU_Bitfield_Find_first_bit() into something suitable for use as
821  * a major or minor component of a priority. See the discussion
822  * for that routine.
823  *
824  * MOXIE Specific Information:
825  *
826  * XXX
827  */
828 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
829 
830 #define _CPU_Priority_bits_index( _priority ) \
831  (_priority)
832 
833 #endif
834 
835 /* end of Priority handler macros */
836 
837 /* functions */
838 
839 /*
840  * _CPU_Initialize
841  *
842  * This routine performs CPU dependent initialization.
843  *
844  * MOXIE Specific Information:
845  *
846  * XXX
847  */
848 void _CPU_Initialize(void);
849 
850 /*
851  * _CPU_ISR_install_raw_handler
852  *
853  * This routine installs a "raw" interrupt handler directly into the
854  * processor's vector table.
855  *
856  * MOXIE Specific Information:
857  *
858  * XXX
859  */
861  uint32_t vector,
862  proc_ptr new_handler,
863  proc_ptr *old_handler
864 );
865 
866 /*
867  * _CPU_ISR_install_vector
868  *
869  * This routine installs an interrupt vector.
870  *
871  * MOXIE Specific Information:
872  *
873  * XXX
874  */
876  uint32_t vector,
877  proc_ptr new_handler,
878  proc_ptr *old_handler
879 );
880 
881 /*
882  * _CPU_Install_interrupt_stack
883  *
884  * This routine installs the hardware interrupt stack pointer.
885  *
886  * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
887  * is TRUE.
888  *
889  * MOXIE Specific Information:
890  *
891  * XXX
892  */
893 void _CPU_Install_interrupt_stack( void );
894 
895 /*
896  * _CPU_Internal_threads_Idle_thread_body
897  *
898  * This routine is the CPU dependent IDLE thread body.
899  *
900  * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
901  * is TRUE.
902  *
903  * MOXIE Specific Information:
904  *
905  * XXX
906  */
907 void *_CPU_Thread_Idle_body( uint32_t );
908 
909 /*
910  * _CPU_Context_switch
911  *
912  * This routine switches from the run context to the heir context.
913  *
914  * MOXIE Specific Information:
915  *
916  * XXX
917  */
919  Context_Control *run,
920  Context_Control *heir
921 );
922 
923 /*
924  * _CPU_Context_restore
925  *
926  * This routine is generallu used only to restart self in an
927  * efficient manner. It may simply be a label in _CPU_Context_switch.
928  *
929  * NOTE: May be unnecessary to reload some registers.
930  *
931  * MOXIE Specific Information:
932  *
933  * XXX
934  */
936  Context_Control *new_context
938 
939 /*
940  * _CPU_Context_save_fp
941  *
942  * This routine saves the floating point context passed to it.
943  *
944  * MOXIE Specific Information:
945  *
946  * XXX
947  */
949  Context_Control_fp **fp_context_ptr
950 );
951 
952 /*
953  * _CPU_Context_restore_fp
954  *
955  * This routine restores the floating point context passed to it.
956  *
957  * MOXIE Specific Information:
958  *
959  * XXX
960  */
962  Context_Control_fp **fp_context_ptr
963 );
964 
965 static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
966 {
967  /* TODO */
968 }
969 
970 static inline void _CPU_Context_validate( uintptr_t pattern )
971 {
972  while (1) {
973  /* TODO */
974  }
975 }
976 
986 typedef struct {
987  uint32_t integer_registers [16];
989 
996 
997 /* The following routine swaps the endian format of an unsigned int.
998  * It must be static because it is referenced indirectly.
999  *
1000  * This version will work on any processor, but if there is a better
1001  * way for your CPU PLEASE use it. The most common way to do this is to:
1002  *
1003  * swap least significant two bytes with 16-bit rotate
1004  * swap upper and lower 16-bits
1005  * swap most significant two bytes with 16-bit rotate
1006  *
1007  * Some CPUs have special instructions which swap a 32-bit quantity in
1008  * a single instruction (e.g. i486). It is probably best to avoid
1009  * an "endian swapping control bit" in the CPU. One good reason is
1010  * that interrupts would probably have to be disabled to ensure that
1011  * an interrupt does not try to access the same "chunk" with the wrong
1012  * endian. Another good reason is that on some CPUs, the endian bit
1013  * endianness for ALL fetches -- both code and data -- so the code
1014  * will be fetched incorrectly.
1015  *
1016  * MOXIE Specific Information:
1017  *
1018  * This is the generic implementation.
1019  */
1020 static inline uint32_t CPU_swap_u32(
1021  uint32_t value
1022 )
1023 {
1024  uint32_t byte1, byte2, byte3, byte4, swapped;
1025 
1026  byte4 = (value >> 24) & 0xff;
1027  byte3 = (value >> 16) & 0xff;
1028  byte2 = (value >> 8) & 0xff;
1029  byte1 = value & 0xff;
1030 
1031  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1032  return( swapped );
1033 }
1034 
1035 #define CPU_swap_u16( value ) \
1036  (((value&0xff) << 8) | ((value >> 8)&0xff))
1037 
1038 typedef uint32_t CPU_Counter_ticks;
1039 
1040 CPU_Counter_ticks _CPU_Counter_read( void );
1041 
1042 static inline CPU_Counter_ticks _CPU_Counter_difference(
1043  CPU_Counter_ticks second,
1044  CPU_Counter_ticks first
1045 )
1046 {
1047  return second - first;
1048 }
1049 
1050 #ifdef __cplusplus
1051 }
1052 #endif
1053 
1054 #endif
void _CPU_ISR_install_vector(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs an interrupt vector.
Definition: cpu.c:69
void _CPU_Context_validate(uintptr_t pattern)
Initializes and validates the CPU context with values derived from the pattern parameter.
Definition: cpu.h:1109
uint32_t _CPU_ISR_Get_level(void)
Return the current interrupt disable level for this task in the format used by the interrupt level po...
Definition: cpu.c:39
void _CPU_Context_restore(Context_Control *new_context)
This routine is generally used only to restart self in an efficient manner.
Definition: cpu_asm.c:112
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:92
void _CPU_Context_volatile_clobber(uintptr_t pattern)
Clobbers all volatile registers with values derived from the pattern parameter.
Definition: cpu.h:1104
This defines the minimal set of integer and processor state registers that must be saved during a vol...
Definition: cpu.h:248
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:26
void _CPU_Install_interrupt_stack(void)
This routine installs the hardware interrupt stack pointer.
Definition: cpu.c:101
SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context
This variable is optional.
Definition: cpu.h:494
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1461
This defines the set of integer and processor state registers that must be saved during an interrupt...
Definition: cpu.h:425
void _CPU_ISR_install_raw_handler(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs a "raw" interrupt handler directly into the processor&#39;s vector table...
Definition: cpu.c:57
void _CPU_Context_restore_fp(Context_Control_fp **fp_context_ptr)
This routine restores the floating point context passed to it.
Definition: cpu.c:176
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: cpu.c:96
CPU_Counter_ticks _CPU_Counter_difference(CPU_Counter_ticks second, CPU_Counter_ticks first)
Returns the difference between the second and first CPU counter value.
Definition: cpu.h:1160
This defines the complete set of floating point registers that must be saved during any context switc...
Definition: cpu.h:294
Interface to Kernel Print Methods.
void _CPU_Context_save_fp(Context_Control_fp **fp_context_ptr)
This routine saves the floating point context passed to it.
Definition: cpu.c:167
#define RTEMS_COMPILER_NO_RETURN_ATTRIBUTE
The following macro is a compiler specific way to indicate that the method will NOT return to the cal...
Definition: basedefs.h:162
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: arm-exception-frame-print.c:46
void * _CPU_Thread_Idle_body(uintptr_t ignored)
This routine is the CPU dependent IDLE thread body.
Definition: cpu.c:125
The set of registers that specifies the complete processor state.
Definition: cpu.h:671
#define SCORE_EXTERN
The following ensures that all data is declared in the space of the initialization routine for either...
Definition: basedefs.h:81
void * proc_ptr
XXX: Eventually proc_ptr needs to disappear!!!
Definition: basedefs.h:329