19 #ifndef _RTEMS_SCORE_CPU_H 20 #define _RTEMS_SCORE_CPU_H 63 #if SPARC_HAS_FPU == 1 64 #if defined(RTEMS_SMP) 65 #define SPARC_USE_SYNCHRONOUS_FP_SWITCH 67 #define SPARC_USE_LAZY_FP_SWITCH 81 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE 91 #define CPU_ISR_PASSES_FRAME_POINTER FALSE 101 #if ( SPARC_HAS_FPU == 1 ) && !defined(SPARC_USE_SYNCHRONOUS_FP_SWITCH) 102 #define CPU_HARDWARE_FP TRUE 104 #define CPU_HARDWARE_FP FALSE 111 #define CPU_SOFTWARE_FP FALSE 121 #define CPU_ALL_TASKS_ARE_FP FALSE 132 #define CPU_IDLE_TASK_IS_FP FALSE 134 #define CPU_USE_DEFERRED_FP_SWITCH FALSE 136 #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE 147 #define CPU_STACK_GROWS_UP FALSE 150 #define CPU_CACHE_LINE_BYTES 64 152 #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) 161 #define CPU_MODES_INTERRUPT_MASK 0x0000000F 229 #define CPU_STACK_FRAME_L0_OFFSET 0x00 231 #define CPU_STACK_FRAME_L1_OFFSET 0x04 233 #define CPU_STACK_FRAME_L2_OFFSET 0x08 235 #define CPU_STACK_FRAME_L3_OFFSET 0x0c 237 #define CPU_STACK_FRAME_L4_OFFSET 0x10 239 #define CPU_STACK_FRAME_L5_OFFSET 0x14 241 #define CPU_STACK_FRAME_L6_OFFSET 0x18 243 #define CPU_STACK_FRAME_L7_OFFSET 0x1c 245 #define CPU_STACK_FRAME_I0_OFFSET 0x20 247 #define CPU_STACK_FRAME_I1_OFFSET 0x24 249 #define CPU_STACK_FRAME_I2_OFFSET 0x28 251 #define CPU_STACK_FRAME_I3_OFFSET 0x2c 253 #define CPU_STACK_FRAME_I4_OFFSET 0x30 255 #define CPU_STACK_FRAME_I5_OFFSET 0x34 257 #define CPU_STACK_FRAME_I6_FP_OFFSET 0x38 259 #define CPU_STACK_FRAME_I7_OFFSET 0x3c 261 #define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40 263 #define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44 265 #define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48 267 #define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c 269 #define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50 271 #define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54 273 #define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58 275 #define CPU_STACK_FRAME_PAD0_OFFSET 0x5c 277 #define CPU_MAXIMUM_PROCESSORS 32 377 uint32_t isr_dispatch_disable;
379 #if defined(SPARC_USE_LAZY_FP_SWITCH) 383 #if defined(RTEMS_SMP) 384 volatile uint32_t is_executing;
393 #define _CPU_Context_Get_SP( _context ) \ 397 static inline bool _CPU_Context_Get_is_executing(
401 return context->is_executing;
404 static inline void _CPU_Context_Set_is_executing(
409 context->is_executing = is_executing;
420 #define G5_OFFSET 0x00 422 #define G7_OFFSET 0x04 425 #define L0_OFFSET 0x08 427 #define L1_OFFSET 0x0C 429 #define L2_OFFSET 0x10 431 #define L3_OFFSET 0x14 433 #define L4_OFFSET 0x18 435 #define L5_OFFSET 0x1C 437 #define L6_OFFSET 0x20 439 #define L7_OFFSET 0x24 442 #define I0_OFFSET 0x28 444 #define I1_OFFSET 0x2C 446 #define I2_OFFSET 0x30 448 #define I3_OFFSET 0x34 450 #define I4_OFFSET 0x38 452 #define I5_OFFSET 0x3C 454 #define I6_FP_OFFSET 0x40 456 #define I7_OFFSET 0x44 459 #define O6_SP_OFFSET 0x48 461 #define O7_OFFSET 0x4C 464 #define PSR_OFFSET 0x50 466 #define ISR_DISPATCH_DISABLE_STACK_OFFSET 0x54 468 #if defined(RTEMS_SMP) 469 #define SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 0x58 522 #define FO_F1_OFFSET 0x00 524 #define F2_F3_OFFSET 0x08 526 #define F4_F5_OFFSET 0x10 528 #define F6_F7_OFFSET 0x18 530 #define F8_F9_OFFSET 0x20 532 #define F1O_F11_OFFSET 0x28 534 #define F12_F13_OFFSET 0x30 536 #define F14_F15_OFFSET 0x38 538 #define F16_F17_OFFSET 0x40 540 #define F18_F19_OFFSET 0x48 542 #define F2O_F21_OFFSET 0x50 544 #define F22_F23_OFFSET 0x58 546 #define F24_F25_OFFSET 0x60 548 #define F26_F27_OFFSET 0x68 550 #define F28_F29_OFFSET 0x70 552 #define F3O_F31_OFFSET 0x78 554 #define FSR_OFFSET 0x80 557 #define CONTEXT_CONTROL_FP_SIZE 0x84 652 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) 661 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 686 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 692 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511 698 #define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x100 703 #define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) 708 #define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 256 ) 713 #define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 256) 719 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE 729 #define CPU_STACK_MINIMUM_SIZE (1024*4) 734 #define CPU_SIZEOF_POINTER 4 742 #define CPU_ALIGNMENT 8 755 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT 761 #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT 763 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 774 #define _CPU_Initialize_vectors() 780 #define _CPU_ISR_Disable( _level ) \ 781 (_level) = sparc_disable_interrupts() 788 #define _CPU_ISR_Enable( _level ) \ 789 sparc_enable_interrupts( _level ) 797 #define _CPU_ISR_Flash( _level ) \ 798 sparc_flash_interrupts( _level ) 800 #define _CPU_ISR_Is_enabled( _isr_cookie ) \ 801 sparc_interrupt_is_enabled( _isr_cookie ) 813 #define _CPU_ISR_Set_level( _newlevel ) \ 814 sparc_enable_interrupts( _newlevel << 8) 852 uint32_t *stack_base,
873 #define _CPU_Context_Initialization_at_thread_begin() \ 875 __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \ 886 #define _CPU_Context_Restart_self( _the_context ) \ 887 _CPU_Context_restore( (_the_context) ); 892 #define _CPU_Context_Initialize_fp( _destination ) \ 898 #define _CPU_Context_save_fp( _fp_context_ptr ) \ 904 #define _CPU_Context_restore_fp( _fp_context_ptr ) \ 922 #if ( SPARC_HAS_BITSCAN == 0 ) 927 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE 929 #error "scan instruction not currently supported by RTEMS!!" 943 typedef void ( *CPU_ISR_raw_handler )( void );
957 CPU_ISR_raw_handler new_handler,
958 CPU_ISR_raw_handler *old_handler
961 typedef void ( *CPU_ISR_handler )( uint32_t );
975 CPU_ISR_handler new_handler,
976 CPU_ISR_handler *old_handler
1006 #if defined(RTEMS_SMP) 1007 uint32_t _CPU_SMP_Initialize(
void );
1009 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1011 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1013 void _CPU_SMP_Prepare_start_multitasking(
void );
1015 #if defined(__leon__) && !defined(RTEMS_PARAVIRT) 1016 static inline uint32_t _CPU_SMP_Get_current_processor(
void )
1018 return _LEON3_Get_current_processor();
1021 uint32_t _CPU_SMP_Get_current_processor(
void );
1024 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1026 static inline void _CPU_SMP_Processor_event_broadcast(
void )
1028 __asm__ volatile (
"" : : :
"memory" );
1031 static inline void _CPU_SMP_Processor_event_receive(
void )
1033 __asm__ volatile (
"" : : :
"memory" );
1037 #if defined(SPARC_USE_LAZY_FP_SWITCH) 1038 #define _CPU_Context_Destroy( _the_thread, _the_context ) \ 1040 Per_CPU_Control *cpu_self = _Per_CPU_Get(); \ 1041 Thread_Control *_fp_owner = cpu_self->cpu_per_cpu.fp_owner; \ 1042 if ( _fp_owner == _the_thread ) { \ 1043 cpu_self->cpu_per_cpu.fp_owner = NULL; \ 1075 static inline uint32_t CPU_swap_u32(
1079 uint32_t byte1, byte2, byte3, byte4, swapped;
1081 byte4 = (value >> 24) & 0xff;
1082 byte3 = (value >> 16) & 0xff;
1083 byte2 = (value >> 8) & 0xff;
1084 byte1 = value & 0xff;
1086 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1097 #define CPU_swap_u16( value ) \ 1098 (((value&0xff) << 8) | ((value >> 8)&0xff)) 1114 SPARC_Counter_read read_isr_disabled;
1115 SPARC_Counter_read
read;
1116 volatile const CPU_Counter_ticks *counter_register;
1117 volatile const uint32_t *pending_register;
1118 uint32_t pending_mask;
1119 CPU_Counter_ticks accumulated;
1120 CPU_Counter_ticks interval;
1127 return ( *_SPARC_Counter.read )();
1130 static inline CPU_Counter_ticks _CPU_Counter_difference(
1131 CPU_Counter_ticks second,
1132 CPU_Counter_ticks first
1135 return second - first;
uint32_t l2
Definition: cpu.h:176
uint32_t g5
Definition: cpu.h:320
uint32_t g7
Definition: cpu.h:593
double f0_f1
Definition: cpu.h:480
uint32_t fsr
Definition: cpu.h:512
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
ssize_t read(int fd, void *buffer, size_t count)
Definition: read.c:27
uint32_t i0
Definition: cpu.h:346
uint32_t l3
Definition: cpu.h:335
uint32_t mov_vector_l3
Definition: cpu.h:635
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
uint32_t i6_fp
Definition: cpu.h:200
uint32_t i5
Definition: cpu.h:605
uint32_t i4
Definition: cpu.h:196
void * structure_return_address
Definition: cpu.h:204
Thread register context.
Definition: cpu.h:196
uint32_t saved_arg4
Definition: cpu.h:219
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:65
uint32_t l2
Definition: cpu.h:333
uint32_t reserved_for_alignment
Definition: cpu.h:591
uint32_t mov_psr_l0
Definition: cpu.h:629
double f8_f9
Definition: cpu.h:488
Interrupt stack frame (ISF).
Definition: cpu.h:306
uint32_t saved_arg0
Definition: cpu.h:211
uint32_t pad0
Definition: cpu.h:223
uint32_t i1
Definition: cpu.h:190
uint32_t g7
Definition: cpu.h:322
uint32_t i6_fp
Definition: cpu.h:358
uint32_t g3
Definition: cpu.h:585
uint32_t sethi_of_handler_to_l4
Definition: cpu.h:631
void _CPU_Context_Initialize(Context_Control *context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
Initializes the CPU context.
Definition: epiphany-context-initialize.c:40
uint32_t saved_arg5
Definition: cpu.h:221
double f10_f11
Definition: cpu.h:490
double l0_and_l1
Definition: cpu.h:331
uint32_t i3
Definition: cpu.h:194
uint32_t l6
Definition: cpu.h:341
uint32_t i5
Definition: cpu.h:356
uint32_t i7
Definition: cpu.h:202
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
double f22_f23
Definition: cpu.h:502
uint32_t l5
Definition: cpu.h:182
uint32_t i7
Definition: cpu.h:609
uint32_t tpc
Definition: cpu.h:613
uint32_t i0
Definition: cpu.h:595
uint32_t i2
Definition: cpu.h:599
double f4_f5
Definition: cpu.h:484
uint32_t i4
Definition: cpu.h:354
uint32_t g2
Definition: cpu.h:583
uint32_t i2
Definition: cpu.h:350
uint32_t l7
Definition: cpu.h:186
uint32_t psr
Definition: cpu.h:371
SPARC_Minimum_stack_frame Stack_frame
Definition: cpu.h:573
double f2_f3
Definition: cpu.h:482
uint32_t l3
Definition: cpu.h:178
double f26_f27
Definition: cpu.h:506
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
uint32_t l5
Definition: cpu.h:339
uint32_t npc
Definition: cpu.h:579
SPARC basic context.
Definition: cpu.h:242
const CPU_Trap_table_entry _CPU_Trap_slot_template
Definition: cpu.c:156
uint32_t jmp_to_low_of_handler_plus_l4
Definition: cpu.h:633
double f12_f13
Definition: cpu.h:492
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
double f18_f19
Definition: cpu.h:498
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1202
#define RTEMS_NO_RETURN
Definition: basedefs.h:101
uint32_t l6
Definition: cpu.h:184
uint32_t _CPU_ISR_Get_level(void)
Definition: cpu.c:88
double f28_f29
Definition: cpu.h:508
uint32_t i0
Definition: cpu.h:188
uint32_t l4
Definition: cpu.h:337
Information Required to Build RTEMS for a Particular Member of the SPARC Family.
double f30_f31
Definition: cpu.h:510
uint32_t i5
Definition: cpu.h:198
uint32_t l1
Definition: cpu.h:174
unsigned context
Definition: tlb.h:108
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.h:703
double f6_f7
Definition: cpu.h:486
uint32_t g1
Definition: cpu.h:581
uint32_t saved_arg3
Definition: cpu.h:217
bool _CPU_ISR_Is_enabled(uint32_t level)
Returns true if interrupts are enabled in the specified ISR level, otherwise returns false...
Definition: cpu.h:381
uint32_t i1
Definition: cpu.h:597
void _CPU_Context_restore(Context_Control *new_context) RTEMS_NO_RETURN
Definition: cpu_asm.c:111
uint32_t o6_sp
Definition: cpu.h:363
uint32_t psr
Definition: cpu.h:575
uintptr_t CPU_Uint32ptr
Definition: cpu.h:668
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
uint32_t i3
Definition: cpu.h:352
double f20_f21
Definition: cpu.h:500
#define SPARC_PSR_PIL_MASK
Definition: sparc.h:127
double f24_f25
Definition: cpu.h:504
uint32_t g4
Definition: cpu.h:587
uint32_t g5
Definition: cpu.h:589
uint32_t l4
Definition: cpu.h:180
double f16_f17
Definition: cpu.h:496
uint32_t i2
Definition: cpu.h:192
void _CPU_Fatal_halt(uint32_t source, uint32_t error) RTEMS_NO_RETURN
Definition: bsp_fatal_halt.c:12
unsigned size
Definition: tte.h:74
double f14_f15
Definition: cpu.h:494
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
SPARC specific RTEMS ISR installer.
Definition: cpu.h:605
The set of registers that specifies the complete processor state.
Definition: cpu.h:635
uint32_t i6_fp
Definition: cpu.h:607
uint32_t i4
Definition: cpu.h:603
uint32_t pc
Definition: cpu.h:577
uint32_t l0
Definition: cpu.h:172
uint32_t y
Definition: cpu.h:611
uint32_t i3
Definition: cpu.h:601
uint32_t saved_arg2
Definition: cpu.h:215
uint32_t l7
Definition: cpu.h:343
uint32_t o7
Definition: cpu.h:368
uint32_t saved_arg1
Definition: cpu.h:213
uint32_t i7
Definition: cpu.h:360
uint32_t i1
Definition: cpu.h:348