RTEMS  5.0.0
Data Fields
CPU_Trap_table_entry Struct Reference

#include <cpu.h>

Data Fields

uint32_t mov_psr_l0
 
uint32_t sethi_of_handler_to_l4
 
uint32_t jmp_to_low_of_handler_plus_l4
 
uint32_t mov_vector_l3
 
uint32_t rdpr_tstate_g4
 
uint32_t sethi_of_hh_handler_to_g2
 
uint32_t or_g2_hm_handler_to_g2
 
uint32_t sllx_g2_by_32_to_g2
 
uint32_t sethi_of_handler_to_g3
 
uint32_t or_g3_g2_to_g3
 
uint32_t jmp_to_low_of_handler_plus_g3
 
uint32_t mov_vector_g2
 

Detailed Description

The following type defines an entry in the SPARC's trap table.

NOTE: The instructions chosen are RTEMS dependent although one is obligated to use two of the four instructions to perform a long jump. The other instructions load one register with the trap type (a.k.a. vector) and another with the psr.

Field Documentation

◆ jmp_to_low_of_handler_plus_l4

uint32_t CPU_Trap_table_entry::jmp_to_low_of_handler_plus_l4

This will contain a "jmp %l4 + %lo(_handler)" instruction.

◆ mov_psr_l0

uint32_t CPU_Trap_table_entry::mov_psr_l0

This will contain a "mov %psr, %l0" instruction.

◆ mov_vector_l3

uint32_t CPU_Trap_table_entry::mov_vector_l3

This will contain a " mov _vector, %l3" instruction.

◆ sethi_of_handler_to_l4

uint32_t CPU_Trap_table_entry::sethi_of_handler_to_l4

This will contain a "sethi %hi(_handler), %l4" instruction.


The documentation for this struct was generated from the following file: