47 #define RISCV_MSTATUS_MIE 0x8 49 #define CPU_ISR_PASSES_FRAME_POINTER FALSE 51 #define CPU_HARDWARE_FP FALSE 52 #define CPU_SOFTWARE_FP FALSE 53 #define CPU_ALL_TASKS_ARE_FP FALSE 54 #define CPU_IDLE_TASK_IS_FP FALSE 55 #define CPU_USE_DEFERRED_FP_SWITCH FALSE 57 #define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE 59 #define CPU_STACK_GROWS_UP FALSE 61 #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (64))) 62 #define CPU_BIG_ENDIAN FALSE 63 #define CPU_LITTLE_ENDIAN TRUE 64 #define CPU_MODES_INTERRUPT_MASK 0x0000000000000001 66 #define CPU_CACHE_LINE_BYTES 64 68 #if __riscv_xlen == 32 70 #define CPU_SIZEOF_POINTER 4 72 #define CPU_STACK_MINIMUM_SIZE 4096 74 #elif __riscv_xlen == 64 76 #define CPU_SIZEOF_POINTER 8 78 #define CPU_STACK_MINIMUM_SIZE 8192 83 #define CPU_ALIGNMENT 16 85 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT 88 #define CPU_STACK_ALIGNMENT 16 90 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 98 #if __riscv_flen == 32 99 typedef float RISCV_Float;
100 #elif __riscv_flen == 64 101 typedef double RISCV_Float;
106 volatile uint32_t is_executing;
143 #define _CPU_Context_Get_SP( _context ) \ 146 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 148 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE 150 #define _CPU_Initialize_vectors() 152 static inline uint32_t riscv_interrupt_disable(
void )
154 unsigned long mstatus;
161 return mstatus & RISCV_MSTATUS_MIE;
164 static inline void riscv_interrupt_enable( uint32_t level )
166 __asm__ volatile (
"csrrs zero, mstatus, %0" : :
"r" ( level ) );
169 #define _CPU_ISR_Disable( _level ) \ 170 _level = riscv_interrupt_disable() 172 #define _CPU_ISR_Enable( _level ) \ 173 riscv_interrupt_enable( _level ) 175 #define _CPU_ISR_Flash( _level ) \ 177 _CPU_ISR_Enable( _level ); \ 178 riscv_interrupt_disable(); \ 183 return ( level & RISCV_MSTATUS_MIE ) != 0;
205 void *stack_area_begin,
206 size_t stack_area_size,
208 void ( *entry_point )(
void ),
213 #define _CPU_Context_Restart_self( _the_context ) \ 214 _CPU_Context_restore( (_the_context) ) 218 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE 220 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE 222 #define CPU_MAXIMUM_PROCESSORS 32 224 typedef uint16_t Priority_bit_map_Word;
232 RISCV_INTERRUPT_SOFTWARE_USER = 0,
233 RISCV_INTERRUPT_SOFTWARE_SUPERVISOR = 1,
234 RISCV_INTERRUPT_SOFTWARE_MACHINE = 3,
235 RISCV_INTERRUPT_TIMER_USER = 4,
236 RISCV_INTERRUPT_TIMER_SUPERVISOR = 5,
237 RISCV_INTERRUPT_TIMER_MACHINE = 7,
238 RISCV_INTERRUPT_EXTERNAL_USER = 8,
239 RISCV_INTERRUPT_EXTERNAL_SUPERVISOR = 9,
240 RISCV_INTERRUPT_EXTERNAL_MACHINE = 11
241 } RISCV_Interrupt_code;
249 RISCV_EXCEPTION_INSTRUCTION_ADDRESS_MISALIGNED = 0,
250 RISCV_EXCEPTION_INSTRUCTION_ACCESS_FAULT = 1,
251 RISCV_EXCEPTION_ILLEGAL_INSTRUCTION = 2,
252 RISCV_EXCEPTION_BREAKPOINT = 3,
253 RISCV_EXCEPTION_LOAD_ADDRESS_MISALIGNED = 4,
254 RISCV_EXCEPTION_LOAD_ACCESS_FAULT = 5,
255 RISCV_EXCEPTION_STORE_OR_AMO_ADDRESS_MISALIGNED = 6,
256 RISCV_EXCEPTION_STORE_OR_AMO_ACCESS_FAULT = 7,
257 RISCV_EXCEPTION_ENVIRONMENT_CALL_FROM_U_MODE = 8,
258 RISCV_EXCEPTION_ENVIRONMENT_CALL_FROM_S_MODE = 9,
259 RISCV_EXCEPTION_ENVIRONMENT_CALL_FROM_M_MODE = 11,
260 RISCV_EXCEPTION_INSTRUCTION_PAGE_FAULT = 12,
261 RISCV_EXCEPTION_LOAD_PAGE_FAULT = 13,
262 RISCV_EXCEPTION_STORE_OR_AMO_PAGE_FAULT = 15
263 } RISCV_Exception_code;
419 static inline uint32_t CPU_swap_u32(
423 uint32_t byte1, byte2, byte3, byte4, swapped;
425 byte4 = (value >> 24) & 0xff;
426 byte3 = (value >> 16) & 0xff;
427 byte2 = (value >> 8) & 0xff;
428 byte1 = value & 0xff;
430 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
434 #define CPU_swap_u16( value ) \ 435 (((value&0xff) << 8) | ((value >> 8)&0xff)) 441 extern volatile uint32_t *
const _RISCV_Counter;
445 static inline CPU_Counter_ticks _CPU_Counter_difference(
446 CPU_Counter_ticks second,
447 CPU_Counter_ticks first
450 return second - first;
455 uint32_t _CPU_SMP_Initialize(
void );
457 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
459 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
461 void _CPU_SMP_Prepare_start_multitasking(
void );
463 static inline uint32_t _CPU_SMP_Get_current_processor(
void )
465 unsigned long mhartid;
467 __asm__ volatile (
"csrr %0, mhartid" :
"=&r" ( mhartid ) );
469 return (uint32_t) mhartid;
472 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
474 static inline void _CPU_SMP_Processor_event_broadcast(
void )
476 __asm__ volatile (
"" : : :
"memory" );
479 static inline void _CPU_SMP_Processor_event_receive(
void )
481 __asm__ volatile (
"" : : :
"memory" );
484 static inline bool _CPU_Context_Get_is_executing(
488 return context->is_executing;
491 static inline void _CPU_Context_Set_is_executing(
496 context->is_executing = is_executing;
#define sp
stack-pointer */
Definition: regs.h:64
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
void _CPU_ISR_Set_level(uint32_t level)
Sets the hardware interrupt level by the level value.
Definition: cpu.c:57
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
Thread register context.
Definition: cpu.h:196
uint32_t isr_dispatch_disable
Definition: cpu.h:110
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:65
Interrupt stack frame (ISF).
Definition: cpu.h:306
void _CPU_Context_Initialize(Context_Control *context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
Initializes the CPU context.
Definition: epiphany-context-initialize.c:40
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
#define CPU_STACK_ALIGNMENT
Definition: cpu.h:446
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1202
#define RTEMS_NO_RETURN
Definition: basedefs.h:101
uint32_t _CPU_ISR_Get_level(void)
Definition: cpu.c:88
#define RTEMS_XSTRING(_x)
Stringifies expansion of _x.
Definition: basedefs.h:509
#define RTEMS_ALIGNED(_alignment)
Instructs the compiler to enforce the specified alignment.
Definition: basedefs.h:204
unsigned context
Definition: tlb.h:108
bool _CPU_ISR_Is_enabled(uint32_t level)
Returns true if interrupts are enabled in the specified ISR level, otherwise returns false...
Definition: cpu.h:381
void _CPU_Context_restore(Context_Control *new_context) RTEMS_NO_RETURN
Definition: cpu_asm.c:111
uintptr_t CPU_Uint32ptr
Definition: cpu.h:668
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
#define ra
return address */
Definition: regs.h:66
void _CPU_Fatal_halt(uint32_t source, uint32_t error) RTEMS_NO_RETURN
Definition: bsp_fatal_halt.c:12
The set of registers that specifies the complete processor state.
Definition: cpu.h:635
#define CPU_MODES_INTERRUPT_MASK
Definition: cpu.h:161
#define gp
global data pointer */
Definition: regs.h:63