Go to the source code of this file.
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#define | RISCV_MSTATUS_MIE 0x8 |
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#define | CPU_ISR_PASSES_FRAME_POINTER FALSE |
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#define | CPU_HARDWARE_FP FALSE |
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#define | CPU_SOFTWARE_FP FALSE |
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#define | CPU_ALL_TASKS_ARE_FP FALSE |
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#define | CPU_IDLE_TASK_IS_FP FALSE |
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#define | CPU_USE_DEFERRED_FP_SWITCH FALSE |
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#define | CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE |
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#define | CPU_STACK_GROWS_UP FALSE |
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#define | CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (64))) |
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#define | CPU_BIG_ENDIAN FALSE |
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#define | CPU_LITTLE_ENDIAN TRUE |
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#define | CPU_MODES_INTERRUPT_MASK 0x0000000000000001 |
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#define | CPU_CACHE_LINE_BYTES 64 |
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#define | CPU_ALIGNMENT 16 |
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#define | CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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#define | CPU_STACK_ALIGNMENT 16 |
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#define | CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
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#define | _CPU_Context_Get_SP(_context) (_context)->sp |
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#define | CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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#define | CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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#define | _CPU_Initialize_vectors() |
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#define | _CPU_ISR_Disable(_level) _level = riscv_interrupt_disable() |
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#define | _CPU_ISR_Enable(_level) riscv_interrupt_enable( _level ) |
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#define | _CPU_ISR_Flash(_level) |
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#define | _CPU_Context_Restart_self(_the_context) _CPU_Context_restore( (_the_context) ) |
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#define | CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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#define | CPU_USE_GENERIC_BITFIELD_DATA TRUE |
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#define | CPU_MAXIMUM_PROCESSORS 32 |
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#define | CPU_swap_u16(value) (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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typedef uint16_t | Priority_bit_map_Word |
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typedef uint32_t | CPU_Counter_ticks |
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typedef uintptr_t | CPU_Uint32ptr |
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enum | RISCV_Interrupt_code {
RISCV_INTERRUPT_SOFTWARE_USER = 0,
RISCV_INTERRUPT_SOFTWARE_SUPERVISOR = 1,
RISCV_INTERRUPT_SOFTWARE_MACHINE = 3,
RISCV_INTERRUPT_TIMER_USER = 4,
RISCV_INTERRUPT_TIMER_SUPERVISOR = 5,
RISCV_INTERRUPT_TIMER_MACHINE = 7,
RISCV_INTERRUPT_EXTERNAL_USER = 8,
RISCV_INTERRUPT_EXTERNAL_SUPERVISOR = 9,
RISCV_INTERRUPT_EXTERNAL_MACHINE = 11
} |
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enum | RISCV_Exception_code {
RISCV_EXCEPTION_INSTRUCTION_ADDRESS_MISALIGNED = 0,
RISCV_EXCEPTION_INSTRUCTION_ACCESS_FAULT = 1,
RISCV_EXCEPTION_ILLEGAL_INSTRUCTION = 2,
RISCV_EXCEPTION_BREAKPOINT = 3,
RISCV_EXCEPTION_LOAD_ADDRESS_MISALIGNED = 4,
RISCV_EXCEPTION_LOAD_ACCESS_FAULT = 5,
RISCV_EXCEPTION_STORE_OR_AMO_ADDRESS_MISALIGNED = 6,
RISCV_EXCEPTION_STORE_OR_AMO_ACCESS_FAULT = 7,
RISCV_EXCEPTION_ENVIRONMENT_CALL_FROM_U_MODE = 8,
RISCV_EXCEPTION_ENVIRONMENT_CALL_FROM_S_MODE = 9,
RISCV_EXCEPTION_ENVIRONMENT_CALL_FROM_M_MODE = 11,
RISCV_EXCEPTION_INSTRUCTION_PAGE_FAULT = 12,
RISCV_EXCEPTION_LOAD_PAGE_FAULT = 13,
RISCV_EXCEPTION_STORE_OR_AMO_PAGE_FAULT = 15
} |
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volatile uint32_t *const | _RISCV_Counter |
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◆ _CPU_ISR_Flash
#define _CPU_ISR_Flash |
( |
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_level | ) |
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Value:do{ \
_CPU_ISR_Enable( _level ); \
riscv_interrupt_disable(); \
} while(0)
◆ CPU_Uint32ptr
Type that can store a 32-bit integer or a pointer.