|
Taken from "MIPS R4000 Microprocessor User's Manual" 2nd edition:
|
#define | CACHE_I (0) |
| primary instruction */
|
|
#define | CACHE_D (1) |
| primary data */
|
|
#define | CACHE_SI (2) |
| secondary instruction */
|
|
#define | CACHE_SD (3) |
| secondary data (or combined instruction/data) */
|
|
#define | INDEX_INVALIDATE (0) |
| also encodes WRITEBACK if CACHE_D or CACHE_SD */
|
|
#define | INDEX_LOAD_TAG (1) |
|
#define | INDEX_STORE_TAG (2) |
|
#define | CREATE_DIRTY_EXCLUSIVE (3) |
| CACHE_D and CACHE_SD only */.
|
|
#define | HIT_INVALIDATE (4) |
|
#define | CACHE_FILL (5) |
| CACHE_I only */.
|
|
#define | HIT_WRITEBACK_INVALIDATE (5) |
| CACHE_D and CACHE_SD only */.
|
|
#define | HIT_WRITEBACK (6) |
| CACHE_I, CACHE_D and CACHE_SD only */.
|
|
#define | HIT_SET_VIRTUAL (7) |
| CACHE_SI and CACHE_SD only */.
|
|
#define | BUILD_CACHE_OP(o, c) (((o) << 2) | (c)) |
|
|
#define | INDEX_INVALIDATE_I BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I) |
|
#define | INDEX_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D) |
|
#define | INDEX_INVALIDATE_SI BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI) |
|
#define | INDEX_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD) |
|
#define | INDEX_LOAD_TAG_I BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I) |
|
#define | INDEX_LOAD_TAG_D BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D) |
|
#define | INDEX_LOAD_TAG_SI BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI) |
|
#define | INDEX_LOAD_TAG_SD BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD) |
|
#define | INDEX_STORE_TAG_I BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I) |
|
#define | INDEX_STORE_TAG_D BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D) |
|
#define | INDEX_STORE_TAG_SI BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI) |
|
#define | INDEX_STORE_TAG_SD BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD) |
|
#define | CREATE_DIRTY_EXCLUSIVE_D BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D) |
|
#define | CREATE_DIRTY_EXCLUSIVE_SD BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD) |
|
#define | HIT_INVALIDATE_I BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I) |
|
#define | HIT_INVALIDATE_D BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D) |
|
#define | HIT_INVALIDATE_SI BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI) |
|
#define | HIT_INVALIDATE_SD BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD) |
|
#define | CACHE_FILL_I BUILD_CACHE_OP(CACHE_FILL,CACHE_I) |
|
#define | HIT_WRITEBACK_INVALIDATE_D BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D) |
|
#define | HIT_WRITEBACK_INVALIDATE_SD BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD) |
|
#define | HIT_WRITEBACK_I BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I) |
|
#define | HIT_WRITEBACK_D BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D) |
|
#define | HIT_WRITEBACK_SD BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD) |
|
#define | HIT_SET_VIRTUAL_SI BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI) |
|
#define | HIT_SET_VIRTUAL_SD BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD) |
|
MIPS Registers.