cpu.h File Reference

#include <rtems/score/basedefs.h>
#include <rtems/score/moxie.h>
#include <rtems/bspIo.h>

Go to the source code of this file.

Data Structures
struct	Context_Control
	Thread register context. More...
struct	Context_Control_fp
	SPARC basic context. More...
struct	CPU_Interrupt_frame
	Interrupt stack frame (ISF). More...
struct	CPU_Exception_frame
	The set of registers that specifies the complete processor state. More...

Macros
#define	RTEMS_USE_32_BIT_OBJECT
#define	CPU_SIMPLE_VECTORED_INTERRUPTS   TRUE
#define	CPU_HARDWARE_FP   FALSE
#define	CPU_ALL_TASKS_ARE_FP   FALSE
#define	CPU_IDLE_TASK_IS_FP   FALSE
#define	CPU_USE_DEFERRED_FP_SWITCH   TRUE
#define	CPU_ENABLE_ROBUST_THREAD_DISPATCH   FALSE
#define	CPU_STACK_GROWS_UP   FALSE
#define	CPU_CACHE_LINE_BYTES   32
#define	CPU_STRUCTURE_ALIGNMENT
#define	CPU_MODES_INTERRUPT_MASK   0x00000001
#define	CPU_MAXIMUM_PROCESSORS   32
#define	nogap   __attribute__ ((packed))
#define	_CPU_Context_Get_SP(_context)   (_context)->sp
#define	CPU_CONTEXT_FP_SIZE   sizeof( Context_Control_fp )
#define	CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK   0
#define	CPU_INTERRUPT_NUMBER_OF_VECTORS   64
#define	CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER   (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
#define	CPU_PROVIDES_ISR_IS_IN_PROGRESS   FALSE
#define	CPU_STACK_MINIMUM_SIZE   (1536)
#define	CPU_SIZEOF_POINTER   4
#define	CPU_ALIGNMENT   8
#define	CPU_HEAP_ALIGNMENT   CPU_ALIGNMENT
#define	CPU_STACK_ALIGNMENT   0
#define	CPU_INTERRUPT_STACK_ALIGNMENT   CPU_CACHE_LINE_BYTES
#define	_CPU_Initialize_vectors()
#define	_CPU_ISR_Disable(_isr_cookie)
#define	_CPU_ISR_Enable(_isr_cookie)
#define	_CPU_ISR_Flash(_isr_cookie)
#define	_CPU_ISR_Set_level(_new_level)
#define	CPU_CCR_INTERRUPTS_ON   0x80
#define	CPU_CCR_INTERRUPTS_OFF   0x00
#define	_CPU_Context_Initialize(_the_context, _stack_base, _size, _isr, _entry_point, _is_fp, _tls_area)
#define	_CPU_Context_Restart_self(_the_context)   _CPU_Context_restore( (_the_context) );
#define	_CPU_Context_Initialize_fp(_destination)   memset( *( _destination ), 0, CPU_CONTEXT_FP_SIZE );
#define	_CPU_Fatal_halt(_source, _error)
#define	CPU_USE_GENERIC_BITFIELD_CODE   TRUE
#define	CPU_swap_u16(value)   (((value&0xff) << 8) | ((value >> 8)&0xff))

Typedefs
typedef void(*	CPU_ISR_handler) (uint32_t)
typedef uint32_t	CPU_Counter_ticks
typedef uintptr_t	CPU_Uint32ptr

Functions
RTEMS_INLINE_ROUTINE bool	_CPU_ISR_Is_enabled (uint32_t level)
uint32_t	_CPU_ISR_Get_level (void)
void	_CPU_Initialize (void)
	CPU initialization. More...
void	_CPU_ISR_install_vector (uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
void *	_CPU_Thread_Idle_body (uintptr_t)
void	_CPU_Context_switch (Context_Control *run, Context_Control *heir)
	CPU switch context. More...
void	_CPU_Context_restore (Context_Control *new_context) RTEMS_NO_RETURN
void	_CPU_Context_save_fp (Context_Control_fp **fp_context_ptr)
void	_CPU_Context_restore_fp (Context_Control_fp **fp_context_ptr)
void	_CPU_Exception_frame_print (const CPU_Exception_frame *frame)
	Prints the exception frame via printk(). More...
uint32_t	_CPU_Counter_frequency (void)
CPU_Counter_ticks	_CPU_Counter_read (void)

Macro Definition Documentation

_CPU_Context_Initialize

#define _CPU_Context_Initialize	(		_the_context,
			_stack_base,
			_size,
			_isr,
			_entry_point,
			_is_fp,
			_tls_area
	)

Value:

/* Locate Me */                                                  \
  do {                                                             \
    uintptr_t   _stack;                                            \
                                                                   \
    (void) _is_fp; /* avoid warning for being unused */            \
    (void) _isr;   /* avoid warning for being unused */            \
    _stack = ((uintptr_t)(_stack_base)) + (_size) - 8;             \
    *((void (**)(void))(_stack)) = (_entry_point);                 \
    _stack -= 4;                                                   \
    (_the_context)->fp = (void *)_stack;                           \
    (_the_context)->sp = (void *)_stack;                           \
  } while (0)

_CPU_Fatal_halt

#define _CPU_Fatal_halt	(		_source,
			_error
	)

Value:

printk("Fatal Error %d.%lu Halted\n",_source,_error); \
        for(;;)

_CPU_ISR_Disable

#define _CPU_ISR_Disable

(

_isr_cookie

)

Value:

do { \
    (_isr_cookie) = 0; \
  } while (0)

_CPU_ISR_Enable

#define _CPU_ISR_Enable

(

_isr_cookie

)

Value:

do { \
    (_isr_cookie) = (_isr_cookie); \
  } while (0)

_CPU_ISR_Flash

#define _CPU_ISR_Flash

(

_isr_cookie

)

Value:

do { \
    _CPU_ISR_Enable( _isr_cookie ); \
    _CPU_ISR_Disable( _isr_cookie ); \
  } while (0)

_CPU_ISR_Set_level

#define _CPU_ISR_Set_level

(

_new_level

)

Value:

{                                                     \
    if (_new_level)   asm volatile ( "nop\n" );         \
    else              asm volatile ( "nop\n" );         \
  }

CPU_SIZEOF_POINTER

#define CPU_SIZEOF_POINTER   4

Size of a pointer.

This must be an integer literal that can be used by the assembler. This value will be used to calculate offsets of structure members. These offsets will be used in assembler code.

Typedef Documentation

CPU_Uint32ptr

typedef uintptr_t CPU_Uint32ptr

Type that can store a 32-bit integer or a pointer.