22 #ifndef _RTEMS_SCORE_CPU_H 23 #define _RTEMS_SCORE_CPU_H 40 #define RTEMS_USE_32_BIT_OBJECT 53 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE 74 #define CPU_HARDWARE_FP FALSE 88 #define CPU_ALL_TASKS_ARE_FP FALSE 105 #define CPU_IDLE_TASK_IS_FP FALSE 136 #define CPU_USE_DEFERRED_FP_SWITCH TRUE 138 #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE 151 #define CPU_STACK_GROWS_UP FALSE 154 #define CPU_CACHE_LINE_BYTES 32 156 #define CPU_STRUCTURE_ALIGNMENT 167 #define CPU_MODES_INTERRUPT_MASK 0x00000001 169 #define CPU_MAXIMUM_PROCESSORS 32 220 #define nogap __attribute__ ((packed)) 241 #define _CPU_Context_Get_SP( _context ) \ 245 double some_float_register[2];
270 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) 281 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 291 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 64 292 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER \ 293 (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) 299 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE 309 #define CPU_STACK_MINIMUM_SIZE (1536) 318 #define CPU_SIZEOF_POINTER 4 328 #define CPU_ALIGNMENT 8 345 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT 359 #define CPU_STACK_ALIGNMENT 0 361 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 370 #define _CPU_Initialize_vectors() 380 #define _CPU_ISR_Disable( _isr_cookie ) \ 394 #define _CPU_ISR_Enable( _isr_cookie ) \ 396 (_isr_cookie) = (_isr_cookie); \ 409 #define _CPU_ISR_Flash( _isr_cookie ) \ 411 _CPU_ISR_Enable( _isr_cookie ); \ 412 _CPU_ISR_Disable( _isr_cookie ); \ 434 #define _CPU_ISR_Set_level( _new_level ) \ 436 if (_new_level) asm volatile ( "nop\n" ); \ 437 else asm volatile ( "nop\n" ); \ 471 #define CPU_CCR_INTERRUPTS_ON 0x80 472 #define CPU_CCR_INTERRUPTS_OFF 0x00 474 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ 475 _isr, _entry_point, _is_fp, _tls_area ) \ 482 _stack = ((uintptr_t)(_stack_base)) + (_size) - 8; \ 483 *((void (**)(void))(_stack)) = (_entry_point); \ 485 (_the_context)->fp = (void *)_stack; \ 486 (_the_context)->sp = (void *)_stack; \ 503 #define _CPU_Context_Restart_self( _the_context ) \ 504 _CPU_Context_restore( (_the_context) ); 506 #define _CPU_Context_Initialize_fp( _destination ) \ 507 memset( *( _destination ), 0, CPU_CONTEXT_FP_SIZE ); 522 #define _CPU_Fatal_halt( _source, _error ) \ 523 printk("Fatal Error %d.%lu Halted\n",_source,_error); \ 528 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE 543 typedef void ( *CPU_ISR_handler )( uint32_t );
547 CPU_ISR_handler new_handler,
548 CPU_ISR_handler *old_handler
619 uint32_t integer_registers [16];
652 static inline uint32_t CPU_swap_u32(
656 uint32_t byte1, byte2, byte3, byte4, swapped;
658 byte4 = (value >> 24) & 0xff;
659 byte3 = (value >> 16) & 0xff;
660 byte2 = (value >> 8) & 0xff;
661 byte1 = value & 0xff;
663 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
667 #define CPU_swap_u16( value ) \ 668 (((value&0xff) << 8) | ((value >> 8)&0xff)) 676 static inline CPU_Counter_ticks _CPU_Counter_difference(
677 CPU_Counter_ticks second,
678 CPU_Counter_ticks first
681 return second - first;
#define sp
stack-pointer */
Definition: regs.h:64
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
Thread register context.
Definition: cpu.h:196
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:65
void _CPU_Context_restore_fp(Context_Control_fp **fp_context_ptr)
Definition: cpu.c:207
Interrupt stack frame (ISF).
Definition: cpu.h:306
#define fp
frame-pointer */
Definition: regs.h:65
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
uint32_t special_interrupt_register
Definition: cpu.h:249
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
SPARC basic context.
Definition: cpu.h:242
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1202
#define RTEMS_NO_RETURN
Definition: basedefs.h:101
Interface to Kernel Print Methods.
uint32_t _CPU_ISR_Get_level(void)
Definition: cpu.c:88
bool _CPU_ISR_Is_enabled(uint32_t level)
Returns true if interrupts are enabled in the specified ISR level, otherwise returns false...
Definition: cpu.h:381
void _CPU_Context_restore(Context_Control *new_context) RTEMS_NO_RETURN
Definition: cpu_asm.c:111
uintptr_t CPU_Uint32ptr
Definition: cpu.h:668
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
SPARC specific RTEMS ISR installer.
Definition: cpu.h:605
void _CPU_Context_save_fp(Context_Control_fp **fp_context_ptr)
Definition: cpu.c:198
The set of registers that specifies the complete processor state.
Definition: cpu.h:635