RTEMS
5.0.0
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MIPS Architecture Support. More...
Modules | |
CPU Related Definitions | |
RTEMS no cpu Build Information | |
Register Structure | |
Data Structures | |
struct | Context_Control |
Thread register context. More... | |
struct | Context_Control_fp |
SPARC basic context. More... | |
struct | CPU_Interrupt_frame |
Interrupt stack frame (ISF). More... | |
Macros | |
#define | CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
#define | CPU_ISR_PASSES_FRAME_POINTER TRUE |
#define | CPU_HARDWARE_FP FALSE |
#define | CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP |
#define | CPU_IDLE_TASK_IS_FP FALSE |
#define | CPU_USE_DEFERRED_FP_SWITCH TRUE |
#define | CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
#define | CPU_STACK_GROWS_UP FALSE |
#define | CPU_CACHE_LINE_BYTES 16 |
#define | CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |
#define | CPU_MODES_INTERRUPT_MASK 0x000000ff |
#define | CPU_SIZEOF_POINTER 4 |
#define | CPU_MAXIMUM_PROCESSORS 32 |
#define | _CPU_Context_Get_SP(_context) (uintptr_t) (_context)->sp |
#define | CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
#define | CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
#define | CPU_STACK_MINIMUM_SIZE (8 * 1024) |
#define | CPU_ALIGNMENT 8 |
#define | CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
#define | CPU_STACK_ALIGNMENT CPU_ALIGNMENT |
#define | CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
#define | _CPU_ISR_Disable(_level) |
#define | _CPU_ISR_Enable(_level) |
#define | _CPU_ISR_Flash(_xlevel) |
#define | _CPU_Context_Restart_self(_the_context) _CPU_Context_restore( (_the_context) ); |
#define | _CPU_Context_Initialize_fp(_destination) |
#define | _CPU_Fatal_halt(_source, _error) |
#define | CPU_USE_GENERIC_BITFIELD_CODE TRUE |
#define | CPU_swap_u16(value) (((value&0xff) << 8) | ((value >> 8)&0xff)) |
#define | CPU_PER_CPU_CONTROL_SIZE 0 |
Typedefs | |
typedef CPU_Interrupt_frame | CPU_Exception_frame |
typedef uint32_t | CPU_Counter_ticks |
typedef uintptr_t | CPU_Uint32ptr |
Functions | |
void | mips_vector_exceptions (CPU_Interrupt_frame *frame) |
uint32_t | mips_interrupt_mask (void) |
RTEMS_INLINE_ROUTINE bool | _CPU_ISR_Is_enabled (uint32_t level) |
uint32_t | _CPU_ISR_Get_level (void) |
void | _CPU_ISR_Set_level (uint32_t) |
Sets the hardware interrupt level by the level value. More... | |
void | _CPU_Context_Initialize (Context_Control *the_context, uintptr_t *stack_base, uint32_t size, uint32_t new_level, void *entry_point, bool is_fp, void *tls_area) |
void | mips_break (int error) |
void | _CPU_Initialize (void) |
CPU initialization. More... | |
void * | _CPU_Thread_Idle_body (uintptr_t ignored) |
void | _CPU_Context_switch (Context_Control *run, Context_Control *heir) |
CPU switch context. More... | |
void | _CPU_Context_restore (Context_Control *new_context) RTEMS_NO_RETURN |
void | _CPU_Context_save_fp (Context_Control_fp **fp_context_ptr) |
void | _CPU_Context_restore_fp (Context_Control_fp **fp_context_ptr) |
void | _CPU_Exception_frame_print (const CPU_Exception_frame *frame) |
Prints the exception frame via printk(). More... | |
uint32_t | _CPU_Counter_frequency (void) |
CPU_Counter_ticks | _CPU_Counter_read (void) |
RTEMS_INLINE_ROUTINE void | _CPU_Context_volatile_clobber (uintptr_t pattern) |
RTEMS_INLINE_ROUTINE void | _CPU_Context_validate (uintptr_t pattern) |
RTEMS_INLINE_ROUTINE void | _CPU_Instruction_illegal (void) |
RTEMS_INLINE_ROUTINE void | _CPU_Instruction_no_operation (void) |
Variables | |
Context_Control_fp | _CPU_Null_fp_context |
MIPS Architecture Support.
#define _CPU_Context_Initialize_fp | ( | _destination | ) |
#define _CPU_Fatal_halt | ( | _source, | |
_error | |||
) |
#define _CPU_ISR_Disable | ( | _level | ) |
#define _CPU_ISR_Enable | ( | _level | ) |
#define _CPU_ISR_Flash | ( | _xlevel | ) |
typedef uintptr_t CPU_Uint32ptr |
Type that can store a 32-bit integer or a pointer.
void _CPU_Context_restore | ( | Context_Control * | new_context | ) |
This routine is generally used only to restart self in an efficient manner. It may simply be a label in _CPU_Context_switch.
[in] | new_context | points to the context to be restored. |
Port Specific Information:
XXX document implementation including references if appropriate
void _CPU_Context_restore_fp | ( | Context_Control_fp ** | fp_context_ptr | ) |
This routine restores the floating point context passed to it.
[in] | fp_context_ptr | is a pointer to a pointer to a floating point context area to restore |
Port Specific Information:
XXX document implementation including references if appropriate
void _CPU_Context_save_fp | ( | Context_Control_fp ** | fp_context_ptr | ) |
This routine saves the floating point context passed to it.
[in] | fp_context_ptr | is a pointer to a pointer to a floating point context area |
Port Specific Information:
XXX document implementation including references if appropriate
void _CPU_Context_switch | ( | Context_Control * | run, |
Context_Control * | heir | ||
) |
CPU switch context.
This routine switches from the run context to the heir context.
[in] | run | points to the context of the currently executing task |
[in] | heir | points to the context of the heir task |
Port Specific Information:
XXX document implementation including references if appropriate
void _CPU_Exception_frame_print | ( | const CPU_Exception_frame * | frame | ) |
Prints the exception frame via printk().
void _CPU_Initialize | ( | void | ) |
CPU initialization.
CPU initialize. This routine performs CPU dependent initialization.
CPU initialize. This routine performs CPU dependent initialization.
CPU initialization.
uint32_t _CPU_ISR_Get_level | ( | void | ) |
Return the current interrupt disable level for this task in the format used by the interrupt level portion of the task mode.
Port Specific Information:
XXX document implementation including references if appropriate
void _CPU_ISR_Set_level | ( | uint32_t | new_level | ) |
Sets the hardware interrupt level by the level value.
[in] | level | for or1k can only range over two values: 0 (enable interrupts) and 1 (disable interrupts). In future implementations if fast context switch is implemented, the level can range from 0 to 15. |