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#define | K0BASE 0x80000000 |
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#define | K0SIZE 0x20000000 |
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#define | K1BASE 0xa0000000 |
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#define | K1SIZE 0x20000000 |
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#define | K2BASE 0xc0000000 |
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#define | K2SIZE 0x20000000 |
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#define | KUBASE 0 |
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#define | KUSIZE 0x80000000 |
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#define | R_VEC (K1BASE+0x1fc00000) /* reset vector */ |
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#define | CAST(as) |
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#define | K0_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* kseg0 to kseg1 */ |
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#define | K1_TO_K0(x) (CAST(unsigned)(x)&0x9FFFFFFF) /* kseg1 to kseg0 */ |
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#define | K0_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg0 to physical */ |
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#define | K1_TO_PHYS(x) (CAST(unsigned)(x)&0x1FFFFFFF) /* kseg1 to physical */ |
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#define | PHYS_TO_K0(x) (CAST(unsigned)(x)|0x80000000) /* physical to kseg0 */ |
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#define | PHYS_TO_K1(x) (CAST(unsigned)(x)|0xA0000000) /* physical to kseg1 */ |
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#define | MINCACHE 0x200 /* 512 For 3041. */ |
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#define | MAXCACHE 0x40000 /* 256*1024 256k */ |
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#define | CAUSE_BD 0x80000000 /* Branch delay slot */ |
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#define | CAUSE_BT 0x40000000 /* Branch Taken */ |
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#define | CAUSE_CEMASK 0x30000000 /* coprocessor error */ |
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#define | CAUSE_CESHIFT 28 |
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#define | CAUSE_IPMASK 0x0000FF00 /* Pending interrupt mask */ |
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#define | CAUSE_IPSHIFT 8 |
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#define | CAUSE_EXCMASK 0x0000003C /* Cause code bits */ |
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#define | CAUSE_EXCSHIFT 2 |
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#define | C0_INX $0 /* tlb index */ |
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#define | C0_RAND $1 /* tlb random */ |
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#define | C0_CTXT $4 /* tlb context */ |
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#define | C0_BADVADDR $8 /* bad virtual address */ |
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#define | C0_TLBHI $10 /* tlb entry hi */ |
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#define | C0_SR $12 /* status register */ |
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#define | C0_CAUSE $13 /* exception cause */ |
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#define | C0_EPC $14 /* exception pc */ |
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#define | C0_PRID $15 /* revision identifier */ |
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#define | C1_REVISION $0 |
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#define | C1_STATUS $31 |
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