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#define | MIPS_HAS_FPU 1 |
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#define | CPU_NAME "MIPS" |
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#define | MIPS_EXCEPTION_BASE 0 |
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#define | MIPS_EXCEPTION_INT MIPS_EXCEPTION_BASE+0 |
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#define | MIPS_EXCEPTION_MOD MIPS_EXCEPTION_BASE+1 |
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#define | MIPS_EXCEPTION_TLBL MIPS_EXCEPTION_BASE+2 |
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#define | MIPS_EXCEPTION_TLBS MIPS_EXCEPTION_BASE+3 |
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#define | MIPS_EXCEPTION_ADEL MIPS_EXCEPTION_BASE+4 |
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#define | MIPS_EXCEPTION_ADES MIPS_EXCEPTION_BASE+5 |
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#define | MIPS_EXCEPTION_IBE MIPS_EXCEPTION_BASE+6 |
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#define | MIPS_EXCEPTION_DBE MIPS_EXCEPTION_BASE+7 |
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#define | MIPS_EXCEPTION_SYSCALL MIPS_EXCEPTION_BASE+8 |
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#define | MIPS_EXCEPTION_BREAK MIPS_EXCEPTION_BASE+9 |
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#define | MIPS_EXCEPTION_RI MIPS_EXCEPTION_BASE+10 |
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#define | MIPS_EXCEPTION_CPU MIPS_EXCEPTION_BASE+11 |
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#define | MIPS_EXCEPTION_OVERFLOW MIPS_EXCEPTION_BASE+12 |
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#define | MIPS_EXCEPTION_TRAP MIPS_EXCEPTION_BASE+13 |
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#define | MIPS_EXCEPTION_VCEI MIPS_EXCEPTION_BASE+14 |
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#define | MIPS_EXCEPTION_FPE MIPS_EXCEPTION_BASE+15 |
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#define | MIPS_EXCEPTION_C2E MIPS_EXCEPTION_BASE+16 |
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#define | MIPS_EXCEPTION_WATCH MIPS_EXCEPTION_BASE+23 |
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#define | MIPS_EXCEPTION_VCED MIPS_EXCEPTION_BASE+31 |
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#define | MIPS_INTERRUPT_BASE MIPS_EXCEPTION_BASE+32 |
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#define | mips_get_sr(_x) |
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#define | mips_set_sr(_x) |
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#define | mips_get_cause(_x) |
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#define | mips_set_cause(_x) |
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#define | mips_get_dcic(_x) |
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#define | mips_set_dcic(_x) |
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#define | mips_get_bpcrm(_x, _y) |
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#define | mips_set_bpcrm(_x, _y) |
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#define | mips_get_bdarm(_x, _y) |
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#define | mips_set_bdarm(_x, _y) |
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#define | mips_get_fcr31(_x) |
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#define | mips_set_fcr31(_x) |
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#define | mips_enable_in_interrupt_mask(_mask) |
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#define | mips_disable_in_interrupt_mask(_mask) |
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