RTEMS 5.2
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VMEConfig.h
1#ifndef RTEMS_BSP_VME_CONFIG_H
2#define RTEMS_BSP_VME_CONFIG_H
3/* VMEConfig.h, S. Kate Feng modified it for MVME5500 3/04
4 *
5 * May 2011 : Use the VME shared IRQ handlers.
6 *
7 * It seems that the implementation of VMEUNIVERSE_IRQ_MGR_FLAG_PW_WORKAROUND
8 * is not fully developed. The UNIV_REGOFF_VCSR_BS is defined for VME64
9 * specification, which does not apply to a VME32 crate. In order to avoid
10 * spurious VME interrupts, a better and more universal solution is
11 * to flush the vmeUniverse FIFO by reading a register back within the
12 * users' Interrupt Service Routine (ISR) before returning.
13 *
14 * Some devices might require the ISR to issue an interrupt status READ
15 * after its IRQ is cleared, but before its corresponding interrupt
16 * is enabled again.
17 *
18 */
19
20/*
21 * Prototypes
22 */
23int BSP_VMEInit(void);
24int BSP_VMEIrqMgrInstall(void);
25
26/* BSP specific address space configuration parameters */
27
28/*
29 * The BSP maps VME address ranges into
30 * one BAT.
31 * NOTE: the BSP (startup/bspstart.c) uses
32 * hardcoded window lengths that match this
33 * layout:
34 */
35#define _VME_A32_WIN0_ON_PCI 0x90000000
36/* If _VME_CSR_ON_PCI is defined then the A32 window is reduced to accommodate
37 * CSR for space.
38 */
39#define _VME_CSR_ON_PCI 0x9e000000
40#define _VME_A24_ON_PCI 0x9f000000
41#define _VME_A16_ON_PCI 0x9fff0000
42
43/* Reuse BAT 0 for VME */
44#define BSP_VME_BAT_IDX 0
45
46/* start of the A32 window on the VME bus
47 * TODO: this should perhaps be a configuration option
48 */
49#define _VME_A32_WIN0_ON_VME 0x20000000
50
51/* if _VME_DRAM_OFFSET is defined, the BSP
52 * will map our RAM onto the VME bus, starting
53 * at _VME_DRAM_OFFSET
54 */
55#define _VME_DRAM_OFFSET 0x90000000
56
57#define BSP_VME_UNIVERSE_INSTALL_IRQ_MGR(err) \
58 do { \
59 err = vmeUniverseInstallIrqMgrAlt(VMEUNIVERSE_IRQ_MGR_FLAG_SHARED, \
60 0, BSP_GPP_VME_VLINT0, \
61 1, BSP_GPP_VME_VLINT1, \
62 2, BSP_GPP_VME_VLINT2, \
63 3, BSP_GPP_VME_VLINT3, \
64 -1 /* terminate list */); \
65 } while (0)
66
67#endif
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