RTEMS 5.2
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m93cxx.h
1/*===============================================================*\
2| Project: RTEMS generic MPC5200 BSP |
3+-----------------------------------------------------------------+
4| Partially based on the code references which are named below. |
5| Adaptions, modifications, enhancements and any recent parts of |
6| the code are: |
7| Copyright (c) 2005 |
8| Embedded Brains GmbH |
9| Obere Lagerstr. 30 |
10| D-82178 Puchheim |
11| Germany |
12| rtems@embedded-brains.de |
13+-----------------------------------------------------------------+
14| The license and distribution terms for this file may be |
15| found in the file LICENSE in this distribution or at |
16| |
17| http://www.rtems.org/license/LICENSE. |
18| |
19+-----------------------------------------------------------------+
20| this file contains definitions for the M93Cxx EEPROM devices |
21\*===============================================================*/
22/***********************************************************************/
23/* */
24/* Module: m93cxx.h */
25/* Date: 07/17/2003 */
26/* Purpose: RTEMS M93C64-based header file */
27/* */
28/*---------------------------------------------------------------------*/
29/* */
30/* Description: M93C46 is a serial microwire EEPROM which contains */
31/* 1Kbit (128 bytes/64 words) of non-volatile memory. */
32/* The device can be configured for byte- or word- */
33/* access. The driver provides a file-like interface */
34/* to this memory. */
35/* */
36/* MPC5x00 PIN settings: */
37/* */
38/* PSC3_6 (output) -> MC93C46 serial data in (D) */
39/* PSC3_7 (input) -> MC93C46 serial data out (Q) */
40/* PSC3_8 (output) -> MC93C46 chip select input (S) */
41/* PSC3_9 (output) -> MC93C46 serial clock (C) */
42/* */
43/*---------------------------------------------------------------------*/
44/* */
45/* Code */
46/* References: none */
47/* Module: */
48/* Project: */
49/* Version */
50/* Date: */
51/* Author: */
52/* Copyright: */
53/* */
54/*---------------------------------------------------------------------*/
55/* */
56/* Partially based on the code references which are named above. */
57/* Adaptions, modifications, enhancements and any recent parts of */
58/* the code are under the right of */
59/* */
60/* IPR Engineering, Dachauer Straße 38, D-80335 München */
61/* Copyright(C) 2003 */
62/* */
63/*---------------------------------------------------------------------*/
64/* */
65/* IPR Engineering makes no representation or warranties with */
66/* respect to the performance of this computer program, and */
67/* specifically disclaims any responsibility for any damages, */
68/* special or consequential, connected with the use of this program. */
69/* */
70/*---------------------------------------------------------------------*/
71/* */
72/* Version history: 1.0 */
73/* */
74/***********************************************************************/
75
76#ifndef __M93CXX_H__
77#define __M93CXX_H__
78
79#ifdef __cplusplus
80extern "C" {
81#endif
82
83static void m93cxx_enable_write(void);
84static void m93cxx_disable_write(void);
85static void m93cxx_write_byte(uint32_t, uint8_t);
86static uint8_t m93cxx_read_byte(uint32_t);
87void wait_usec(unsigned long);
88
89#define M93CXX_MODE_WORD
90/*#define M93C46_MODE_BYTE*/
91#define M93C46
92#define M93C46_NVRAM_SIZE 128
93
94#define GPIO_PSC3_6 (1 << 12)
95#define GPIO_PSC3_7 (1 << 13)
96#define GPIO_PSC3_8 (1 << 26)
97#define GPIO_PSC3_9 (1 << 26)
98
99#define START_BIT 0x1
100#define EWDS_OPCODE 0x0
101#define WRAL_OPCODE 0x1
102#define ERAL_OPCODE 0x2
103#define EWEN_OPCODE 0x3
104#define WRITE_OPCODE 0x4
105#define READ_OPCODE 0x8
106#define ERASE_OPCODE 0xC
107
108#define WAIT(i) wait_usec(i)
109
110#define ENABLE_CHIP_SELECT mpc5200.gpiosido |= GPIO_PSC3_8
111#define DISABLE_CHIP_SELECT mpc5200.gpiosido &= ~GPIO_PSC3_8
112#define SET_DATA_BIT_HIGH mpc5200.gpiosdo |= GPIO_PSC3_6
113#define SET_DATA_BIT_LOW mpc5200.gpiosdo &= ~GPIO_PSC3_6
114
115#ifdef M93CXX_MODE_BYTE
116#define GET_DATA_BYTE_SHIFT(val) ((val) |= ((mpc5200.gpiosdi & GPIO_PSC3_7) >> 13)); \
117 ((val) <<= 1)
118#define SET_DATA_BYTE_SHIFT(val) (((val) & 0x80) ? (mpc5200.gpiosdo |= GPIO_PSC3_6) : (mpc5200.gpiosdo &= ~GPIO_PSC3_6)); \
119 ((val) <<= 1)
120#else
121#define GET_DATA_WORD_SHIFT(val) ((val) |= ((mpc5200.gpiosdi & GPIO_PSC3_7) >> 13)); \
122 ((val) <<= 1)
123#define SET_DATA_WORD_SHIFT(val) (((val) & 0x8000) ? (mpc5200.gpiosdo |= GPIO_PSC3_6) : (mpc5200.gpiosdo &= ~GPIO_PSC3_6)); \
124 ((val) <<= 1)
125#endif
126
127#define MASK_HEAD_SHIFT(head) ((((head) & 0x80000000) >> 31) ? (mpc5200.gpiosdo |= GPIO_PSC3_6) : (mpc5200.gpiosdo &= ~GPIO_PSC3_6)); \
128 ((head) <<= 1)
129#define DO_CLOCK_CYCLE mpc5200.gpiowdo |= GPIO_PSC3_9; \
130 WAIT(1000); \
131 mpc5200.gpiowdo &= ~GPIO_PSC3_9
132#define CHECK_WRITE_BUSY while(!(mpc5200.gpiosdi & GPIO_PSC3_7))
133
134
135#ifdef M93CXX_MODE_BYTE
136#ifdef M93C46
137#define M93C46_EWDS ((START_BIT << 31) | (EWDS_OPCODE << 27))
138#define M93C46_WRAL ((START_BIT << 31) | (WRAL_OPCODE << 27))
139#define M93C46_ERAL ((START_BIT << 31) | (ERAL_OPCODE << 27))
140#define M93C46_EWEN ((START_BIT << 31) | (EWEN_OPCODE << 27))
141#define M93C46_READ(addr) ((START_BIT << 31) | (READ_OPCODE << 27) | ((addr) << 22))
142#define M93C46_WRITE(addr) ((START_BIT << 31) | (WRITE_OPCODE << 27) | ((addr) << 22))
143#define M93C46_ERASE(addr) ((START_BIT << 31) | (ERASE_OPCODE << 27) | ((addr) << 22))
144#define M93C46_CLOCK_CYCLES 10
145#endif
146#else
147#ifdef M93C46
148#define M93C46_EWDS ((START_BIT << 31) | (EWDS_OPCODE << 27))
149#define M93C46_WRAL ((START_BIT << 31) | (WRAL_OPCODE << 27))
150#define M93C46_ERAL ((START_BIT << 31) | (ERAL_OPCODE << 27))
151#define M93C46_EWEN ((START_BIT << 31) | (EWEN_OPCODE << 27))
152#define M93C46_READ(addr) ((START_BIT << 31) | (READ_OPCODE << 27) | ((addr) << 23))
153#define M93C46_WRITE(addr) ((START_BIT << 31) | (WRITE_OPCODE << 27) | ((addr) << 23))
154#define M93C46_ERASE(addr) ((START_BIT << 31) | (ERASE_OPCODE << 27) | ((addr) << 23))
155#define M93C46_CLOCK_CYCLES 9
156#endif
157#endif
158
159#ifdef __cplusplus
160}
161#endif
162
163#endif /* __M93CXX_H__ */
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