35 #ifndef _RTEMS_SCORE_CPU_H 36 #define _RTEMS_SCORE_CPU_H 38 #include <rtems/score/types.h> 69 #define CPU_INLINE_ENABLE_DISPATCH FALSE 92 #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE 102 #define CPU_STACK_GROWS_UP FALSE 124 #define CPU_STRUCTURE_ALIGNMENT \ 125 __attribute__ ((aligned (PPC_STRUCTURE_ALIGNMENT))) 127 #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE 134 #if defined(__BIG_ENDIAN__) || defined(_BIG_ENDIAN) 135 #define CPU_BIG_ENDIAN TRUE 136 #define CPU_LITTLE_ENDIAN FALSE 138 #define CPU_BIG_ENDIAN FALSE 139 #define CPU_LITTLE_ENDIAN TRUE 158 #if ( PPC_HAS_FPU == 1 ) 159 #define CPU_HARDWARE_FP TRUE 160 #define CPU_SOFTWARE_FP FALSE 162 #define CPU_HARDWARE_FP FALSE 163 #define CPU_SOFTWARE_FP FALSE 179 #define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP 193 #define CPU_IDLE_TASK_IS_FP FALSE 195 #define CPU_PER_CPU_CONTROL_SIZE 0 237 #define PPC_GPR_TYPE uint32_t 238 #define PPC_GPR_SIZE 4 239 #define PPC_GPR_LOAD lwz 240 #define PPC_GPR_STORE stw 242 #define PPC_GPR_TYPE uint64_t 243 #define PPC_GPR_SIZE 8 244 #define PPC_GPR_LOAD evldd 245 #define PPC_GPR_STORE evstdd 279 #if defined(PPC_MULTILIB_ALTIVEC) 280 uint32_t reserved_for_alignment;
294 #elif defined(__ALTIVEC__) 304 uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE];
306 #if defined(PPC_MULTILIB_FPU) 326 #if defined(RTEMS_SMP) 332 volatile uint32_t is_executing;
338 PPC_DEFAULT_CACHE_LINE_SIZE
340 + (
sizeof(
ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0
342 : PPC_DEFAULT_CACHE_LINE_SIZE
343 -
sizeof(
ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE)
349 uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE;
350 uintptr_t mask = clsz - 1;
351 uintptr_t addr = (uintptr_t) context;
356 #define _CPU_Context_Get_SP( _context ) \ 357 ppc_get_context(_context)->gpr1 360 static inline bool _CPU_Context_Get_is_executing(
364 return ppc_get_context(context)->is_executing;
367 static inline void _CPU_Context_Set_is_executing(
372 ppc_get_context(context)->is_executing = is_executing;
377 #define PPC_CONTEXT_OFFSET_GPR1 (PPC_DEFAULT_CACHE_LINE_SIZE + 0) 378 #define PPC_CONTEXT_OFFSET_MSR (PPC_DEFAULT_CACHE_LINE_SIZE + 4) 379 #define PPC_CONTEXT_OFFSET_LR (PPC_DEFAULT_CACHE_LINE_SIZE + 8) 380 #define PPC_CONTEXT_OFFSET_CR (PPC_DEFAULT_CACHE_LINE_SIZE + 12) 382 #define PPC_CONTEXT_GPR_OFFSET( gpr ) \ 383 (((gpr) - 14) * PPC_GPR_SIZE + PPC_DEFAULT_CACHE_LINE_SIZE + 16) 385 #define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 ) 386 #define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 ) 387 #define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 ) 388 #define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 ) 389 #define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 ) 390 #define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 ) 391 #define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 ) 392 #define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 ) 393 #define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 ) 394 #define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 ) 395 #define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 ) 396 #define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 ) 397 #define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 ) 398 #define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 ) 399 #define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 ) 400 #define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 ) 401 #define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 ) 402 #define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 ) 403 #define PPC_CONTEXT_OFFSET_GPR2 PPC_CONTEXT_GPR_OFFSET( 32 ) 405 #ifdef PPC_MULTILIB_ALTIVEC 406 #define PPC_CONTEXT_OFFSET_V( v ) \ 407 ( ( ( v ) - 20 ) * 16 + PPC_DEFAULT_CACHE_LINE_SIZE + 96 ) 408 #define PPC_CONTEXT_OFFSET_V20 PPC_CONTEXT_OFFSET_V( 20 ) 409 #define PPC_CONTEXT_OFFSET_V21 PPC_CONTEXT_OFFSET_V( 21 ) 410 #define PPC_CONTEXT_OFFSET_V22 PPC_CONTEXT_OFFSET_V( 22 ) 411 #define PPC_CONTEXT_OFFSET_V23 PPC_CONTEXT_OFFSET_V( 23 ) 412 #define PPC_CONTEXT_OFFSET_V24 PPC_CONTEXT_OFFSET_V( 24 ) 413 #define PPC_CONTEXT_OFFSET_V25 PPC_CONTEXT_OFFSET_V( 25 ) 414 #define PPC_CONTEXT_OFFSET_V26 PPC_CONTEXT_OFFSET_V( 26 ) 415 #define PPC_CONTEXT_OFFSET_V27 PPC_CONTEXT_OFFSET_V( 27 ) 416 #define PPC_CONTEXT_OFFSET_V28 PPC_CONTEXT_OFFSET_V( 28 ) 417 #define PPC_CONTEXT_OFFSET_V29 PPC_CONTEXT_OFFSET_V( 29 ) 418 #define PPC_CONTEXT_OFFSET_V30 PPC_CONTEXT_OFFSET_V( 30 ) 419 #define PPC_CONTEXT_OFFSET_V31 PPC_CONTEXT_OFFSET_V( 31 ) 420 #define PPC_CONTEXT_OFFSET_VRSAVE PPC_CONTEXT_OFFSET_V( 32 ) 421 #define PPC_CONTEXT_OFFSET_F( f ) \ 422 ( ( ( f ) - 14 ) * 8 + PPC_DEFAULT_CACHE_LINE_SIZE + 296 ) 424 #define PPC_CONTEXT_OFFSET_F( f ) \ 425 ( ( ( f ) - 14 ) * 8 + PPC_DEFAULT_CACHE_LINE_SIZE + 96 ) 428 #ifdef PPC_MULTILIB_FPU 429 #define PPC_CONTEXT_OFFSET_F14 PPC_CONTEXT_OFFSET_F( 14 ) 430 #define PPC_CONTEXT_OFFSET_F15 PPC_CONTEXT_OFFSET_F( 15 ) 431 #define PPC_CONTEXT_OFFSET_F16 PPC_CONTEXT_OFFSET_F( 16 ) 432 #define PPC_CONTEXT_OFFSET_F17 PPC_CONTEXT_OFFSET_F( 17 ) 433 #define PPC_CONTEXT_OFFSET_F18 PPC_CONTEXT_OFFSET_F( 18 ) 434 #define PPC_CONTEXT_OFFSET_F19 PPC_CONTEXT_OFFSET_F( 19 ) 435 #define PPC_CONTEXT_OFFSET_F20 PPC_CONTEXT_OFFSET_F( 20 ) 436 #define PPC_CONTEXT_OFFSET_F21 PPC_CONTEXT_OFFSET_F( 21 ) 437 #define PPC_CONTEXT_OFFSET_F22 PPC_CONTEXT_OFFSET_F( 22 ) 438 #define PPC_CONTEXT_OFFSET_F23 PPC_CONTEXT_OFFSET_F( 23 ) 439 #define PPC_CONTEXT_OFFSET_F24 PPC_CONTEXT_OFFSET_F( 24 ) 440 #define PPC_CONTEXT_OFFSET_F25 PPC_CONTEXT_OFFSET_F( 25 ) 441 #define PPC_CONTEXT_OFFSET_F26 PPC_CONTEXT_OFFSET_F( 26 ) 442 #define PPC_CONTEXT_OFFSET_F27 PPC_CONTEXT_OFFSET_F( 27 ) 443 #define PPC_CONTEXT_OFFSET_F28 PPC_CONTEXT_OFFSET_F( 28 ) 444 #define PPC_CONTEXT_OFFSET_F29 PPC_CONTEXT_OFFSET_F( 29 ) 445 #define PPC_CONTEXT_OFFSET_F30 PPC_CONTEXT_OFFSET_F( 30 ) 446 #define PPC_CONTEXT_OFFSET_F31 PPC_CONTEXT_OFFSET_F( 31 ) 449 #if defined(PPC_MULTILIB_FPU) 450 #define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_F( 32 ) 451 #elif defined(PPC_MULTILIB_ALTIVEC) 452 #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_OFFSET_VRSAVE + 4) 454 #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_GPR_OFFSET( 32 ) + 4) 458 #define PPC_CONTEXT_OFFSET_IS_EXECUTING PPC_CONTEXT_VOLATILE_SIZE 463 #if (PPC_HAS_FPU == 1) 470 #if (PPC_HAS_DOUBLE == 1) 525 #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE 551 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE 568 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE 579 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE 587 #define CPU_ISR_PASSES_FRAME_POINTER 0 625 #define CPU_USE_DEFERRED_FP_SWITCH FALSE 649 #define CPU_MODES_INTERRUPT_LEVEL 0x00000001 650 #define CPU_MODES_INTERRUPT_MASK 0x00000001 659 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) 667 #define CPU_STACK_CHECK_SIZE (128) 675 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 684 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE 699 register unsigned int msr;
701 if (msr & MSR_EE)
return 0;
707 register unsigned int msr;
710 msr |= ppc_interrupt_get_disable_mask();
713 msr &= ~ppc_interrupt_get_disable_mask();
718 void BSP_panic(
char *);
728 void _BSP_Fatal_error(
unsigned int);
732 #define _CPU_Fatal_halt( _source, _error ) \ 733 _BSP_Fatal_error(_error) 742 #define CPU_STACK_MINIMUM_SIZE (1024*8) 744 #define CPU_SIZEOF_POINTER 4 751 #define CPU_ALIGNMENT (PPC_ALIGNMENT) 765 #define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) 779 #define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT) 790 #define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) 813 static inline uint32_t CPU_swap_u32(
819 __asm__ volatile(
"rlwimi %0,%1,8,24,31;" 820 "rlwimi %0,%1,24,16,23;" 821 "rlwimi %0,%1,8,8,15;" 822 "rlwimi %0,%1,24,0,7;" :
823 "=&r" ((swapped)) :
"r" ((value)));
828 #define CPU_swap_u16( value ) \ 829 (((value&0xff) << 8) | ((value >> 8)&0xff)) 835 CPU_Counter_ticks value;
837 #if defined(__PPC_CPU_E6500__) 839 __asm__ volatile(
"mfspr %0, 526" :
"=r" (value) );
841 __asm__ volatile(
"mfspr %0, 268" :
"=r" (value) );
848 CPU_Counter_ticks second,
849 CPU_Counter_ticks first
852 return second - first;
879 uint32_t *stack_base,
897 #define _CPU_Context_Restart_self( _the_context ) \ 898 _CPU_Context_restore( (_the_context) ); 914 #define _CPU_Context_Fp_start( _base, _offset ) \ 915 ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) 929 #define _CPU_Context_Initialize_fp( _destination ) \ 930 memset( *(_destination), 0, sizeof( **(_destination) ) ) 993 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ 995 __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ 1007 #define _CPU_Priority_Mask( _bit_number ) \ 1008 ( 0x80000000 >> (_bit_number) ) 1017 #define _CPU_Priority_bits_index( _priority ) \ 1096 uint32_t _CPU_SMP_Initialize(
void );
1098 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1100 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1102 void _CPU_SMP_Prepare_start_multitasking(
void );
1104 static inline uint32_t _CPU_SMP_Get_current_processor(
void )
1117 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1119 static inline void _CPU_SMP_Processor_event_broadcast(
void )
1121 __asm__ volatile (
"" : : :
"memory" );
1124 static inline void _CPU_SMP_Processor_event_receive(
void )
1126 __asm__ volatile (
"" : : :
"memory" );
1133 uint32_t _EXC_number;
1139 uint32_t EXC_SPEFSCR;
1174 #if defined(PPC_MULTILIB_ALTIVEC) || defined(PPC_MULTILIB_FPU) 1177 #ifdef PPC_MULTILIB_ALTIVEC 1216 #ifdef PPC_MULTILIB_FPU 1261 _CPU_Initialize_altivec(
void);
1270 _CPU_Context_switch_altivec(
1282 _CPU_Context_restore_altivec(
1293 _CPU_Context_initialize_altivec(
1297 void _CPU_Fatal_error(
void _CPU_ISR_install_vector(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs an interrupt vector.
Definition: cpu.c:69
void _CPU_Context_validate(uintptr_t pattern)
Initializes and validates the CPU context with values derived from the pattern parameter.
Definition: cpu.h:1109
uint32_t _CPU_ISR_Get_level(void)
Return the current interrupt disable level for this task in the format used by the interrupt level po...
Definition: cpu.c:39
void _CPU_Context_restore(Context_Control *new_context)
This routine is generally used only to restart self in an efficient manner.
Definition: cpu_asm.c:112
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:92
void _CPU_Context_volatile_clobber(uintptr_t pattern)
Clobbers all volatile registers with values derived from the pattern parameter.
Definition: cpu.h:1104
This defines the minimal set of integer and processor state registers that must be saved during a vol...
Definition: cpu.h:248
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:26
uint32_t reserved_for_alignment
This is the offset is reserved for alignment on an ISF.
Definition: cpu.h:717
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1461
This defines the set of integer and processor state registers that must be saved during an interrupt...
Definition: cpu.h:425
void _CPU_ISR_Set_level(uint32_t level)
Sets the hardware interrupt level by the level value.
Definition: cpu.c:62
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
void _CPU_Context_restore_fp(Context_Control_fp **fp_context_ptr)
This routine restores the floating point context passed to it.
Definition: cpu.c:176
IBM/Motorola Power Pc Definitions.
void _CPU_Context_Initialize(Context_Control *the_context, uint32_t *stack_base, uint32_t size, uint32_t new_level, void *entry_point, bool is_fp, void *tls_area)
Initialize the context to a state suitable for starting a task after a context restore operation...
Definition: cpu.c:183
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: cpu.c:96
CPU_Counter_ticks _CPU_Counter_difference(CPU_Counter_ticks second, CPU_Counter_ticks first)
Returns the difference between the second and first CPU counter value.
Definition: cpu.h:1160
This defines the complete set of floating point registers that must be saved during any context switc...
Definition: cpu.h:294
void _CPU_Context_save_fp(Context_Control_fp **fp_context_ptr)
This routine saves the floating point context passed to it.
Definition: cpu.c:167
#define RTEMS_COMPILER_NO_RETURN_ATTRIBUTE
The following macro is a compiler specific way to indicate that the method will NOT return to the cal...
Definition: basedefs.h:162
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: arm-exception-frame-print.c:46
The set of registers that specifies the complete processor state.
Definition: cpu.h:671
#define CPU_MODES_INTERRUPT_MASK
The following defines the number of bits actually used in the interrupt field of the task mode...
Definition: cpu.h:375
PowerPc MSR and Registers Access Definitions.
uint32_t pc
This is the offset of the XXX on an ISF.
Definition: cpu.h:506
void * proc_ptr
XXX: Eventually proc_ptr needs to disappear!!!
Definition: basedefs.h:329