24 #ifndef _RTEMS_SCORE_CPU_H 25 #define _RTEMS_SCORE_CPU_H 47 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE 55 #define CPU_ISR_PASSES_FRAME_POINTER FALSE 64 #if ( SPARC_HAS_FPU == 1 ) 65 #define CPU_HARDWARE_FP TRUE 67 #define CPU_HARDWARE_FP FALSE 69 #define CPU_SOFTWARE_FP FALSE 78 #define CPU_ALL_TASKS_ARE_FP FALSE 88 #define CPU_IDLE_TASK_IS_FP FALSE 105 #define CPU_USE_DEFERRED_FP_SWITCH TRUE 107 #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE 119 #define CPU_STACK_GROWS_UP FALSE 122 #define CPU_CACHE_LINE_BYTES 32 138 #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( 16 ) 148 #define CPU_MODES_INTERRUPT_MASK 0x0000000F 150 #define CPU_MAXIMUM_PROCESSORS 32 178 void *structure_return_address;
194 #define CPU_STACK_FRAME_L0_OFFSET 0x00 195 #define CPU_STACK_FRAME_L1_OFFSET 0x08 196 #define CPU_STACK_FRAME_L2_OFFSET 0x10 197 #define CPU_STACK_FRAME_L3_OFFSET 0x18 198 #define CPU_STACK_FRAME_L4_OFFSET 0x20 199 #define CPU_STACK_FRAME_L5_OFFSET 0x28 200 #define CPU_STACK_FRAME_L6_OFFSET 0x30 201 #define CPU_STACK_FRAME_L7_OFFSET 0x38 202 #define CPU_STACK_FRAME_I0_OFFSET 0x40 203 #define CPU_STACK_FRAME_I1_OFFSET 0x48 204 #define CPU_STACK_FRAME_I2_OFFSET 0x50 205 #define CPU_STACK_FRAME_I3_OFFSET 0x58 206 #define CPU_STACK_FRAME_I4_OFFSET 0x60 207 #define CPU_STACK_FRAME_I5_OFFSET 0x68 208 #define CPU_STACK_FRAME_I6_FP_OFFSET 0x70 209 #define CPU_STACK_FRAME_I7_OFFSET 0x78 210 #define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x80 211 #define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x88 212 #define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x90 213 #define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x98 214 #define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0xA0 215 #define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0xA8 216 #define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0xB0 217 #define CPU_STACK_FRAME_PAD0_OFFSET 0xB8 219 #define SPARC64_MINIMUM_STACK_FRAME_SIZE 0xC0 277 uint32_t isr_dispatch_disable;
281 #define _CPU_Context_Get_SP( _context ) \ 290 #define G1_OFFSET 0x00 291 #define G2_OFFSET 0x08 292 #define G3_OFFSET 0x10 293 #define G4_OFFSET 0x18 294 #define G5_OFFSET 0x20 295 #define G6_OFFSET 0x28 296 #define G7_OFFSET 0x30 298 #define L0_OFFSET 0x38 299 #define L1_OFFSET 0x40 300 #define L2_OFFSET 0x48 301 #define L3_OFFSET 0x50 302 #define L4_OFFSET 0x58 303 #define L5_OFFSET 0x60 304 #define L6_OFFSET 0x68 305 #define L7_OFFSET 0x70 307 #define I0_OFFSET 0x78 308 #define I1_OFFSET 0x80 309 #define I2_OFFSET 0x88 310 #define I3_OFFSET 0x90 311 #define I4_OFFSET 0x98 312 #define I5_OFFSET 0xA0 313 #define I6_FP_OFFSET 0xA8 314 #define I7_OFFSET 0xB0 316 #define O0_OFFSET 0xB8 317 #define O1_OFFSET 0xC0 318 #define O2_OFFSET 0xC8 319 #define O3_OFFSET 0xD0 320 #define O4_OFFSET 0xD8 321 #define O5_OFFSET 0xE0 322 #define O6_SP_OFFSET 0xE8 323 #define O7_OFFSET 0xF0 325 #define ISR_DISPATCH_DISABLE_STACK_OFFSET 0xF8 326 #define ISR_PAD_OFFSET 0xFC 376 #define FO_OFFSET 0x00 377 #define F2_OFFSET 0x08 378 #define F4_OFFSET 0x10 379 #define F6_OFFSET 0x18 380 #define F8_OFFSET 0x20 381 #define F1O_OFFSET 0x28 382 #define F12_OFFSET 0x30 383 #define F14_OFFSET 0x38 384 #define F16_OFFSET 0x40 385 #define F18_OFFSET 0x48 386 #define F2O_OFFSET 0x50 387 #define F22_OFFSET 0x58 388 #define F24_OFFSET 0x60 389 #define F26_OFFSET 0x68 390 #define F28_OFFSET 0x70 391 #define F3O_OFFSET 0x78 392 #define F32_OFFSET 0x80 393 #define F34_OFFSET 0x88 394 #define F36_OFFSET 0x90 395 #define F38_OFFSET 0x98 396 #define F4O_OFFSET 0xA0 397 #define F42_OFFSET 0xA8 398 #define F44_OFFSET 0xB0 399 #define F46_OFFSET 0xB8 400 #define F48_OFFSET 0xC0 401 #define F5O_OFFSET 0xC8 402 #define F52_OFFSET 0xD0 403 #define F54_OFFSET 0xD8 404 #define F56_OFFSET 0xE0 405 #define F58_OFFSET 0xE8 406 #define F6O_OFFSET 0xF0 407 #define F62_OFFSET 0xF8 408 #define FSR_OFFSET 0x100 410 #define CONTEXT_CONTROL_FP_SIZE 0x108 456 #define ISF_TSTATE_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x00 457 #define ISF_TPC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x08 458 #define ISF_TNPC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x10 459 #define ISF_PIL_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x18 460 #define ISF_Y_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x20 461 #define ISF_G1_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x28 462 #define ISF_G2_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x30 463 #define ISF_G3_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x38 464 #define ISF_G4_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x40 465 #define ISF_G5_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x48 466 #define ISF_G6_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x50 467 #define ISF_G7_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x58 468 #define ISF_O0_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x60 469 #define ISF_O1_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x68 470 #define ISF_O2_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x70 471 #define ISF_O3_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x78 472 #define ISF_O4_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x80 473 #define ISF_O5_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x88 474 #define ISF_O6_SP_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x90 475 #define ISF_O7_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x98 476 #define ISF_TVEC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0xA0 478 #define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE SPARC64_MINIMUM_STACK_FRAME_SIZE + 0xA8 495 extern volatile uint32_t _CPU_ISR_Dispatch_disable;
518 uint32_t rdpr_tstate_g4;
519 uint32_t sethi_of_hh_handler_to_g2;
520 uint32_t or_g2_hm_handler_to_g2;
521 uint32_t sllx_g2_by_32_to_g2;
522 uint32_t sethi_of_handler_to_g3;
523 uint32_t or_g3_g2_to_g3;
524 uint32_t jmp_to_low_of_handler_plus_g3;
525 uint32_t mov_vector_g2;
544 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) 554 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 582 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 512 583 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 1023 585 #define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x200 586 #define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap) 587 #define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 512 ) 589 #define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 512) 596 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE 607 #define CPU_STACK_MINIMUM_SIZE (1024*8) 609 #define CPU_SIZEOF_POINTER 8 621 #define CPU_ALIGNMENT 8 635 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT 651 #define CPU_STACK_ALIGNMENT 16 653 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 665 #define _CPU_Initialize_vectors() 672 #define _CPU_ISR_Disable( _level ) \ 673 (_level) = sparc_disable_interrupts() 681 #define _CPU_ISR_Enable( _level ) \ 682 sparc_enable_interrupts( _level ) 691 #define _CPU_ISR_Flash( _level ) \ 692 sparc_flash_interrupts( _level ) 696 return ( level & SPARC_PSTATE_IE_MASK ) != 0;
705 #define _CPU_ISR_Set_level( _newlevel ) \ 706 sparc_enable_interrupts( _newlevel) 752 #define _CPU_Context_Initialization_at_thread_begin() \ 754 __asm__ volatile ("set _Thread_Handler,%%i7\n"::); \ 766 #define _CPU_Context_Restart_self( _the_context ) \ 767 _CPU_Context_restore( (_the_context) ); 778 #define _CPU_Context_Initialize_fp( _destination ) \ 780 *(*(_destination)) = _CPU_Null_fp_context; \ 793 #define _CPU_Fatal_halt( _source, _error ) \ 797 level = sparc_disable_interrupts(); \ 798 __asm__ volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \ 811 #if ( SPARC_HAS_BITSCAN == 0 ) 812 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE 814 #error "scan instruction not currently supported by RTEMS!!" 826 #if ( SPARC_HAS_BITSCAN == 1 ) 827 #error "scan instruction not currently supported by RTEMS!!" 842 typedef void ( *CPU_ISR_raw_handler )( void );
846 CPU_ISR_raw_handler new_handler,
847 CPU_ISR_raw_handler *old_handler
850 typedef void ( *CPU_ISR_handler )( uint32_t );
854 CPU_ISR_handler new_handler,
855 CPU_ISR_handler *old_handler
926 static inline uint32_t CPU_swap_u32(
930 uint32_t byte1, byte2, byte3, byte4, swapped;
932 byte4 = (value >> 24) & 0xff;
933 byte3 = (value >> 16) & 0xff;
934 byte2 = (value >> 8) & 0xff;
935 byte1 = value & 0xff;
937 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
941 #define CPU_swap_u16( value ) \ 942 (((value&0xff) << 8) | ((value >> 8)&0xff)) 950 static inline CPU_Counter_ticks _CPU_Counter_difference(
951 CPU_Counter_ticks second,
952 CPU_Counter_ticks first
955 return second - first;
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
Thread register context.
Definition: cpu.h:196
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:65
void _CPU_Context_restore_fp(Context_Control_fp **fp_context_ptr)
Definition: cpu.c:207
Interrupt stack frame (ISF).
Definition: cpu.h:306
void _CPU_Context_Initialize(Context_Control *context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
Initializes the CPU context.
Definition: epiphany-context-initialize.c:40
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
Information Required to Build RTEMS for a Particular Member of the SPARC Family.
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
SPARC basic context.
Definition: cpu.h:242
const CPU_Trap_table_entry _CPU_Trap_slot_template
Definition: cpu.c:156
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1202
#define RTEMS_NO_RETURN
Definition: basedefs.h:101
uint32_t _CPU_ISR_Get_level(void)
Definition: cpu.c:88
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.h:703
bool _CPU_ISR_Is_enabled(uint32_t level)
Returns true if interrupts are enabled in the specified ISR level, otherwise returns false...
Definition: cpu.h:381
void _CPU_Context_restore(Context_Control *new_context) RTEMS_NO_RETURN
Definition: cpu_asm.c:111
uintptr_t CPU_Uint32ptr
Definition: cpu.h:668
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
unsigned size
Definition: tte.h:74
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
SPARC specific RTEMS ISR installer.
Definition: cpu.h:605
void _CPU_Context_save_fp(Context_Control_fp **fp_context_ptr)
Definition: cpu.c:198
The set of registers that specifies the complete processor state.
Definition: cpu.h:635
Context_Control_fp _CPU_Null_fp_context
Definition: cpu.c:45