RTEMS  5.0.0
Data Structures | Macros | Typedefs | Functions | Variables
cpu.h File Reference

SPARC64 CPU Department Source. More...

#include <rtems/score/basedefs.h>
#include <rtems/score/sparc64.h>

Go to the source code of this file.

Data Structures

struct  SPARC64_Minimum_stack_frame
 
struct  Context_Control
 Thread register context. More...
 
struct  Context_Control_fp
 SPARC basic context. More...
 
struct  CPU_Interrupt_frame
 Interrupt stack frame (ISF). More...
 
struct  CPU_Trap_table_entry
 

Macros

#define CPU_SIMPLE_VECTORED_INTERRUPTS   TRUE
 
#define CPU_ISR_PASSES_FRAME_POINTER   FALSE
 
#define CPU_HARDWARE_FP   FALSE
 
#define CPU_SOFTWARE_FP   FALSE
 
#define CPU_ALL_TASKS_ARE_FP   FALSE
 
#define CPU_IDLE_TASK_IS_FP   FALSE
 
#define CPU_USE_DEFERRED_FP_SWITCH   TRUE
 
#define CPU_ENABLE_ROBUST_THREAD_DISPATCH   FALSE
 
#define CPU_STACK_GROWS_UP   FALSE
 
#define CPU_CACHE_LINE_BYTES   32
 
#define CPU_STRUCTURE_ALIGNMENT   RTEMS_ALIGNED( 16 )
 
#define CPU_MODES_INTERRUPT_MASK   0x0000000F
 
#define CPU_MAXIMUM_PROCESSORS   32
 
#define CPU_STACK_FRAME_L0_OFFSET   0x00
 
#define CPU_STACK_FRAME_L1_OFFSET   0x08
 
#define CPU_STACK_FRAME_L2_OFFSET   0x10
 
#define CPU_STACK_FRAME_L3_OFFSET   0x18
 
#define CPU_STACK_FRAME_L4_OFFSET   0x20
 
#define CPU_STACK_FRAME_L5_OFFSET   0x28
 
#define CPU_STACK_FRAME_L6_OFFSET   0x30
 
#define CPU_STACK_FRAME_L7_OFFSET   0x38
 
#define CPU_STACK_FRAME_I0_OFFSET   0x40
 
#define CPU_STACK_FRAME_I1_OFFSET   0x48
 
#define CPU_STACK_FRAME_I2_OFFSET   0x50
 
#define CPU_STACK_FRAME_I3_OFFSET   0x58
 
#define CPU_STACK_FRAME_I4_OFFSET   0x60
 
#define CPU_STACK_FRAME_I5_OFFSET   0x68
 
#define CPU_STACK_FRAME_I6_FP_OFFSET   0x70
 
#define CPU_STACK_FRAME_I7_OFFSET   0x78
 
#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET   0x80
 
#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET   0x88
 
#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET   0x90
 
#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET   0x98
 
#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET   0xA0
 
#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET   0xA8
 
#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET   0xB0
 
#define CPU_STACK_FRAME_PAD0_OFFSET   0xB8
 
#define SPARC64_MINIMUM_STACK_FRAME_SIZE   0xC0
 
#define _CPU_Context_Get_SP(_context)   (_context)->o6_sp
 
#define G1_OFFSET   0x00
 
#define G2_OFFSET   0x08
 
#define G3_OFFSET   0x10
 
#define G4_OFFSET   0x18
 
#define G5_OFFSET   0x20
 
#define G6_OFFSET   0x28
 
#define G7_OFFSET   0x30
 
#define L0_OFFSET   0x38
 
#define L1_OFFSET   0x40
 
#define L2_OFFSET   0x48
 
#define L3_OFFSET   0x50
 
#define L4_OFFSET   0x58
 
#define L5_OFFSET   0x60
 
#define L6_OFFSET   0x68
 
#define L7_OFFSET   0x70
 
#define I0_OFFSET   0x78
 
#define I1_OFFSET   0x80
 
#define I2_OFFSET   0x88
 
#define I3_OFFSET   0x90
 
#define I4_OFFSET   0x98
 
#define I5_OFFSET   0xA0
 
#define I6_FP_OFFSET   0xA8
 
#define I7_OFFSET   0xB0
 
#define O0_OFFSET   0xB8
 
#define O1_OFFSET   0xC0
 
#define O2_OFFSET   0xC8
 
#define O3_OFFSET   0xD0
 
#define O4_OFFSET   0xD8
 
#define O5_OFFSET   0xE0
 
#define O6_SP_OFFSET   0xE8
 
#define O7_OFFSET   0xF0
 
#define ISR_DISPATCH_DISABLE_STACK_OFFSET   0xF8
 
#define ISR_PAD_OFFSET   0xFC
 
#define FO_OFFSET   0x00
 
#define F2_OFFSET   0x08
 
#define F4_OFFSET   0x10
 
#define F6_OFFSET   0x18
 
#define F8_OFFSET   0x20
 
#define F1O_OFFSET   0x28
 
#define F12_OFFSET   0x30
 
#define F14_OFFSET   0x38
 
#define F16_OFFSET   0x40
 
#define F18_OFFSET   0x48
 
#define F2O_OFFSET   0x50
 
#define F22_OFFSET   0x58
 
#define F24_OFFSET   0x60
 
#define F26_OFFSET   0x68
 
#define F28_OFFSET   0x70
 
#define F3O_OFFSET   0x78
 
#define F32_OFFSET   0x80
 
#define F34_OFFSET   0x88
 
#define F36_OFFSET   0x90
 
#define F38_OFFSET   0x98
 
#define F4O_OFFSET   0xA0
 
#define F42_OFFSET   0xA8
 
#define F44_OFFSET   0xB0
 
#define F46_OFFSET   0xB8
 
#define F48_OFFSET   0xC0
 
#define F5O_OFFSET   0xC8
 
#define F52_OFFSET   0xD0
 
#define F54_OFFSET   0xD8
 
#define F56_OFFSET   0xE0
 
#define F58_OFFSET   0xE8
 
#define F6O_OFFSET   0xF0
 
#define F62_OFFSET   0xF8
 
#define FSR_OFFSET   0x100
 
#define CONTEXT_CONTROL_FP_SIZE   0x108
 
#define ISF_TSTATE_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x00
 
#define ISF_TPC_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x08
 
#define ISF_TNPC_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x10
 
#define ISF_PIL_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x18
 
#define ISF_Y_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x20
 
#define ISF_G1_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x28
 
#define ISF_G2_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x30
 
#define ISF_G3_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x38
 
#define ISF_G4_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x40
 
#define ISF_G5_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x48
 
#define ISF_G6_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x50
 
#define ISF_G7_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x58
 
#define ISF_O0_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x60
 
#define ISF_O1_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x68
 
#define ISF_O2_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x70
 
#define ISF_O3_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x78
 
#define ISF_O4_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x80
 
#define ISF_O5_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x88
 
#define ISF_O6_SP_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x90
 
#define ISF_O7_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x98
 
#define ISF_TVEC_OFFSET   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0xA0
 
#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE   SPARC64_MINIMUM_STACK_FRAME_SIZE + 0xA8
 
#define CPU_CONTEXT_FP_SIZE   sizeof( Context_Control_fp )
 
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK   1024
 
#define CPU_INTERRUPT_NUMBER_OF_VECTORS   512
 
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER   1023
 
#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK   0x200
 
#define SPARC_ASYNCHRONOUS_TRAP(_trap)   (_trap)
 
#define SPARC_SYNCHRONOUS_TRAP(_trap)   ((_trap) + 512 )
 
#define SPARC_REAL_TRAP_NUMBER(_trap)   ((_trap) % 512)
 
#define CPU_PROVIDES_ISR_IS_IN_PROGRESS   FALSE
 
#define CPU_STACK_MINIMUM_SIZE   (1024*8)
 
#define CPU_SIZEOF_POINTER   8
 
#define CPU_ALIGNMENT   8
 
#define CPU_HEAP_ALIGNMENT   CPU_ALIGNMENT
 
#define CPU_STACK_ALIGNMENT   16
 
#define CPU_INTERRUPT_STACK_ALIGNMENT   CPU_CACHE_LINE_BYTES
 
#define _CPU_Initialize_vectors()
 
#define _CPU_ISR_Disable(_level)   (_level) = sparc_disable_interrupts()
 
#define _CPU_ISR_Enable(_level)   sparc_enable_interrupts( _level )
 
#define _CPU_ISR_Flash(_level)   sparc_flash_interrupts( _level )
 
#define _CPU_ISR_Set_level(_newlevel)   sparc_enable_interrupts( _newlevel)
 
#define _CPU_Context_Initialization_at_thread_begin()
 
#define _CPU_Context_Restart_self(_the_context)   _CPU_Context_restore( (_the_context) );
 
#define _CPU_Context_Initialize_fp(_destination)
 
#define _CPU_Fatal_halt(_source, _error)
 
#define CPU_USE_GENERIC_BITFIELD_CODE   TRUE
 
#define CPU_swap_u16(value)   (((value&0xff) << 8) | ((value >> 8)&0xff))
 

Typedefs

typedef void(* CPU_ISR_raw_handler) (void)
 
typedef void(* CPU_ISR_handler) (uint32_t)
 
typedef CPU_Interrupt_frame CPU_Exception_frame
 
typedef uint32_t CPU_Counter_ticks
 
typedef uintptr_t CPU_Uint32ptr
 

Functions

RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled (uint32_t level)
 Returns true if interrupts are enabled in the specified ISR level, otherwise returns false. More...
 
uint32_t _CPU_ISR_Get_level (void)
 Returns the interrupt level of the executing thread. More...
 
void _CPU_Context_Initialize (Context_Control *the_context, void *stack_base, uint32_t size, uint32_t new_level, void *entry_point, bool is_fp, void *tls_area)
 
void _CPU_Initialize (void)
 CPU initialization. More...
 
void _CPU_ISR_install_raw_handler (uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
 SPARC specific raw ISR installer. More...
 
void _CPU_ISR_install_vector (uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
 SPARC specific RTEMS ISR installer. More...
 
void * _CPU_Thread_Idle_body (uintptr_t ignored)
 
void _CPU_Context_switch (Context_Control *run, Context_Control *heir)
 CPU switch context. More...
 
void _CPU_Context_restore (Context_Control *new_context) RTEMS_NO_RETURN
 SPARC specific context restore. More...
 
void _CPU_Context_save_fp (Context_Control_fp **fp_context_ptr)
 
void _CPU_Context_restore_fp (Context_Control_fp **fp_context_ptr)
 
void _CPU_Exception_frame_print (const CPU_Exception_frame *frame)
 Prints the exception frame via printk(). More...
 
uint32_t _CPU_Counter_frequency (void)
 Returns the current CPU counter frequency in Hz. More...
 
CPU_Counter_ticks _CPU_Counter_read (void)
 Returns the current CPU counter value. More...
 

Variables

Context_Control_fp _CPU_Null_fp_context
 
volatile uint32_t _CPU_ISR_Dispatch_disable
 
const CPU_Trap_table_entry _CPU_Trap_slot_template
 

Detailed Description

SPARC64 CPU Department Source.

This include file contains information pertaining to the port of the executive to the SPARC64 processor.

Macro Definition Documentation

◆ _CPU_Context_Initialization_at_thread_begin

#define _CPU_Context_Initialization_at_thread_begin ( )
Value:
do { \
__asm__ volatile ("set _Thread_Handler,%%i7\n"::); \
} while (0)

◆ _CPU_Context_Initialize_fp

#define _CPU_Context_Initialize_fp (   _destination)
Value:
do { \
*(*(_destination)) = _CPU_Null_fp_context; \
} while (0)
Context_Control_fp _CPU_Null_fp_context
Definition: cpu.c:45

◆ _CPU_Fatal_halt

#define _CPU_Fatal_halt (   _source,
  _error 
)
Value:
do { \
uint32_t level; \
\
level = sparc_disable_interrupts(); \
__asm__ volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \
while (1); /* loop forever */ \
} while (0)

Typedef Documentation

◆ CPU_Uint32ptr

typedef uintptr_t CPU_Uint32ptr

Type that can store a 32-bit integer or a pointer.

Variable Documentation

◆ _CPU_Trap_slot_template

const CPU_Trap_table_entry _CPU_Trap_slot_template

This is the set of opcodes for the instructions loaded into a trap table entry. The routine which installs a handler is responsible for filling in the fields for the _handler address and the _vector trap type.

The constants following this structure are masks for the fields which must be filled in when the handler is installed.