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#define | CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
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#define | CPU_ISR_PASSES_FRAME_POINTER FALSE |
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#define | CPU_HARDWARE_FP FALSE |
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#define | CPU_SOFTWARE_FP FALSE |
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#define | CPU_ALL_TASKS_ARE_FP FALSE |
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#define | CPU_IDLE_TASK_IS_FP FALSE |
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#define | CPU_USE_DEFERRED_FP_SWITCH TRUE |
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#define | CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
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#define | CPU_STACK_GROWS_UP FALSE |
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#define | CPU_CACHE_LINE_BYTES 32 |
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#define | CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( 16 ) |
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#define | CPU_MODES_INTERRUPT_MASK 0x0000000F |
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#define | CPU_MAXIMUM_PROCESSORS 32 |
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#define | CPU_STACK_FRAME_L0_OFFSET 0x00 |
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#define | CPU_STACK_FRAME_L1_OFFSET 0x08 |
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#define | CPU_STACK_FRAME_L2_OFFSET 0x10 |
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#define | CPU_STACK_FRAME_L3_OFFSET 0x18 |
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#define | CPU_STACK_FRAME_L4_OFFSET 0x20 |
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#define | CPU_STACK_FRAME_L5_OFFSET 0x28 |
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#define | CPU_STACK_FRAME_L6_OFFSET 0x30 |
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#define | CPU_STACK_FRAME_L7_OFFSET 0x38 |
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#define | CPU_STACK_FRAME_I0_OFFSET 0x40 |
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#define | CPU_STACK_FRAME_I1_OFFSET 0x48 |
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#define | CPU_STACK_FRAME_I2_OFFSET 0x50 |
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#define | CPU_STACK_FRAME_I3_OFFSET 0x58 |
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#define | CPU_STACK_FRAME_I4_OFFSET 0x60 |
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#define | CPU_STACK_FRAME_I5_OFFSET 0x68 |
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#define | CPU_STACK_FRAME_I6_FP_OFFSET 0x70 |
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#define | CPU_STACK_FRAME_I7_OFFSET 0x78 |
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#define | CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x80 |
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#define | CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x88 |
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#define | CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x90 |
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#define | CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x98 |
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#define | CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0xA0 |
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#define | CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0xA8 |
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#define | CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0xB0 |
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#define | CPU_STACK_FRAME_PAD0_OFFSET 0xB8 |
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#define | SPARC64_MINIMUM_STACK_FRAME_SIZE 0xC0 |
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#define | _CPU_Context_Get_SP(_context) (_context)->o6_sp |
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#define | G1_OFFSET 0x00 |
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#define | G2_OFFSET 0x08 |
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#define | G3_OFFSET 0x10 |
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#define | G4_OFFSET 0x18 |
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#define | G5_OFFSET 0x20 |
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#define | G6_OFFSET 0x28 |
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#define | G7_OFFSET 0x30 |
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#define | L0_OFFSET 0x38 |
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#define | L1_OFFSET 0x40 |
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#define | L2_OFFSET 0x48 |
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#define | L3_OFFSET 0x50 |
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#define | L4_OFFSET 0x58 |
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#define | L5_OFFSET 0x60 |
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#define | L6_OFFSET 0x68 |
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#define | L7_OFFSET 0x70 |
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#define | I0_OFFSET 0x78 |
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#define | I1_OFFSET 0x80 |
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#define | I2_OFFSET 0x88 |
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#define | I3_OFFSET 0x90 |
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#define | I4_OFFSET 0x98 |
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#define | I5_OFFSET 0xA0 |
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#define | I6_FP_OFFSET 0xA8 |
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#define | I7_OFFSET 0xB0 |
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#define | O0_OFFSET 0xB8 |
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#define | O1_OFFSET 0xC0 |
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#define | O2_OFFSET 0xC8 |
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#define | O3_OFFSET 0xD0 |
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#define | O4_OFFSET 0xD8 |
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#define | O5_OFFSET 0xE0 |
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#define | O6_SP_OFFSET 0xE8 |
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#define | O7_OFFSET 0xF0 |
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#define | ISR_DISPATCH_DISABLE_STACK_OFFSET 0xF8 |
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#define | ISR_PAD_OFFSET 0xFC |
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#define | FO_OFFSET 0x00 |
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#define | F2_OFFSET 0x08 |
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#define | F4_OFFSET 0x10 |
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#define | F6_OFFSET 0x18 |
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#define | F8_OFFSET 0x20 |
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#define | F1O_OFFSET 0x28 |
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#define | F12_OFFSET 0x30 |
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#define | F14_OFFSET 0x38 |
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#define | F16_OFFSET 0x40 |
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#define | F18_OFFSET 0x48 |
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#define | F2O_OFFSET 0x50 |
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#define | F22_OFFSET 0x58 |
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#define | F24_OFFSET 0x60 |
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#define | F26_OFFSET 0x68 |
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#define | F28_OFFSET 0x70 |
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#define | F3O_OFFSET 0x78 |
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#define | F32_OFFSET 0x80 |
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#define | F34_OFFSET 0x88 |
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#define | F36_OFFSET 0x90 |
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#define | F38_OFFSET 0x98 |
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#define | F4O_OFFSET 0xA0 |
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#define | F42_OFFSET 0xA8 |
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#define | F44_OFFSET 0xB0 |
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#define | F46_OFFSET 0xB8 |
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#define | F48_OFFSET 0xC0 |
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#define | F5O_OFFSET 0xC8 |
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#define | F52_OFFSET 0xD0 |
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#define | F54_OFFSET 0xD8 |
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#define | F56_OFFSET 0xE0 |
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#define | F58_OFFSET 0xE8 |
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#define | F6O_OFFSET 0xF0 |
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#define | F62_OFFSET 0xF8 |
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#define | FSR_OFFSET 0x100 |
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#define | CONTEXT_CONTROL_FP_SIZE 0x108 |
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#define | ISF_TSTATE_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x00 |
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#define | ISF_TPC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x08 |
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#define | ISF_TNPC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x10 |
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#define | ISF_PIL_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x18 |
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#define | ISF_Y_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x20 |
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#define | ISF_G1_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x28 |
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#define | ISF_G2_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x30 |
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#define | ISF_G3_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x38 |
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#define | ISF_G4_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x40 |
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#define | ISF_G5_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x48 |
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#define | ISF_G6_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x50 |
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#define | ISF_G7_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x58 |
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#define | ISF_O0_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x60 |
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#define | ISF_O1_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x68 |
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#define | ISF_O2_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x70 |
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#define | ISF_O3_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x78 |
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#define | ISF_O4_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x80 |
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#define | ISF_O5_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x88 |
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#define | ISF_O6_SP_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x90 |
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#define | ISF_O7_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0x98 |
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#define | ISF_TVEC_OFFSET SPARC64_MINIMUM_STACK_FRAME_SIZE + 0xA0 |
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#define | CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE SPARC64_MINIMUM_STACK_FRAME_SIZE + 0xA8 |
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#define | CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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#define | CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 |
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#define | CPU_INTERRUPT_NUMBER_OF_VECTORS 512 |
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#define | CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 1023 |
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#define | SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x200 |
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#define | SPARC_ASYNCHRONOUS_TRAP(_trap) (_trap) |
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#define | SPARC_SYNCHRONOUS_TRAP(_trap) ((_trap) + 512 ) |
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#define | SPARC_REAL_TRAP_NUMBER(_trap) ((_trap) % 512) |
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#define | CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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#define | CPU_STACK_MINIMUM_SIZE (1024*8) |
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#define | CPU_SIZEOF_POINTER 8 |
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#define | CPU_ALIGNMENT 8 |
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#define | CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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#define | CPU_STACK_ALIGNMENT 16 |
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#define | CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
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#define | _CPU_Initialize_vectors() |
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#define | _CPU_ISR_Disable(_level) (_level) = sparc_disable_interrupts() |
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#define | _CPU_ISR_Enable(_level) sparc_enable_interrupts( _level ) |
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#define | _CPU_ISR_Flash(_level) sparc_flash_interrupts( _level ) |
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#define | _CPU_ISR_Set_level(_newlevel) sparc_enable_interrupts( _newlevel) |
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#define | _CPU_Context_Initialization_at_thread_begin() |
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#define | _CPU_Context_Restart_self(_the_context) _CPU_Context_restore( (_the_context) ); |
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#define | _CPU_Context_Initialize_fp(_destination) |
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#define | _CPU_Fatal_halt(_source, _error) |
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#define | CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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#define | CPU_swap_u16(value) (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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RTEMS_INLINE_ROUTINE bool | _CPU_ISR_Is_enabled (uint32_t level) |
| Returns true if interrupts are enabled in the specified ISR level, otherwise returns false. More...
|
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uint32_t | _CPU_ISR_Get_level (void) |
| Returns the interrupt level of the executing thread. More...
|
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void | _CPU_Context_Initialize (Context_Control *the_context, void *stack_base, uint32_t size, uint32_t new_level, void *entry_point, bool is_fp, void *tls_area) |
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void | _CPU_Initialize (void) |
| CPU initialization. More...
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void | _CPU_ISR_install_raw_handler (uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler) |
| SPARC specific raw ISR installer. More...
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void | _CPU_ISR_install_vector (uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler) |
| SPARC specific RTEMS ISR installer. More...
|
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void * | _CPU_Thread_Idle_body (uintptr_t ignored) |
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void | _CPU_Context_switch (Context_Control *run, Context_Control *heir) |
| CPU switch context. More...
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void | _CPU_Context_restore (Context_Control *new_context) RTEMS_NO_RETURN |
| SPARC specific context restore. More...
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void | _CPU_Context_save_fp (Context_Control_fp **fp_context_ptr) |
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void | _CPU_Context_restore_fp (Context_Control_fp **fp_context_ptr) |
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void | _CPU_Exception_frame_print (const CPU_Exception_frame *frame) |
| Prints the exception frame via printk(). More...
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uint32_t | _CPU_Counter_frequency (void) |
| Returns the current CPU counter frequency in Hz. More...
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CPU_Counter_ticks | _CPU_Counter_read (void) |
| Returns the current CPU counter value. More...
|
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SPARC64 CPU Department Source.
This include file contains information pertaining to the port of the executive to the SPARC64 processor.