37 #ifndef _RTEMS_SCORE_CPU_H 38 #define _RTEMS_SCORE_CPU_H 41 #if defined(RTEMS_PARAVIRT) 42 #include <rtems/score/paravirt.h> 65 #define CPU_STACK_GROWS_UP FALSE 67 #define CPU_CACHE_LINE_BYTES PPC_STRUCTURE_ALIGNMENT 69 #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) 87 #if ( PPC_HAS_FPU == 1 ) 88 #define CPU_HARDWARE_FP TRUE 89 #define CPU_SOFTWARE_FP FALSE 91 #define CPU_HARDWARE_FP FALSE 92 #define CPU_SOFTWARE_FP FALSE 108 #define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP 122 #define CPU_IDLE_TASK_IS_FP FALSE 124 #define CPU_MAXIMUM_PROCESSORS 32 166 #define PPC_GPR_TYPE uintptr_t 167 #if defined(__powerpc64__) 168 #define PPC_GPR_SIZE 8 169 #define PPC_GPR_LOAD ld 170 #define PPC_GPR_STORE std 172 #define PPC_GPR_SIZE 4 173 #define PPC_GPR_LOAD lwz 174 #define PPC_GPR_STORE stw 177 #define PPC_GPR_TYPE uint64_t 178 #define PPC_GPR_SIZE 8 179 #define PPC_GPR_LOAD evldd 180 #define PPC_GPR_STORE evstdd 183 #if defined(__powerpc64__) 184 #define PPC_REG_SIZE 8 185 #define PPC_REG_LOAD ld 186 #define PPC_REG_STORE std 187 #define PPC_REG_STORE_UPDATE stdu 188 #define PPC_REG_CMP cmpd 190 #define PPC_REG_SIZE 4 191 #define PPC_REG_LOAD lwz 192 #define PPC_REG_STORE stw 193 #define PPC_REG_STORE_UPDATE stwu 194 #define PPC_REG_CMP cmpw 227 uint32_t isr_dispatch_disable;
228 uint32_t reserved_for_alignment;
229 #if defined(PPC_MULTILIB_ALTIVEC) 243 #elif defined(__ALTIVEC__) 253 uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE];
255 #if defined(PPC_MULTILIB_FPU) 281 #if defined(RTEMS_SMP) 282 volatile uint32_t is_executing;
288 PPC_DEFAULT_CACHE_LINE_SIZE
290 + (
sizeof(
ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0
292 : PPC_DEFAULT_CACHE_LINE_SIZE
293 -
sizeof(
ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE)
299 uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE;
300 uintptr_t mask = clsz - 1;
301 uintptr_t addr = (uintptr_t) context;
306 #define _CPU_Context_Get_SP( _context ) \ 307 ppc_get_context(_context)->gpr1 310 static inline bool _CPU_Context_Get_is_executing(
314 return ppc_get_context(context)->is_executing;
317 static inline void _CPU_Context_Set_is_executing(
322 ppc_get_context(context)->is_executing = is_executing;
327 #define PPC_CONTEXT_OFFSET_MSR (PPC_DEFAULT_CACHE_LINE_SIZE) 328 #define PPC_CONTEXT_OFFSET_CR (PPC_DEFAULT_CACHE_LINE_SIZE + 4) 329 #define PPC_CONTEXT_OFFSET_GPR1 (PPC_DEFAULT_CACHE_LINE_SIZE + 8) 330 #define PPC_CONTEXT_OFFSET_LR (PPC_DEFAULT_CACHE_LINE_SIZE + PPC_REG_SIZE + 8) 332 #define PPC_CONTEXT_GPR_OFFSET( gpr ) \ 333 (((gpr) - 14) * PPC_GPR_SIZE + \ 334 PPC_DEFAULT_CACHE_LINE_SIZE + 8 + 2 * PPC_REG_SIZE) 336 #define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 ) 337 #define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 ) 338 #define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 ) 339 #define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 ) 340 #define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 ) 341 #define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 ) 342 #define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 ) 343 #define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 ) 344 #define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 ) 345 #define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 ) 346 #define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 ) 347 #define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 ) 348 #define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 ) 349 #define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 ) 350 #define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 ) 351 #define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 ) 352 #define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 ) 353 #define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 ) 354 #define PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE PPC_CONTEXT_GPR_OFFSET( 32 ) 356 #ifdef PPC_MULTILIB_ALTIVEC 357 #define PPC_CONTEXT_OFFSET_V( v ) \ 358 ( ( ( v ) - 20 ) * 16 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8) 359 #define PPC_CONTEXT_OFFSET_V20 PPC_CONTEXT_OFFSET_V( 20 ) 360 #define PPC_CONTEXT_OFFSET_V21 PPC_CONTEXT_OFFSET_V( 21 ) 361 #define PPC_CONTEXT_OFFSET_V22 PPC_CONTEXT_OFFSET_V( 22 ) 362 #define PPC_CONTEXT_OFFSET_V23 PPC_CONTEXT_OFFSET_V( 23 ) 363 #define PPC_CONTEXT_OFFSET_V24 PPC_CONTEXT_OFFSET_V( 24 ) 364 #define PPC_CONTEXT_OFFSET_V25 PPC_CONTEXT_OFFSET_V( 25 ) 365 #define PPC_CONTEXT_OFFSET_V26 PPC_CONTEXT_OFFSET_V( 26 ) 366 #define PPC_CONTEXT_OFFSET_V27 PPC_CONTEXT_OFFSET_V( 27 ) 367 #define PPC_CONTEXT_OFFSET_V28 PPC_CONTEXT_OFFSET_V( 28 ) 368 #define PPC_CONTEXT_OFFSET_V29 PPC_CONTEXT_OFFSET_V( 29 ) 369 #define PPC_CONTEXT_OFFSET_V30 PPC_CONTEXT_OFFSET_V( 30 ) 370 #define PPC_CONTEXT_OFFSET_V31 PPC_CONTEXT_OFFSET_V( 31 ) 371 #define PPC_CONTEXT_OFFSET_VRSAVE PPC_CONTEXT_OFFSET_V( 32 ) 372 #define PPC_CONTEXT_OFFSET_F( f ) \ 373 ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_VRSAVE + 8 ) 375 #define PPC_CONTEXT_OFFSET_F( f ) \ 376 ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8 ) 379 #ifdef PPC_MULTILIB_FPU 380 #define PPC_CONTEXT_OFFSET_F14 PPC_CONTEXT_OFFSET_F( 14 ) 381 #define PPC_CONTEXT_OFFSET_F15 PPC_CONTEXT_OFFSET_F( 15 ) 382 #define PPC_CONTEXT_OFFSET_F16 PPC_CONTEXT_OFFSET_F( 16 ) 383 #define PPC_CONTEXT_OFFSET_F17 PPC_CONTEXT_OFFSET_F( 17 ) 384 #define PPC_CONTEXT_OFFSET_F18 PPC_CONTEXT_OFFSET_F( 18 ) 385 #define PPC_CONTEXT_OFFSET_F19 PPC_CONTEXT_OFFSET_F( 19 ) 386 #define PPC_CONTEXT_OFFSET_F20 PPC_CONTEXT_OFFSET_F( 20 ) 387 #define PPC_CONTEXT_OFFSET_F21 PPC_CONTEXT_OFFSET_F( 21 ) 388 #define PPC_CONTEXT_OFFSET_F22 PPC_CONTEXT_OFFSET_F( 22 ) 389 #define PPC_CONTEXT_OFFSET_F23 PPC_CONTEXT_OFFSET_F( 23 ) 390 #define PPC_CONTEXT_OFFSET_F24 PPC_CONTEXT_OFFSET_F( 24 ) 391 #define PPC_CONTEXT_OFFSET_F25 PPC_CONTEXT_OFFSET_F( 25 ) 392 #define PPC_CONTEXT_OFFSET_F26 PPC_CONTEXT_OFFSET_F( 26 ) 393 #define PPC_CONTEXT_OFFSET_F27 PPC_CONTEXT_OFFSET_F( 27 ) 394 #define PPC_CONTEXT_OFFSET_F28 PPC_CONTEXT_OFFSET_F( 28 ) 395 #define PPC_CONTEXT_OFFSET_F29 PPC_CONTEXT_OFFSET_F( 29 ) 396 #define PPC_CONTEXT_OFFSET_F30 PPC_CONTEXT_OFFSET_F( 30 ) 397 #define PPC_CONTEXT_OFFSET_F31 PPC_CONTEXT_OFFSET_F( 31 ) 400 #if defined(PPC_MULTILIB_FPU) 401 #define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_F( 32 ) 402 #elif defined(PPC_MULTILIB_ALTIVEC) 403 #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_OFFSET_VRSAVE + 4) 404 #elif defined(__ALTIVEC__) 405 #define PPC_CONTEXT_VOLATILE_SIZE \ 406 (PPC_CONTEXT_GPR_OFFSET( 32 ) + 8 \ 407 + 16 * 12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE) 409 #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_GPR_OFFSET( 32 ) + 8) 412 #define PPC_CONTEXT_OFFSET_TP PPC_CONTEXT_VOLATILE_SIZE 415 #define PPC_CONTEXT_OFFSET_IS_EXECUTING \ 416 (PPC_CONTEXT_OFFSET_TP + PPC_REG_SIZE) 421 #if (PPC_HAS_FPU == 1) 428 #if (PPC_HAS_DOUBLE == 1) 452 #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE 460 #define CPU_ISR_PASSES_FRAME_POINTER FALSE 498 #define CPU_USE_DEFERRED_FP_SWITCH FALSE 500 #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE 524 #define CPU_MODES_INTERRUPT_MASK 0x00000001 533 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) 541 #define CPU_STACK_CHECK_PATTERN_INITIALIZER \ 542 { 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ 543 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ 544 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ 545 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ 546 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ 547 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ 548 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ 549 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06 } 557 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 566 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE 581 return ( level & MSR_EE ) != 0;
584 #if !defined(PPC_DISABLE_INLINE_ISR_DISABLE_ENABLE) 590 if (msr & MSR_EE)
return 0;
599 msr |= ppc_interrupt_get_disable_mask();
602 msr &= ~ppc_interrupt_get_disable_mask();
608 uint32_t ppc_get_interrupt_level(
void );
609 void ppc_set_interrupt_level( uint32_t level );
610 #define _CPU_ISR_Get_level( _new_level ) ppc_get_interrupt_level() 611 #define _CPU_ISR_Set_level( _new_level ) ppc_set_interrupt_level(_new_level) 616 #define _CPU_Fatal_halt( _source, _error ) \ 618 ppc_interrupt_disable(); \ 625 : "r" (_source), "r" (_error) \ 635 #define CPU_STACK_MINIMUM_SIZE (1024*8) 637 #if defined(__powerpc64__) 638 #define CPU_SIZEOF_POINTER 8 640 #define CPU_SIZEOF_POINTER 4 648 #define CPU_ALIGNMENT (PPC_ALIGNMENT) 662 #define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) 673 #define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) 675 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 698 static inline uint32_t CPU_swap_u32(
704 __asm__ volatile(
"rlwimi %0,%1,8,24,31;" 705 "rlwimi %0,%1,24,16,23;" 706 "rlwimi %0,%1,8,8,15;" 707 "rlwimi %0,%1,24,0,7;" :
708 "=&r" ((swapped)) :
"r" ((value)));
713 #define CPU_swap_u16( value ) \ 714 (((value&0xff) << 8) | ((value >> 8)&0xff)) 722 CPU_Counter_ticks value;
724 #if defined(__PPC_CPU_E6500__) 726 __asm__ volatile(
"mfspr %0, 526" :
"=r" (value) );
727 #elif defined(mpc860) 728 __asm__ volatile(
"mftb %0" :
"=r" (value) );
730 __asm__ volatile(
"mfspr %0, 268" :
"=r" (value) );
736 static inline CPU_Counter_ticks _CPU_Counter_difference(
737 CPU_Counter_ticks second,
738 CPU_Counter_ticks first
741 return second - first;
786 #define _CPU_Context_Restart_self( _the_context ) \ 787 _CPU_Context_restore( (_the_context) ); 801 #define _CPU_Context_Initialize_fp( _destination ) \ 802 memset( *(_destination), 0, sizeof( **(_destination) ) ) 810 #define CPU_USE_GENERIC_BITFIELD_CODE FALSE 867 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ 869 __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ 871 (_output) = (_output) - 16; \ 882 #define _CPU_Priority_Mask( _bit_number ) \ 883 ( 0x8000u >> (_bit_number) ) 892 #define _CPU_Priority_bits_index( _priority ) \ 957 uint32_t _CPU_SMP_Initialize(
void );
959 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
961 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
963 void _CPU_SMP_Prepare_start_multitasking(
void );
965 static inline uint32_t _CPU_SMP_Get_current_processor(
void )
978 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
980 static inline void _CPU_SMP_Processor_event_broadcast(
void )
982 __asm__ volatile (
"" : : :
"memory" );
985 static inline void _CPU_SMP_Processor_event_receive(
void )
987 __asm__ volatile (
"" : : :
"memory" );
994 uint32_t _EXC_number;
995 uint32_t RESERVED_FOR_ALIGNMENT_0;
1000 uintptr_t RESERVED_FOR_ALIGNMENT_1;
1002 uint32_t EXC_SPEFSCR;
1037 uintptr_t RESERVED_FOR_ALIGNMENT_2;
1038 #ifdef PPC_MULTILIB_ALTIVEC 1040 uint32_t RESERVED_FOR_ALIGNMENT_3[3];
1043 uint32_t RESERVED_FOR_ALIGNMENT_4[3];
1079 #ifdef PPC_MULTILIB_FPU 1113 uint64_t RESERVED_FOR_ALIGNMENT_5;
1125 _CPU_Initialize_altivec(
void);
1134 _CPU_Context_switch_altivec(
1146 _CPU_Context_restore_altivec(
1157 _CPU_Context_initialize_altivec(
1161 void _CPU_Fatal_error(
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
void _CPU_ISR_Set_level(uint32_t level)
Sets the hardware interrupt level by the level value.
Definition: cpu.c:57
IBM/Motorola PowerPC Definitions.
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
Thread register context.
Definition: cpu.h:196
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:65
void _CPU_Context_restore_fp(Context_Control_fp **fp_context_ptr)
Definition: cpu.c:207
void _CPU_Context_Initialize(Context_Control *context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
Initializes the CPU context.
Definition: epiphany-context-initialize.c:40
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
SPARC basic context.
Definition: cpu.h:242
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1202
#define RTEMS_NO_RETURN
Definition: basedefs.h:101
uint32_t _CPU_ISR_Get_level(void)
Definition: cpu.c:88
unsigned context
Definition: tlb.h:108
bool _CPU_ISR_Is_enabled(uint32_t level)
Returns true if interrupts are enabled in the specified ISR level, otherwise returns false...
Definition: cpu.h:381
void _CPU_Context_restore(Context_Control *new_context) RTEMS_NO_RETURN
Definition: cpu_asm.c:111
uintptr_t CPU_Uint32ptr
Definition: cpu.h:668
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
unsigned size
Definition: tte.h:74
void _CPU_Context_save_fp(Context_Control_fp **fp_context_ptr)
Definition: cpu.c:198
The set of registers that specifies the complete processor state.
Definition: cpu.h:635
#define CPU_MODES_INTERRUPT_MASK
Definition: cpu.h:161