RTEMS CPU Kit with SuperCore  4.11.3
cpu.h
Go to the documentation of this file.
1 
10 /*
11  * COPYRIGHT (c) 1989-2012.
12  * On-Line Applications Research Corporation (OAR).
13  *
14  * The license and distribution terms for this file may be
15  * found in the file LICENSE in this distribution or at
16  * http://www.rtems.org/license/LICENSE.
17  */
18 
19 #ifndef _RTEMS_SCORE_CPU_H
20 #define _RTEMS_SCORE_CPU_H
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
26 #include <rtems/score/types.h>
27 #include <rtems/score/v850.h>
28 
29 /* conditional compilation parameters */
30 
53 #define CPU_INLINE_ENABLE_DISPATCH TRUE
54 
82 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
83 
95 #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
96 
115 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
116 
129 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
130 
171 #define CPU_HARDWARE_FP FALSE
172 #define CPU_SOFTWARE_FP FALSE
173 
202 #define CPU_ALL_TASKS_ARE_FP FALSE
203 
219 #define CPU_IDLE_TASK_IS_FP FALSE
220 
250 #define CPU_USE_DEFERRED_FP_SWITCH TRUE
251 
277 #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
278 
290 #define CPU_STACK_GROWS_UP FALSE
291 
315 #define CPU_STRUCTURE_ALIGNMENT
316 
320 #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
321 
343 #define CPU_BIG_ENDIAN FALSE
344 
358 #define CPU_LITTLE_ENDIAN TRUE
359 
372 #define CPU_MODES_INTERRUPT_MASK 0x00000001
373 
374 #define CPU_PER_CPU_CONTROL_SIZE 0
375 
425 typedef struct {
426  uint32_t r1;
429  uint32_t r20;
430  uint32_t r21;
431  uint32_t r22;
432  uint32_t r23;
433  uint32_t r24;
434  uint32_t r25;
435  uint32_t r26;
436  uint32_t r27;
437  uint32_t r28;
438  uint32_t r29;
439  uint32_t r31;
440  uint32_t psw;
442 
450 #define _CPU_Context_Get_SP( _context ) \
451  (_context)->r3_stack_pointer
452 
457 typedef struct {
459  double some_float_register;
461 
467 typedef struct {
472  uint32_t special_interrupt_register;
474 
509 /* #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) */
510 #define CPU_CONTEXT_FP_SIZE 0
511 
522 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
523 
528 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
529 
541 #define CPU_STACK_MINIMUM_SIZE (1024*4)
542 
543 #define CPU_SIZEOF_POINTER 4
544 
553 #define CPU_ALIGNMENT 8
554 
578 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
579 
596 #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
597 
612 #define CPU_STACK_ALIGNMENT 4
613 
614 /*
615  * ISR handler macros
616  */
617 
633 #define _CPU_ISR_Disable( _isr_cookie ) \
634  do { \
635  unsigned int _psw; \
636  \
637  v850_get_psw( _psw ); \
638  __asm__ __volatile__( "di" ); \
639  _isr_cookie = _psw; \
640  } while (0)
641 
653 #define _CPU_ISR_Enable( _isr_cookie ) \
654  do { \
655  unsigned int _psw = (_isr_cookie); \
656  \
657  v850_set_psw( _psw ); \
658  } while (0)
659 
672 #define _CPU_ISR_Flash( _isr_cookie ) \
673  do { \
674  unsigned int _psw = (_isr_cookie); \
675  v850_set_psw( _psw ); \
676  __asm__ __volatile__( "di" ); \
677  } while (0)
678 
694 #define _CPU_ISR_Set_level( new_level ) \
695  do { \
696  if ( new_level ) \
697  __asm__ __volatile__( "di" ); \
698  else \
699  __asm__ __volatile__( "ei" ); \
700  } while (0)
701 
712 uint32_t _CPU_ISR_Get_level( void );
713 
714 /* end of ISR handler macros */
715 
718 /* Context handler macros */
719 
753  Context_Control *the_context,
754  uint32_t *stack_base,
755  uint32_t size,
756  uint32_t new_level,
757  void *entry_point,
758  bool is_fp,
759  void *tls_area
760 );
761 
777 #define _CPU_Context_Restart_self( _the_context ) \
778  _CPU_Context_restore( (_the_context) );
779 
780 /* XXX this should be possible to remove */
781 #if 0
782 
804 #define _CPU_Context_Fp_start( _base, _offset ) \
805  ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
806 #endif
807 
808 /* XXX this should be possible to remove */
809 #if 0
810 
828 #define _CPU_Context_Initialize_fp( _destination ) \
829  { \
830  }
831 #endif
832 
833 /* end of Context handler macros */
834 
835 /* Fatal Error manager macros */
836 
846 #define _CPU_Fatal_halt( _source, _error ) \
847  do { \
848  __asm__ __volatile__ ( "di" ); \
849  __asm__ __volatile__ ( "mov %0, r10; " : "=r" ((_error)) ); \
850  __asm__ __volatile__ ( "halt" ); \
851  } while (0)
852 
853 /* end of Fatal Error manager macros */
854 
855 /* Bitfield handler macros */
856 
869 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
870 
886 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
887 
952 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
953 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \
954  { \
955  (_output) = 0; /* do something to prevent warnings */ \
956  }
957 #endif
958 
959 /* end of Bitfield handler macros */
960 
971 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
972 
973 #define _CPU_Priority_Mask( _bit_number ) \
974  ( 1 << (_bit_number) )
975 
976 #endif
977 
991 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
992 
993 #define _CPU_Priority_bits_index( _priority ) \
994  (_priority)
995 
996 #endif
997 
998 /* end of Priority handler macros */
999 
1002 /* functions */
1003 
1014 void _CPU_Initialize(void);
1015 
1031 void _CPU_Context_switch(
1032  Context_Control *run,
1033  Context_Control *heir
1034 );
1035 
1049  Context_Control *new_context
1051 
1052 /* XXX this should be possible to remove */
1053 #if 0
1054 
1068  Context_Control_fp **fp_context_ptr
1069 );
1070 #endif
1071 
1072 /* XXX this should be possible to remove */
1073 #if 0
1074 
1088  Context_Control_fp **fp_context_ptr
1089 );
1090 #endif
1091 
1092 static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
1093 {
1094  /* TODO */
1095 }
1096 
1097 static inline void _CPU_Context_validate( uintptr_t pattern )
1098 {
1099  while (1) {
1100  /* TODO */
1101  }
1102 }
1103 
1106 /* FIXME */
1107 typedef CPU_Interrupt_frame CPU_Exception_frame;
1108 
1109 void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1110 
1139 static inline uint32_t CPU_swap_u32(
1140  uint32_t value
1141 )
1142 {
1143  unsigned int swapped;
1144 
1145  #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1)
1146  unsigned int v;
1147 
1148  v = value;
1149  __asm__ __volatile__ ("bsw %0, %1" : "=r" (v), "=&r" (swapped) );
1150  #else
1151  uint32_t byte1, byte2, byte3, byte4;
1152 
1153  byte4 = (value >> 24) & 0xff;
1154  byte3 = (value >> 16) & 0xff;
1155  byte2 = (value >> 8) & 0xff;
1156  byte1 = value & 0xff;
1157 
1158  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1159  #endif
1160  return swapped;
1161 }
1162 
1174 static inline uint16_t CPU_swap_u16( uint16_t value )
1175 {
1176  unsigned int swapped;
1177 
1178  #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1)
1179  unsigned int v;
1180 
1181  v = value;
1182  __asm__ __volatile__ ("bsh %0, %1" : "=r" (v), "=&r" (swapped) );
1183  #else
1184  swapped = ((value & 0xff) << 8) | ((value >> 8) & 0xff);
1185  #endif
1186  return swapped;
1187 }
1188 
1189 typedef uint32_t CPU_Counter_ticks;
1190 
1191 CPU_Counter_ticks _CPU_Counter_read( void );
1192 
1193 static inline CPU_Counter_ticks _CPU_Counter_difference(
1194  CPU_Counter_ticks second,
1195  CPU_Counter_ticks first
1196 )
1197 {
1198  return second - first;
1199 }
1200 
1201 #ifdef __cplusplus
1202 }
1203 #endif
1204 
1205 #endif
void _CPU_Context_validate(uintptr_t pattern)
Initializes and validates the CPU context with values derived from the pattern parameter.
Definition: cpu.h:1109
uint32_t _CPU_ISR_Get_level(void)
Return the current interrupt disable level for this task in the format used by the interrupt level po...
Definition: cpu.c:39
void _CPU_Context_restore(Context_Control *new_context)
This routine is generally used only to restart self in an efficient manner.
Definition: cpu_asm.c:112
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:92
uint32_t r3_stack_pointer
This field is the stack pointer (e.g.
Definition: cpu.h:428
void _CPU_Context_volatile_clobber(uintptr_t pattern)
Clobbers all volatile registers with values derived from the pattern parameter.
Definition: cpu.h:1104
This defines the minimal set of integer and processor state registers that must be saved during a vol...
Definition: cpu.h:248
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:26
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1461
This defines the set of integer and processor state registers that must be saved during an interrupt...
Definition: cpu.h:425
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
void _CPU_Context_restore_fp(Context_Control_fp **fp_context_ptr)
This routine restores the floating point context passed to it.
Definition: cpu.c:176
void _CPU_Context_Initialize(Context_Control *the_context, uint32_t *stack_base, uint32_t size, uint32_t new_level, void *entry_point, bool is_fp, void *tls_area)
Initialize the context to a state suitable for starting a task after a context restore operation...
Definition: cpu.c:183
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: cpu.c:96
CPU_Counter_ticks _CPU_Counter_difference(CPU_Counter_ticks second, CPU_Counter_ticks first)
Returns the difference between the second and first CPU counter value.
Definition: cpu.h:1160
This defines the complete set of floating point registers that must be saved during any context switc...
Definition: cpu.h:294
void _CPU_Context_save_fp(Context_Control_fp **fp_context_ptr)
This routine saves the floating point context passed to it.
Definition: cpu.c:167
#define CPU_swap_u16(value)
This routine swaps a 16 bir quantity.
Definition: cpu.h:1253
V850 Set up Basic CPU Dependency Settings Based on Compiler Settings.
#define RTEMS_COMPILER_NO_RETURN_ATTRIBUTE
The following macro is a compiler specific way to indicate that the method will NOT return to the cal...
Definition: basedefs.h:162
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: arm-exception-frame-print.c:46