On some CPUs, RTEMS supports a software managed interrupt stack. More...

Macros
#define	CPU_MODES_INTERRUPT_MASK 0x00000001
	The following defines the number of bits actually used in the interrupt field of the task mode. More...

#define	CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
	Amount of extra stack (above minimum stack size) required by MPCI receive server thread. More...

#define	CPU_INTERRUPT_NUMBER_OF_VECTORS 16
	This defines the number of entries in the _ISR_Vector_table managed by RTEMS. More...

#define	CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
	This defines the highest interrupt vector number for this port.

#define	CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
	This is defined if the port has a special way to report the ISR nesting level. More...

#define	_CPU_Initialize_vectors()
	Support routine to initialize the RTEMS vector table after it is allocated. More...

#define	_CPU_ISR_Disable(_level)
	Disable all interrupts for an RTEMS critical section. More...

#define	_CPU_ISR_Enable(_level)
	Enable interrupts to the previous level (returned by _CPU_ISR_Disable). More...

#define	_CPU_ISR_Flash(_level)
	This temporarily restores the interrupt to _isr_cookie before immediately disabling them again. More...

#define	_CPU_ISR_Set_level(_new_level)
	This routine and _CPU_ISR_Get_level Map the interrupt level in task mode onto the hardware that the CPU actually provides. More...

#define	CPU_MODES_INTERRUPT_MASK 0x00000001
	The following defines the number of bits actually used in the interrupt field of the task mode. More...

#define	CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
	Amount of extra stack (above minimum stack size) required by MPCI receive server thread. More...

#define	CPU_INTERRUPT_NUMBER_OF_VECTORS 32
	This defines the number of entries in the _ISR_Vector_table managed by RTEMS. More...

#define	CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
	This defines the highest interrupt vector number for this port.

#define	CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
	This is defined if the port has a special way to report the ISR nesting level. More...

#define	_CPU_Initialize_vectors()
	Support routine to initialize the RTEMS vector table after it is allocated. More...

#define	_CPU_ISR_Disable(_isr_cookie) lm32_disable_interrupts( _isr_cookie );
	Disable all interrupts for an RTEMS critical section. More...

#define	_CPU_ISR_Enable(_isr_cookie) lm32_enable_interrupts( _isr_cookie );
	Enable interrupts to the previous level (returned by _CPU_ISR_Disable). More...

#define	_CPU_ISR_Flash(_isr_cookie) lm32_flash_interrupts( _isr_cookie );
	This temporarily restores the interrupt to _isr_cookie before immediately disabling them again. More...

#define	_CPU_ISR_Set_level(new_level)
	This routine and _CPU_ISR_Get_level Map the interrupt level in task mode onto the hardware that the CPU actually provides. More...

#define	CPU_MODES_INTERRUPT_MASK 0x00000001
	The following defines the number of bits actually used in the interrupt field of the task mode. More...

#define	CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
	Amount of extra stack (above minimum stack size) required by MPCI receive server thread. More...

#define	CPU_INTERRUPT_NUMBER_OF_VECTORS 32
	This defines the number of entries in the _ISR_Vector_table managed by RTEMS. More...

#define	CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
	This defines the highest interrupt vector number for this port. More...

#define	CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
	This is defined if the port has a special way to report the ISR nesting level. More...

#define	_CPU_Initialize_vectors()
	Support routine to initialize the RTEMS vector table after it is allocated. More...

#define	_CPU_ISR_Disable(_isr_cookie)
	Disable all interrupts for an RTEMS critical section. More...

#define	_CPU_ISR_Enable(_isr_cookie)
	Enable interrupts to the previous level (returned by _CPU_ISR_Disable). More...

#define	_CPU_ISR_Flash(_isr_cookie)
	This temporarily restores the interrupt to _isr_cookie before immediately disabling them again. More...

#define	_CPU_ISR_Set_level(_new_level)
	This routine and _CPU_ISR_Get_level Map the interrupt level in task mode onto the hardware that the CPU actually provides. More...

#define	CPU_MODES_INTERRUPT_MASK 0x00000001
	The following defines the number of bits actually used in the interrupt field of the task mode. More...

#define	CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
	Amount of extra stack (above minimum stack size) required by MPCI receive server thread. More...

#define	CPU_INTERRUPT_NUMBER_OF_VECTORS 32
	This defines the number of entries in the _ISR_Vector_table managed by RTEMS. More...

#define	CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
	This defines the highest interrupt vector number for this port.

#define	CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
	This is defined if the port has a special way to report the ISR nesting level. More...

#define	_CPU_Initialize_vectors()
	Support routine to initialize the RTEMS vector table after it is allocated. More...

#define	_CPU_ISR_Disable(_isr_cookie)
	Disable all interrupts for an RTEMS critical section. More...

#define	_CPU_ISR_Enable(_isr_cookie)
	Enable interrupts to the previous level (returned by _CPU_ISR_Disable). More...

#define	_CPU_ISR_Flash(_isr_cookie)
	This temporarily restores the interrupt to _isr_cookie before immediately disabling them again. More...

#define	CPU_MODES_INTERRUPT_MASK 0x00000001
	The following defines the number of bits actually used in the interrupt field of the task mode. More...

#define	CPU_INTERRUPT_NUMBER_OF_VECTORS 32
	This defines the number of entries in the _ISR_Vector_table managed by RTEMS in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE. More...

#define	CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
	This defines the highest interrupt vector number for this port in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE. More...

#define	CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
	This is defined if the port has a special way to report the ISR nesting level. More...

#define	_CPU_Initialize_vectors()
	Support routine to initialize the RTEMS vector table after it is allocated. More...

#define	_CPU_ISR_Disable(_isr_cookie)
	Disable all interrupts for an RTEMS critical section. More...

#define	_CPU_ISR_Enable(_isr_cookie)
	Enable interrupts to the previous level (returned by _CPU_ISR_Disable). More...

#define	_CPU_ISR_Flash(_isr_cookie)
	This temporarily restores the interrupt to _isr_cookie before immediately disabling them again. More...

#define	_CPU_ISR_Set_level(new_level)
	This routine and _CPU_ISR_Get_level Map the interrupt level in task mode onto the hardware that the CPU actually provides. More...

#define	CPU_MODES_INTERRUPT_MASK 0x00000001
	The following defines the number of bits actually used in the interrupt field of the task mode. More...

#define	CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
	Amount of extra stack (above minimum stack size) required by MPCI receive server thread. More...

#define	CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
	This is defined if the port has a special way to report the ISR nesting level. More...

#define	_CPU_ISR_Disable(_isr_cookie)
	Disable all interrupts for an RTEMS critical section. More...

#define	_CPU_ISR_Enable(_isr_cookie)
	Enable interrupts to the previous level (returned by _CPU_ISR_Disable). More...

#define	_CPU_ISR_Flash(_isr_cookie)
	This temporarily restores the interrupt to _isr_cookie before immediately disabling them again. More...

#define	_CPU_ISR_Set_level(new_level)
	This routine and _CPU_ISR_Get_level Map the interrupt level in task mode onto the hardware that the CPU actually provides. More...

Functions
uint32_t	_CPU_ISR_Get_level (void)
	Return the current interrupt disable level for this task in the format used by the interrupt level portion of the task mode. More...

void	_CPU_ISR_install_raw_handler (uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
	This routine installs a "raw" interrupt handler directly into the processor's vector table. More...

void	_CPU_ISR_install_vector (uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
	This routine installs an interrupt vector. More...

void	_CPU_Install_interrupt_stack (void)
	This routine installs the hardware interrupt stack pointer. More...

Detailed Description

On some CPUs, RTEMS supports a software managed interrupt stack.

This variable is optional.

This stack is allocated by the Interrupt Manager and the switch is performed in _ISR_Handler. These variables contain pointers to the lowest and highest addresses in the chunk of memory allocated for the interrupt stack. Since it is unknown whether the stack grows up or down (in general), this give the CPU dependent code the option of picking the version it wants to use.

Note: These two variables are required if the macro CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.

Port Specific Information:

XXX document implementation including references if appropriate

It is used on CPUs on which it is difficult to generate an "uninitialized" FP context. It is filled in by _CPU_Initialize and copied into the task's FP context area during _CPU_Context_Initialize.

Port Specific Information:

XXX document implementation including references if appropriate

On some CPUs, RTEMS supports a software managed interrupt stack. This stack is allocated by the Interrupt Manager and the switch is performed in _ISR_Handler. These variables contain pointers to the lowest and highest addresses in the chunk of memory allocated for the interrupt stack. Since it is unknown whether the stack grows up or down (in general), this give the CPU dependent code the option of picking the version it wants to use.

NOTE: These two variables are required if the macro CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.

Port Specific Information:

XXX document implementation including references if appropriate

This stack is allocated by the Interrupt Manager and the switch is performed in _ISR_Handler. These variables contain pointers to the lowest and highest addresses in the chunk of memory allocated for the interrupt stack. Since it is unknown whether the stack grows up or down (in general), this give the CPU dependent code the option of picking the version it wants to use.

NOTE: These two variables are required if the macro CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.

Port Specific Information:

XXX document implementation including references if appropriate

Macro Definition Documentation

◆ _CPU_Initialize_vectors [1/5]

#define _CPU_Initialize_vectors ( )

Support routine to initialize the RTEMS vector table after it is allocated.

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_Initialize_vectors [2/5]

#define _CPU_Initialize_vectors ( )

Support routine to initialize the RTEMS vector table after it is allocated.

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_Initialize_vectors [3/5]

#define _CPU_Initialize_vectors ( )

Support routine to initialize the RTEMS vector table after it is allocated.

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_Initialize_vectors [4/5]

#define _CPU_Initialize_vectors ( )

Support routine to initialize the RTEMS vector table after it is allocated.

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_Initialize_vectors [5/5]

#define _CPU_Initialize_vectors ( )

Support routine to initialize the RTEMS vector table after it is allocated.

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_ISR_Disable [1/6]

#define _CPU_ISR_Disable ( _isr_cookie )

Value:

do { \
    unsigned int _psw; \
    \
    v850_get_psw( _psw ); \
    __asm__ __volatile__( "di" ); \
    _isr_cookie = _psw; \
  } while (0)

Disable all interrupts for an RTEMS critical section.

The previous level is returned in _isr_cookie.

Parameters

[out] _isr_cookie will contain the previous level cookie

Port Specific Information:

On the v850, we need to save the PSW and use "di" to disable interrupts.

◆ _CPU_ISR_Disable [2/6]

#define _CPU_ISR_Disable ( _isr_cookie )

Value:

do { \
    int _flg; \
    m32c_get_flg( _flg ); \
    _isr_cookie = _flg; \
    __asm__ volatile( "fclr I" ); \
  } while(0)

Disable all interrupts for an RTEMS critical section.

The previous level is returned in _isr_cookie.

Parameters

[out] _isr_cookie will contain the previous level cookie

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_ISR_Disable [3/6]

#define _CPU_ISR_Disable ( _level )

Value:

{                                     \
       __asm__ volatile ("cli %0; csync \n" : "=d" (_level) );     \
  }

Disable all interrupts for an RTEMS critical section.

The previous level is returned in _isr_cookie.

Parameters

[out] _isr_cookie will contain the previous level cookie

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_ISR_Disable [4/6]

#define _CPU_ISR_Disable ( _isr_cookie ) lm32_disable_interrupts( _isr_cookie );

Disable all interrupts for an RTEMS critical section.

The previous level is returned in _isr_cookie.

Parameters

[out] _isr_cookie will contain the previous level cookie

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_ISR_Disable [5/6]

#define _CPU_ISR_Disable ( _isr_cookie )

Value:

do { \
    (_isr_cookie) = 0; \
  } while (0)

Disable all interrupts for an RTEMS critical section.

The previous level is returned in _isr_cookie.

Parameters

[out] _isr_cookie will contain the previous level cookie

Port Specific Information:

TODO: As of 8 October 2014, this method is not implemented.

◆ _CPU_ISR_Disable [6/6]

#define _CPU_ISR_Disable ( _isr_cookie )

Value:

{ \
    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
  }

Disable all interrupts for an RTEMS critical section.

The previous level is returned in _isr_cookie.

Parameters

[out] _isr_cookie will contain the previous level cookie

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_ISR_Enable [1/6]

#define _CPU_ISR_Enable ( _isr_cookie )

Value:

do { \
    unsigned int _psw = (_isr_cookie); \
    \
    v850_set_psw( _psw ); \
  } while (0)

Enable interrupts to the previous level (returned by _CPU_ISR_Disable).

This indicates the end of an RTEMS critical section. The parameter _isr_cookie is not modified.

Parameters

[in] _isr_cookie contain the previous level cookie

Port Specific Information:

On the v850, we simply need to restore the PSW.

◆ _CPU_ISR_Enable [2/6]

#define _CPU_ISR_Enable ( _isr_cookie )

Value:

do { \
    int _flg = (int) (_isr_cookie); \
    m32c_set_flg( _flg ); \
  } while(0)

Enable interrupts to the previous level (returned by _CPU_ISR_Disable).

This indicates the end of an RTEMS critical section. The parameter _isr_cookie is not modified.

Parameters

[in] _isr_cookie contain the previous level cookie

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_ISR_Enable [3/6]

#define _CPU_ISR_Enable ( _level )

Value:

{ \
    __asm__ __volatile__ ("sti %0; csync \n" : : "d" (_level) );   \
  }

Enable interrupts to the previous level (returned by _CPU_ISR_Disable).

This indicates the end of an RTEMS critical section. The parameter _isr_cookie is not modified.

Parameters

[in] _isr_cookie contain the previous level cookie

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_ISR_Enable [4/6]

#define _CPU_ISR_Enable ( _isr_cookie ) lm32_enable_interrupts( _isr_cookie );

Enable interrupts to the previous level (returned by _CPU_ISR_Disable).

This indicates the end of an RTEMS critical section. The parameter _isr_cookie is not modified.

Parameters

[in] _isr_cookie contain the previous level cookie

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_ISR_Enable [5/6]

#define _CPU_ISR_Enable ( _isr_cookie )

Value:

do { \
    (_isr_cookie) = (_isr_cookie); \
  } while (0)

Enable interrupts to the previous level (returned by _CPU_ISR_Disable).

This indicates the end of an RTEMS critical section. The parameter _isr_cookie is not modified.

Parameters

[in] _isr_cookie contain the previous level cookie

Port Specific Information:

TODO: As of 8 October 2014, this method is not implemented.

◆ _CPU_ISR_Enable [6/6]

#define _CPU_ISR_Enable ( _isr_cookie )

Value:

{ \

}

Enable interrupts to the previous level (returned by _CPU_ISR_Disable).

This indicates the end of an RTEMS critical section. The parameter _isr_cookie is not modified.

Parameters

[in] _isr_cookie contain the previous level cookie

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_ISR_Flash [1/6]

#define _CPU_ISR_Flash ( _isr_cookie )

Value:

do { \
    unsigned int _psw = (_isr_cookie); \
    v850_set_psw( _psw ); \
    __asm__ __volatile__( "di" ); \
  } while (0)

This temporarily restores the interrupt to _isr_cookie before immediately disabling them again.

This is used to divide long RTEMS critical sections into two or more parts. The parameter _isr_cookie is not modified.

Parameters

[in] _isr_cookie contain the previous level cookie

Port Specific Information:

This saves at least one instruction over using enable/disable back to back.

◆ _CPU_ISR_Flash [2/6]

#define _CPU_ISR_Flash ( _isr_cookie )

Value:

do { \
    int _flg = (int) (_isr_cookie); \
    m32c_set_flg( _flg ); \
    __asm__ volatile( "fclr I" ); \
  } while(0)

This temporarily restores the interrupt to _isr_cookie before immediately disabling them again.

This is used to divide long RTEMS critical sections into two or more parts. The parameter _isr_cookie is not modified.

Parameters

[in] _isr_cookie contain the previous level cookie

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_ISR_Flash [3/6]

#define _CPU_ISR_Flash ( _level )

Value:

{ \
    __asm__ __volatile__ ("sti %0; csync; cli r0; csync" \
                          : : "d"(_level) : "R0" ); \
  }

This temporarily restores the interrupt to _isr_cookie before immediately disabling them again.

This is used to divide long RTEMS critical sections into two or more parts. The parameter _isr_cookie is not modified.

Parameters

[in] _isr_cookie contain the previous level cookie

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_ISR_Flash [4/6]

#define _CPU_ISR_Flash ( _isr_cookie ) lm32_flash_interrupts( _isr_cookie );

This temporarily restores the interrupt to _isr_cookie before immediately disabling them again.

This is used to divide long RTEMS critical sections into two or more parts. The parameter _isr_cookie is not modified.

Parameters

[in] _isr_cookie contain the previous level cookie

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_ISR_Flash [5/6]

#define _CPU_ISR_Flash ( _isr_cookie )

Value:

do { \
    _CPU_ISR_Enable( _isr_cookie ); \
    _CPU_ISR_Disable( _isr_cookie ); \
  } while (0)

This temporarily restores the interrupt to _isr_cookie before immediately disabling them again.

This is used to divide long RTEMS critical sections into two or more parts. The parameter _isr_cookie is not modified.

Parameters

[in] _isr_cookie contain the previous level cookie

Port Specific Information:

TODO: As of 8 October 2014, this method is not implemented.

◆ _CPU_ISR_Flash [6/6]

#define _CPU_ISR_Flash ( _isr_cookie )

Value:

{ \

}

This temporarily restores the interrupt to _isr_cookie before immediately disabling them again.

This is used to divide long RTEMS critical sections into two or more parts. The parameter _isr_cookie is not modified.

Parameters

[in] _isr_cookie contain the previous level cookie

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_ISR_Set_level [1/5]

#define _CPU_ISR_Set_level ( new_level )

Value:

do { \
    if ( new_level ) \
      __asm__ __volatile__( "di" ); \
    else \
      __asm__ __volatile__( "ei" ); \
  } while (0)

This routine and _CPU_ISR_Get_level Map the interrupt level in task mode onto the hardware that the CPU actually provides.

Currently, interrupt levels which do not map onto the CPU in a generic fashion are undefined. Someday, it would be nice if these were "mapped" by the application via a callout. For example, m68k has 8 levels 0 - 7, levels 8 - 255 would be available for bsp/application specific meaning. This could be used to manage a programmable interrupt controller via the rtems_task_mode directive.

Port Specific Information:

On the v850, level 0 is enabled. Non-zero is disabled.

◆ _CPU_ISR_Set_level [2/5]

#define _CPU_ISR_Set_level ( _new_level )

Value:

do { \
    if (_new_level) __asm__ volatile( "fclr I" ); \
    else            __asm__ volatile( "fset I" ); \
  } while(0)

This routine and _CPU_ISR_Get_level Map the interrupt level in task mode onto the hardware that the CPU actually provides.

Currently, interrupt levels which do not map onto the CPU in a generic fashion are undefined. Someday, it would be nice if these were "mapped" by the application via a callout. For example, m68k has 8 levels 0 - 7, levels 8 - 255 would be available for bsp/application specific meaning. This could be used to manage a programmable interrupt controller via the rtems_task_mode directive.

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_ISR_Set_level [3/5]

#define _CPU_ISR_Set_level ( new_level )

Value:

{ \
    _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 ); \
  }

This routine and _CPU_ISR_Get_level Map the interrupt level in task mode onto the hardware that the CPU actually provides.

Currently, interrupt levels which do not map onto the CPU in a generic fashion are undefined. Someday, it would be nice if these were "mapped" by the application via a callout. For example, m68k has 8 levels 0 - 7, levels 8 - 255 would be available for bsp/application specific meaning. This could be used to manage a programmable interrupt controller via the rtems_task_mode directive.

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_ISR_Set_level [4/5]

#define _CPU_ISR_Set_level ( _new_level )

Value:

{ \
    __asm__ __volatile__ ( "sti %0; csync" : : "d"(_new_level ? 0 : 0xffff) ); \
  }

This routine and _CPU_ISR_Get_level Map the interrupt level in task mode onto the hardware that the CPU actually provides.

Currently, interrupt levels which do not map onto the CPU in a generic fashion are undefined. Someday, it would be nice if these were "mapped" by the application via a callout. For example, m68k has 8 levels 0 - 7, levels 8 - 255 would be available for bsp/application specific meaning. This could be used to manage a programmable interrupt controller via the rtems_task_mode directive.

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_ISR_Set_level [5/5]

#define _CPU_ISR_Set_level ( new_level )

Value:

{ \

}

This routine and _CPU_ISR_Get_level Map the interrupt level in task mode onto the hardware that the CPU actually provides.

Currently, interrupt levels which do not map onto the CPU in a generic fashion are undefined. Someday, it would be nice if these were "mapped" by the application via a callout. For example, m68k has 8 levels 0 - 7, levels 8 - 255 would be available for bsp/application specific meaning. This could be used to manage a programmable interrupt controller via the rtems_task_mode directive.

Port Specific Information:

XXX document implementation including references if appropriate

◆ CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER [1/2]

#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)

This defines the highest interrupt vector number for this port.

◆ CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER [2/2]

#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)

This defines the highest interrupt vector number for this port in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE.

It must be less than CPU_INTERRUPT_NUMBER_OF_VECTORS. It may be not a compile-time constant.

It must be undefined in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to FALSE.

◆ CPU_INTERRUPT_NUMBER_OF_VECTORS [1/5]

#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32

This defines the number of entries in the _ISR_Vector_table managed by RTEMS.

Port Specific Information:

XXX document implementation including references if appropriate

◆ CPU_INTERRUPT_NUMBER_OF_VECTORS [2/5]

#define CPU_INTERRUPT_NUMBER_OF_VECTORS 16

This defines the number of entries in the _ISR_Vector_table managed by RTEMS.

Port Specific Information:

XXX document implementation including references if appropriate

◆ CPU_INTERRUPT_NUMBER_OF_VECTORS [3/5]

#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32

This defines the number of entries in the _ISR_Vector_table managed by RTEMS.

Port Specific Information:

XXX document implementation including references if appropriate

◆ CPU_INTERRUPT_NUMBER_OF_VECTORS [4/5]

#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32

This defines the number of entries in the _ISR_Vector_table managed by RTEMS.

Port Specific Information:

XXX document implementation including references if appropriate

◆ CPU_INTERRUPT_NUMBER_OF_VECTORS [5/5]

#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32

This defines the number of entries in the _ISR_Vector_table managed by RTEMS in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE.

It must be a compile-time constant.

It must be undefined in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to FALSE.

◆ CPU_MODES_INTERRUPT_MASK [1/6]

#define CPU_MODES_INTERRUPT_MASK 0x00000001

The following defines the number of bits actually used in the interrupt field of the task mode.

How those bits map to the CPU interrupt levels is defined by the routine _CPU_ISR_Set_level.

Port Specific Information:

XXX document implementation including references if appropriate

◆ CPU_MODES_INTERRUPT_MASK [2/6]

#define CPU_MODES_INTERRUPT_MASK 0x00000001

The following defines the number of bits actually used in the interrupt field of the task mode.

How those bits map to the CPU interrupt levels is defined by the routine _CPU_ISR_Set_level.

Port Specific Information:

The v850 only has a single bit in the CPU for interrupt disable/enable.

◆ CPU_MODES_INTERRUPT_MASK [3/6]

#define CPU_MODES_INTERRUPT_MASK 0x00000001

The following defines the number of bits actually used in the interrupt field of the task mode.

How those bits map to the CPU interrupt levels is defined by the routine _CPU_ISR_Set_level.

Port Specific Information:

XXX document implementation including references if appropriate

◆ CPU_MODES_INTERRUPT_MASK [4/6]

#define CPU_MODES_INTERRUPT_MASK 0x00000001

The following defines the number of bits actually used in the interrupt field of the task mode.

How those bits map to the CPU interrupt levels is defined by the routine _CPU_ISR_Set_level.

Port Specific Information:

XXX document implementation including references if appropriate

◆ CPU_MODES_INTERRUPT_MASK [5/6]

#define CPU_MODES_INTERRUPT_MASK 0x00000001

The following defines the number of bits actually used in the interrupt field of the task mode.

How those bits map to the CPU interrupt levels is defined by the routine _CPU_ISR_Set_level.

Port Specific Information:

XXX document implementation including references if appropriate

◆ CPU_MODES_INTERRUPT_MASK [6/6]

#define CPU_MODES_INTERRUPT_MASK 0x00000001

The following defines the number of bits actually used in the interrupt field of the task mode.

How those bits map to the CPU interrupt levels is defined by the routine _CPU_ISR_Set_level.

Port Specific Information:

XXX document implementation including references if appropriate

◆ CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK [1/5]

#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0

Amount of extra stack (above minimum stack size) required by MPCI receive server thread.

Remember that in a multiprocessor system this thread must exist and be able to process all directives.

Port Specific Information:

There is no reason to think the v850 needs extra MPCI receive server stack.

◆ CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK [2/5]

#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0

Amount of extra stack (above minimum stack size) required by MPCI receive server thread.

Remember that in a multiprocessor system this thread must exist and be able to process all directives.

Port Specific Information:

XXX document implementation including references if appropriate

◆ CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK [3/5]

#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0

Amount of extra stack (above minimum stack size) required by MPCI receive server thread.

Remember that in a multiprocessor system this thread must exist and be able to process all directives.

Port Specific Information:

XXX document implementation including references if appropriate

◆ CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK [4/5]

#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0

Amount of extra stack (above minimum stack size) required by MPCI receive server thread.

Remember that in a multiprocessor system this thread must exist and be able to process all directives.

Port Specific Information:

XXX document implementation including references if appropriate

◆ CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK [5/5]

#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0

Amount of extra stack (above minimum stack size) required by MPCI receive server thread.

Remember that in a multiprocessor system this thread must exist and be able to process all directives.

Port Specific Information:

XXX document implementation including references if appropriate

◆ CPU_PROVIDES_ISR_IS_IN_PROGRESS [1/6]

#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE

This is defined if the port has a special way to report the ISR nesting level.

Most ports maintain the variable _ISR_Nest_level.

◆ CPU_PROVIDES_ISR_IS_IN_PROGRESS [2/6]

#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE

This is defined if the port has a special way to report the ISR nesting level.

Most ports maintain the variable _ISR_Nest_level.

◆ CPU_PROVIDES_ISR_IS_IN_PROGRESS [3/6]

#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE

This is defined if the port has a special way to report the ISR nesting level.

Most ports maintain the variable _ISR_Nest_level.

◆ CPU_PROVIDES_ISR_IS_IN_PROGRESS [4/6]

#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE

This is defined if the port has a special way to report the ISR nesting level.

Most ports maintain the variable _ISR_Nest_level.

◆ CPU_PROVIDES_ISR_IS_IN_PROGRESS [5/6]

#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE

This is defined if the port has a special way to report the ISR nesting level.

Most ports maintain the variable _ISR_Nest_level.

◆ CPU_PROVIDES_ISR_IS_IN_PROGRESS [6/6]

#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE

This is defined if the port has a special way to report the ISR nesting level.

Most ports maintain the variable _ISR_Nest_level.

Function Documentation

◆ _CPU_Install_interrupt_stack()

void _CPU_Install_interrupt_stack ( void )

This routine installs the hardware interrupt stack pointer.

Note: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK is TRUE.

Port Specific Information:

XXX document implementation including references if appropriate

NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK is TRUE.

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_ISR_Get_level()

uint32_t _CPU_ISR_Get_level ( void )

Return the current interrupt disable level for this task in the format used by the interrupt level portion of the task mode.

Note: This routine usually must be implemented as a subroutine.

Port Specific Information:

XXX document implementation including references if appropriate

NOTE: This routine usually must be implemented as a subroutine.

Port Specific Information:

XXX document implementation including references if appropriate

NOTE: This routine usually must be implemented as a subroutine.

Port Specific Information:

TODO: As of 8 October 2014, this method is not implemented.

Note: This routine usually must be implemented as a subroutine.

Port Specific Information:

This method is implemented in C on the v850.

NOTE: This routine usually must be implemented as a subroutine.

Port Specific Information:

XXX document implementation including references if appropriate

NOTE: This routine usually must be implemented as a subroutine.

Port Specific Information:

TODO: As of 8 October 2014, this method is not implemented.

Note: This routine usually must be implemented as a subroutine.

Port Specific Information:

This method is implemented in C on the v850.

◆ _CPU_ISR_install_raw_handler()

void _CPU_ISR_install_raw_handler	(	uint32_t	vector,
		proc_ptr	new_handler,
		proc_ptr *	old_handler
	)

This routine installs a "raw" interrupt handler directly into the processor's vector table.

Parameters

[in]	vector	is the vector number
[in]	new_handler	is the raw ISR handler to install
[in]	old_handler	is the previously installed ISR Handler

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_ISR_install_vector()

void _CPU_ISR_install_vector	(	uint32_t	vector,
		proc_ptr	new_handler,
		proc_ptr *	old_handler
	)

This routine installs an interrupt vector.

Parameters

[in]	vector	is the vector number
[in]	new_handler	is the RTEMS ISR handler to install
[in]	old_handler	is the previously installed ISR Handler

Port Specific Information:

XXX document implementation including references if appropriate

Macros

Functions

Detailed Description

Macro Definition Documentation

◆ _CPU_Initialize_vectors [1/5]

◆ _CPU_Initialize_vectors [2/5]

◆ _CPU_Initialize_vectors [3/5]

◆ _CPU_Initialize_vectors [4/5]

◆ _CPU_Initialize_vectors [5/5]

◆ _CPU_ISR_Disable [1/6]

◆ _CPU_ISR_Disable [2/6]

◆ _CPU_ISR_Disable [3/6]

◆ _CPU_ISR_Disable [4/6]

◆ _CPU_ISR_Disable [5/6]

◆ _CPU_ISR_Disable [6/6]

◆ _CPU_ISR_Enable [1/6]

◆ _CPU_ISR_Enable [2/6]

◆ _CPU_ISR_Enable [3/6]

◆ _CPU_ISR_Enable [4/6]

◆ _CPU_ISR_Enable [5/6]

◆ _CPU_ISR_Enable [6/6]

◆ _CPU_ISR_Flash [1/6]

◆ _CPU_ISR_Flash [2/6]

◆ _CPU_ISR_Flash [3/6]

◆ _CPU_ISR_Flash [4/6]

◆ _CPU_ISR_Flash [5/6]

◆ _CPU_ISR_Flash [6/6]

◆ _CPU_ISR_Set_level [1/5]

◆ _CPU_ISR_Set_level [2/5]

◆ _CPU_ISR_Set_level [3/5]

◆ _CPU_ISR_Set_level [4/5]

◆ _CPU_ISR_Set_level [5/5]

◆ CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER [1/2]

◆ CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER [2/2]

◆ CPU_INTERRUPT_NUMBER_OF_VECTORS [1/5]

◆ CPU_INTERRUPT_NUMBER_OF_VECTORS [2/5]

◆ CPU_INTERRUPT_NUMBER_OF_VECTORS [3/5]

◆ CPU_INTERRUPT_NUMBER_OF_VECTORS [4/5]

◆ CPU_INTERRUPT_NUMBER_OF_VECTORS [5/5]

◆ CPU_MODES_INTERRUPT_MASK [1/6]

◆ CPU_MODES_INTERRUPT_MASK [2/6]

◆ CPU_MODES_INTERRUPT_MASK [3/6]

◆ CPU_MODES_INTERRUPT_MASK [4/6]

◆ CPU_MODES_INTERRUPT_MASK [5/6]

◆ CPU_MODES_INTERRUPT_MASK [6/6]

◆ CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK [1/5]

◆ CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK [2/5]

◆ CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK [3/5]

◆ CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK [4/5]

◆ CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK [5/5]

◆ CPU_PROVIDES_ISR_IS_IN_PROGRESS [1/6]

◆ CPU_PROVIDES_ISR_IS_IN_PROGRESS [2/6]

◆ CPU_PROVIDES_ISR_IS_IN_PROGRESS [3/6]

◆ CPU_PROVIDES_ISR_IS_IN_PROGRESS [4/6]

◆ CPU_PROVIDES_ISR_IS_IN_PROGRESS [5/6]

◆ CPU_PROVIDES_ISR_IS_IN_PROGRESS [6/6]

Function Documentation

◆ _CPU_Install_interrupt_stack()

◆ _CPU_ISR_Get_level()

◆ _CPU_ISR_install_raw_handler()

◆ _CPU_ISR_install_vector()