RTEMS  5.0.0
core_cm7.h
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1 /**************************************************************************/
7 /* Copyright (c) 2009 - 2015 ARM LIMITED
8 
9  All rights reserved.
10  Redistribution and use in source and binary forms, with or without
11  modification, are permitted provided that the following conditions are met:
12  - Redistributions of source code must retain the above copyright
13  notice, this list of conditions and the following disclaimer.
14  - Redistributions in binary form must reproduce the above copyright
15  notice, this list of conditions and the following disclaimer in the
16  documentation and/or other materials provided with the distribution.
17  - Neither the name of ARM nor the names of its contributors may be used
18  to endorse or promote products derived from this software without
19  specific prior written permission.
20  *
21  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31  POSSIBILITY OF SUCH DAMAGE.
32  ---------------------------------------------------------------------------*/
33 
34 
35 #if defined ( __ICCARM__ )
36  #pragma system_include /* treat file as system include file for MISRA check */
37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
38  #pragma clang system_header /* treat file as system include file */
39 #endif
40 
41 #ifndef __CORE_CM7_H_GENERIC
42 #define __CORE_CM7_H_GENERIC
43 
44 #include <stdint.h>
45 
46 #ifdef __cplusplus
47  extern "C" {
48 #endif
49 
65 /*******************************************************************************
66  * CMSIS definitions
67  ******************************************************************************/
73 /* CMSIS CM7 definitions */
74 #define __CM7_CMSIS_VERSION_MAIN (0x04U)
75 #define __CM7_CMSIS_VERSION_SUB (0x1EU)
76 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
77  __CM7_CMSIS_VERSION_SUB )
79 #define __CORTEX_M (0x07U)
82 #if defined ( __CC_ARM )
83  #define __ASM __asm
84  #define __INLINE __inline
85  #define __STATIC_INLINE static __inline
86 
87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
88  #define __ASM __asm
89  #define __INLINE __inline
90  #define __STATIC_INLINE static __inline
91 
92 #elif defined ( __GNUC__ )
93  #define __ASM __asm
94  #define __INLINE inline
95  #define __STATIC_INLINE static inline
96 
97 #elif defined ( __ICCARM__ )
98  #define __ASM __asm
99  #define __INLINE inline
100  #define __STATIC_INLINE static inline
101 
102 #elif defined ( __TMS470__ )
103  #define __ASM __asm
104  #define __STATIC_INLINE static inline
105 
106 #elif defined ( __TASKING__ )
107  #define __ASM __asm
108  #define __INLINE inline
109  #define __STATIC_INLINE static inline
110 
111 #elif defined ( __CSMC__ )
112  #define __packed
113  #define __ASM _asm
114  #define __INLINE inline
115  #define __STATIC_INLINE static inline
116 
117 #else
118  #error Unknown compiler
119 #endif
120 
124 #if defined ( __CC_ARM )
125  #if defined __TARGET_FPU_VFP
126  #if (__FPU_PRESENT == 1U)
127  #define __FPU_USED 1U
128  #else
129  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130  #define __FPU_USED 0U
131  #endif
132  #else
133  #define __FPU_USED 0U
134  #endif
135 
136 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
137  #if defined __ARM_PCS_VFP
138  #if (__FPU_PRESENT == 1)
139  #define __FPU_USED 1U
140  #else
141  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
142  #define __FPU_USED 0U
143  #endif
144  #else
145  #define __FPU_USED 0U
146  #endif
147 
148 #elif defined ( __GNUC__ )
149  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
150  #if (__FPU_PRESENT == 1U)
151  #define __FPU_USED 1U
152  #else
153  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154  #define __FPU_USED 0U
155  #endif
156  #else
157  #define __FPU_USED 0U
158  #endif
159 
160 #elif defined ( __ICCARM__ )
161  #if defined __ARMVFP__
162  #if (__FPU_PRESENT == 1U)
163  #define __FPU_USED 1U
164  #else
165  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
166  #define __FPU_USED 0U
167  #endif
168  #else
169  #define __FPU_USED 0U
170  #endif
171 
172 #elif defined ( __TMS470__ )
173  #if defined __TI_VFP_SUPPORT__
174  #if (__FPU_PRESENT == 1U)
175  #define __FPU_USED 1U
176  #else
177  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
178  #define __FPU_USED 0U
179  #endif
180  #else
181  #define __FPU_USED 0U
182  #endif
183 
184 #elif defined ( __TASKING__ )
185  #if defined __FPU_VFP__
186  #if (__FPU_PRESENT == 1U)
187  #define __FPU_USED 1U
188  #else
189  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
190  #define __FPU_USED 0U
191  #endif
192  #else
193  #define __FPU_USED 0U
194  #endif
195 
196 #elif defined ( __CSMC__ )
197  #if ( __CSMC__ & 0x400U)
198  #if (__FPU_PRESENT == 1U)
199  #define __FPU_USED 1U
200  #else
201  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
202  #define __FPU_USED 0U
203  #endif
204  #else
205  #define __FPU_USED 0U
206  #endif
207 
208 #endif
209 
210 #include "core_cmInstr.h" /* Core Instruction Access */
211 #include "core_cmFunc.h" /* Core Function Access */
212 #include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
213 
214 #ifdef __cplusplus
215 }
216 #endif
217 
218 #endif /* __CORE_CM7_H_GENERIC */
219 
220 #ifndef __CMSIS_GENERIC
221 
222 #ifndef __CORE_CM7_H_DEPENDANT
223 #define __CORE_CM7_H_DEPENDANT
224 
225 #ifdef __cplusplus
226  extern "C" {
227 #endif
228 
229 /* check device defines and use defaults */
230 #if defined __CHECK_DEVICE_DEFINES
231  #ifndef __CM7_REV
232  #define __CM7_REV 0x0000U
233  #warning "__CM7_REV not defined in device header file; using default!"
234  #endif
235 
236  #ifndef __FPU_PRESENT
237  #define __FPU_PRESENT 0U
238  #warning "__FPU_PRESENT not defined in device header file; using default!"
239  #endif
240 
241  #ifndef __MPU_PRESENT
242  #define __MPU_PRESENT 0U
243  #warning "__MPU_PRESENT not defined in device header file; using default!"
244  #endif
245 
246  #ifndef __ICACHE_PRESENT
247  #define __ICACHE_PRESENT 0U
248  #warning "__ICACHE_PRESENT not defined in device header file; using default!"
249  #endif
250 
251  #ifndef __DCACHE_PRESENT
252  #define __DCACHE_PRESENT 0U
253  #warning "__DCACHE_PRESENT not defined in device header file; using default!"
254  #endif
255 
256  #ifndef __DTCM_PRESENT
257  #define __DTCM_PRESENT 0U
258  #warning "__DTCM_PRESENT not defined in device header file; using default!"
259  #endif
260 
261  #ifndef __NVIC_PRIO_BITS
262  #define __NVIC_PRIO_BITS 3U
263  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
264  #endif
265 
266  #ifndef __Vendor_SysTickConfig
267  #define __Vendor_SysTickConfig 0U
268  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
269  #endif
270 #endif
271 
272 /* IO definitions (access restrictions to peripheral registers) */
281 #ifdef __cplusplus
282  #define __I volatile
283 #else
284  #define __I volatile const
285 #endif
286 #define __O volatile
287 #define __IO volatile
289 /* following defines should be used for structure members */
290 #define __IM volatile const
291 #define __OM volatile
292 #define __IOM volatile
294 
298 /*******************************************************************************
299  * Register Abstraction
300  Core Register contain:
301  - Core Register
302  - Core NVIC Register
303  - Core SCB Register
304  - Core SysTick Register
305  - Core Debug Register
306  - Core MPU Register
307  - Core FPU Register
308  ******************************************************************************/
309 
325 typedef union
326 {
327  struct
328  {
329  uint32_t _reserved0:16;
330  uint32_t GE:4;
331  uint32_t _reserved1:7;
332  uint32_t Q:1;
333  uint32_t V:1;
334  uint32_t C:1;
335  uint32_t Z:1;
336  uint32_t N:1;
337  } b;
338  uint32_t w;
339 } APSR_Type;
340 
341 /* APSR Register Definitions */
342 #define APSR_N_Pos 31U
343 #define APSR_N_Msk (1UL << APSR_N_Pos)
345 #define APSR_Z_Pos 30U
346 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
348 #define APSR_C_Pos 29U
349 #define APSR_C_Msk (1UL << APSR_C_Pos)
351 #define APSR_V_Pos 28U
352 #define APSR_V_Msk (1UL << APSR_V_Pos)
354 #define APSR_Q_Pos 27U
355 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
357 #define APSR_GE_Pos 16U
358 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
364 typedef union
365 {
366  struct
367  {
368  uint32_t ISR:9;
369  uint32_t _reserved0:23;
370  } b;
371  uint32_t w;
372 } IPSR_Type;
373 
374 /* IPSR Register Definitions */
375 #define IPSR_ISR_Pos 0U
376 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
382 typedef union
383 {
384  struct
385  {
386  uint32_t ISR:9;
387  uint32_t _reserved0:7;
388  uint32_t GE:4;
389  uint32_t _reserved1:4;
390  uint32_t T:1;
391  uint32_t IT:2;
392  uint32_t Q:1;
393  uint32_t V:1;
394  uint32_t C:1;
395  uint32_t Z:1;
396  uint32_t N:1;
397  } b;
398  uint32_t w;
399 } xPSR_Type;
400 
401 /* xPSR Register Definitions */
402 #define xPSR_N_Pos 31U
403 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
405 #define xPSR_Z_Pos 30U
406 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
408 #define xPSR_C_Pos 29U
409 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
411 #define xPSR_V_Pos 28U
412 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
414 #define xPSR_Q_Pos 27U
415 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
417 #define xPSR_IT_Pos 25U
418 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos)
420 #define xPSR_T_Pos 24U
421 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
423 #define xPSR_GE_Pos 16U
424 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
426 #define xPSR_ISR_Pos 0U
427 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
433 typedef union
434 {
435  struct
436  {
437  uint32_t nPRIV:1;
438  uint32_t SPSEL:1;
439  uint32_t FPCA:1;
440  uint32_t _reserved0:29;
441  } b;
442  uint32_t w;
443 } CONTROL_Type;
444 
445 /* CONTROL Register Definitions */
446 #define CONTROL_FPCA_Pos 2U
447 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
449 #define CONTROL_SPSEL_Pos 1U
450 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
452 #define CONTROL_nPRIV_Pos 0U
453 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
455 
468 typedef struct
469 {
470  __IOM uint32_t ISER[8U];
471  uint32_t RESERVED0[24U];
472  __IOM uint32_t ICER[8U];
473  uint32_t RSERVED1[24U];
474  __IOM uint32_t ISPR[8U];
475  uint32_t RESERVED2[24U];
476  __IOM uint32_t ICPR[8U];
477  uint32_t RESERVED3[24U];
478  __IOM uint32_t IABR[8U];
479  uint32_t RESERVED4[56U];
480  __IOM uint8_t IP[240U];
481  uint32_t RESERVED5[644U];
482  __OM uint32_t STIR;
483 } NVIC_Type;
484 
485 /* Software Triggered Interrupt Register Definitions */
486 #define NVIC_STIR_INTID_Pos 0U
487 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
489 
502 typedef struct
503 {
504  __IM uint32_t CPUID;
505  __IOM uint32_t ICSR;
506  __IOM uint32_t VTOR;
507  __IOM uint32_t AIRCR;
508  __IOM uint32_t SCR;
509  __IOM uint32_t CCR;
510  __IOM uint8_t SHPR[12U];
511  __IOM uint32_t SHCSR;
512  __IOM uint32_t CFSR;
513  __IOM uint32_t HFSR;
514  __IOM uint32_t DFSR;
515  __IOM uint32_t MMFAR;
516  __IOM uint32_t BFAR;
517  __IOM uint32_t AFSR;
518  __IM uint32_t ID_PFR[2U];
519  __IM uint32_t ID_DFR;
520  __IM uint32_t ID_AFR;
521  __IM uint32_t ID_MFR[4U];
522  __IM uint32_t ID_ISAR[5U];
523  uint32_t RESERVED0[1U];
524  __IM uint32_t CLIDR;
525  __IM uint32_t CTR;
526  __IM uint32_t CCSIDR;
527  __IOM uint32_t CSSELR;
528  __IOM uint32_t CPACR;
529  uint32_t RESERVED3[93U];
530  __OM uint32_t STIR;
531  uint32_t RESERVED4[15U];
532  __IM uint32_t MVFR0;
533  __IM uint32_t MVFR1;
534  __IM uint32_t MVFR2;
535  uint32_t RESERVED5[1U];
536  __OM uint32_t ICIALLU;
537  uint32_t RESERVED6[1U];
538  __OM uint32_t ICIMVAU;
539  __OM uint32_t DCIMVAC;
540  __OM uint32_t DCISW;
541  __OM uint32_t DCCMVAU;
542  __OM uint32_t DCCMVAC;
543  __OM uint32_t DCCSW;
544  __OM uint32_t DCCIMVAC;
545  __OM uint32_t DCCISW;
546  uint32_t RESERVED7[6U];
547  __IOM uint32_t ITCMCR;
548  __IOM uint32_t DTCMCR;
549  __IOM uint32_t AHBPCR;
550  __IOM uint32_t CACR;
551  __IOM uint32_t AHBSCR;
552  uint32_t RESERVED8[1U];
553  __IOM uint32_t ABFSR;
554 } SCB_Type;
555 
556 /* SCB CPUID Register Definitions */
557 #define SCB_CPUID_IMPLEMENTER_Pos 24U
558 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
560 #define SCB_CPUID_VARIANT_Pos 20U
561 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
563 #define SCB_CPUID_ARCHITECTURE_Pos 16U
564 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
566 #define SCB_CPUID_PARTNO_Pos 4U
567 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
569 #define SCB_CPUID_REVISION_Pos 0U
570 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
572 /* SCB Interrupt Control State Register Definitions */
573 #define SCB_ICSR_NMIPENDSET_Pos 31U
574 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
576 #define SCB_ICSR_PENDSVSET_Pos 28U
577 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
579 #define SCB_ICSR_PENDSVCLR_Pos 27U
580 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
582 #define SCB_ICSR_PENDSTSET_Pos 26U
583 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
585 #define SCB_ICSR_PENDSTCLR_Pos 25U
586 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
588 #define SCB_ICSR_ISRPREEMPT_Pos 23U
589 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
591 #define SCB_ICSR_ISRPENDING_Pos 22U
592 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
594 #define SCB_ICSR_VECTPENDING_Pos 12U
595 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
597 #define SCB_ICSR_RETTOBASE_Pos 11U
598 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
600 #define SCB_ICSR_VECTACTIVE_Pos 0U
601 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
603 /* SCB Vector Table Offset Register Definitions */
604 #define SCB_VTOR_TBLOFF_Pos 7U
605 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
607 /* SCB Application Interrupt and Reset Control Register Definitions */
608 #define SCB_AIRCR_VECTKEY_Pos 16U
609 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
611 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
612 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
614 #define SCB_AIRCR_ENDIANESS_Pos 15U
615 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
617 #define SCB_AIRCR_PRIGROUP_Pos 8U
618 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
620 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
621 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
623 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
624 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
626 #define SCB_AIRCR_VECTRESET_Pos 0U
627 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
629 /* SCB System Control Register Definitions */
630 #define SCB_SCR_SEVONPEND_Pos 4U
631 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
633 #define SCB_SCR_SLEEPDEEP_Pos 2U
634 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
636 #define SCB_SCR_SLEEPONEXIT_Pos 1U
637 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
639 /* SCB Configuration Control Register Definitions */
640 #define SCB_CCR_BP_Pos 18U
641 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
643 #define SCB_CCR_IC_Pos 17U
644 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
646 #define SCB_CCR_DC_Pos 16U
647 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
649 #define SCB_CCR_STKALIGN_Pos 9U
650 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
652 #define SCB_CCR_BFHFNMIGN_Pos 8U
653 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
655 #define SCB_CCR_DIV_0_TRP_Pos 4U
656 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
658 #define SCB_CCR_UNALIGN_TRP_Pos 3U
659 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
661 #define SCB_CCR_USERSETMPEND_Pos 1U
662 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
664 #define SCB_CCR_NONBASETHRDENA_Pos 0U
665 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
667 /* SCB System Handler Control and State Register Definitions */
668 #define SCB_SHCSR_USGFAULTENA_Pos 18U
669 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
671 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
672 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
674 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
675 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
677 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
678 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
680 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
681 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
683 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
684 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
686 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
687 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
689 #define SCB_SHCSR_SYSTICKACT_Pos 11U
690 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
692 #define SCB_SHCSR_PENDSVACT_Pos 10U
693 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
695 #define SCB_SHCSR_MONITORACT_Pos 8U
696 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
698 #define SCB_SHCSR_SVCALLACT_Pos 7U
699 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
701 #define SCB_SHCSR_USGFAULTACT_Pos 3U
702 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
704 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
705 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
707 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
708 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
710 /* SCB Configurable Fault Status Register Definitions */
711 #define SCB_CFSR_USGFAULTSR_Pos 16U
712 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
714 #define SCB_CFSR_BUSFAULTSR_Pos 8U
715 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
717 #define SCB_CFSR_MEMFAULTSR_Pos 0U
718 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
720 /* SCB Hard Fault Status Register Definitions */
721 #define SCB_HFSR_DEBUGEVT_Pos 31U
722 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
724 #define SCB_HFSR_FORCED_Pos 30U
725 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
727 #define SCB_HFSR_VECTTBL_Pos 1U
728 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
730 /* SCB Debug Fault Status Register Definitions */
731 #define SCB_DFSR_EXTERNAL_Pos 4U
732 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
734 #define SCB_DFSR_VCATCH_Pos 3U
735 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
737 #define SCB_DFSR_DWTTRAP_Pos 2U
738 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
740 #define SCB_DFSR_BKPT_Pos 1U
741 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
743 #define SCB_DFSR_HALTED_Pos 0U
744 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
746 /* SCB Cache Level ID Register Definitions */
747 #define SCB_CLIDR_LOUU_Pos 27U
748 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
750 #define SCB_CLIDR_LOC_Pos 24U
751 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
753 /* SCB Cache Type Register Definitions */
754 #define SCB_CTR_FORMAT_Pos 29U
755 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
757 #define SCB_CTR_CWG_Pos 24U
758 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
760 #define SCB_CTR_ERG_Pos 20U
761 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
763 #define SCB_CTR_DMINLINE_Pos 16U
764 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
766 #define SCB_CTR_IMINLINE_Pos 0U
767 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
769 /* SCB Cache Size ID Register Definitions */
770 #define SCB_CCSIDR_WT_Pos 31U
771 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
773 #define SCB_CCSIDR_WB_Pos 30U
774 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
776 #define SCB_CCSIDR_RA_Pos 29U
777 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
779 #define SCB_CCSIDR_WA_Pos 28U
780 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
782 #define SCB_CCSIDR_NUMSETS_Pos 13U
783 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
785 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
786 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
788 #define SCB_CCSIDR_LINESIZE_Pos 0U
789 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
791 /* SCB Cache Size Selection Register Definitions */
792 #define SCB_CSSELR_LEVEL_Pos 1U
793 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
795 #define SCB_CSSELR_IND_Pos 0U
796 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
798 /* SCB Software Triggered Interrupt Register Definitions */
799 #define SCB_STIR_INTID_Pos 0U
800 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
802 /* SCB D-Cache Invalidate by Set-way Register Definitions */
803 #define SCB_DCISW_WAY_Pos 30U
804 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
806 #define SCB_DCISW_SET_Pos 5U
807 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
809 /* SCB D-Cache Clean by Set-way Register Definitions */
810 #define SCB_DCCSW_WAY_Pos 30U
811 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
813 #define SCB_DCCSW_SET_Pos 5U
814 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
816 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
817 #define SCB_DCCISW_WAY_Pos 30U
818 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
820 #define SCB_DCCISW_SET_Pos 5U
821 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
823 /* Instruction Tightly-Coupled Memory Control Register Definitions */
824 #define SCB_ITCMCR_SZ_Pos 3U
825 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)
827 #define SCB_ITCMCR_RETEN_Pos 2U
828 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)
830 #define SCB_ITCMCR_RMW_Pos 1U
831 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)
833 #define SCB_ITCMCR_EN_Pos 0U
834 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/)
836 /* Data Tightly-Coupled Memory Control Register Definitions */
837 #define SCB_DTCMCR_SZ_Pos 3U
838 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)
840 #define SCB_DTCMCR_RETEN_Pos 2U
841 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)
843 #define SCB_DTCMCR_RMW_Pos 1U
844 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)
846 #define SCB_DTCMCR_EN_Pos 0U
847 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/)
849 /* AHBP Control Register Definitions */
850 #define SCB_AHBPCR_SZ_Pos 1U
851 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)
853 #define SCB_AHBPCR_EN_Pos 0U
854 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/)
856 /* L1 Cache Control Register Definitions */
857 #define SCB_CACR_FORCEWT_Pos 2U
858 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)
860 #define SCB_CACR_ECCEN_Pos 1U
861 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)
863 #define SCB_CACR_SIWT_Pos 0U
864 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/)
866 /* AHBS Control Register Definitions */
867 #define SCB_AHBSCR_INITCOUNT_Pos 11U
868 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
870 #define SCB_AHBSCR_TPRI_Pos 2U
871 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
873 #define SCB_AHBSCR_CTL_Pos 0U
874 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
876 /* Auxiliary Bus Fault Status Register Definitions */
877 #define SCB_ABFSR_AXIMTYPE_Pos 8U
878 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)
880 #define SCB_ABFSR_EPPB_Pos 4U
881 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)
883 #define SCB_ABFSR_AXIM_Pos 3U
884 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)
886 #define SCB_ABFSR_AHBP_Pos 2U
887 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)
889 #define SCB_ABFSR_DTCM_Pos 1U
890 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)
892 #define SCB_ABFSR_ITCM_Pos 0U
893 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
895 
908 typedef struct
909 {
910  uint32_t RESERVED0[1U];
911  __IM uint32_t ICTR;
912  __IOM uint32_t ACTLR;
913 } SCnSCB_Type;
914 
915 /* Interrupt Controller Type Register Definitions */
916 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
917 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
919 /* Auxiliary Control Register Definitions */
920 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U
921 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)
923 #define SCnSCB_ACTLR_DISRAMODE_Pos 11U
924 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)
926 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U
927 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)
929 #define SCnSCB_ACTLR_DISFOLD_Pos 2U
930 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
932 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U
933 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)
935 
948 typedef struct
949 {
950  __IOM uint32_t CTRL;
951  __IOM uint32_t LOAD;
952  __IOM uint32_t VAL;
953  __IM uint32_t CALIB;
954 } SysTick_Type;
955 
956 /* SysTick Control / Status Register Definitions */
957 #define SysTick_CTRL_COUNTFLAG_Pos 16U
958 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
960 #define SysTick_CTRL_CLKSOURCE_Pos 2U
961 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
963 #define SysTick_CTRL_TICKINT_Pos 1U
964 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
966 #define SysTick_CTRL_ENABLE_Pos 0U
967 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
969 /* SysTick Reload Register Definitions */
970 #define SysTick_LOAD_RELOAD_Pos 0U
971 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
973 /* SysTick Current Register Definitions */
974 #define SysTick_VAL_CURRENT_Pos 0U
975 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
977 /* SysTick Calibration Register Definitions */
978 #define SysTick_CALIB_NOREF_Pos 31U
979 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
981 #define SysTick_CALIB_SKEW_Pos 30U
982 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
984 #define SysTick_CALIB_TENMS_Pos 0U
985 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
987 
1000 typedef struct
1001 {
1002  __OM union
1003  {
1004  __OM uint8_t u8;
1005  __OM uint16_t u16;
1006  __OM uint32_t u32;
1007  } PORT [32U];
1008  uint32_t RESERVED0[864U];
1009  __IOM uint32_t TER;
1010  uint32_t RESERVED1[15U];
1011  __IOM uint32_t TPR;
1012  uint32_t RESERVED2[15U];
1013  __IOM uint32_t TCR;
1014  uint32_t RESERVED3[29U];
1015  __OM uint32_t IWR;
1016  __IM uint32_t IRR;
1017  __IOM uint32_t IMCR;
1018  uint32_t RESERVED4[43U];
1019  __OM uint32_t LAR;
1020  __IM uint32_t LSR;
1021  uint32_t RESERVED5[6U];
1022  __IM uint32_t PID4;
1023  __IM uint32_t PID5;
1024  __IM uint32_t PID6;
1025  __IM uint32_t PID7;
1026  __IM uint32_t PID0;
1027  __IM uint32_t PID1;
1028  __IM uint32_t PID2;
1029  __IM uint32_t PID3;
1030  __IM uint32_t CID0;
1031  __IM uint32_t CID1;
1032  __IM uint32_t CID2;
1033  __IM uint32_t CID3;
1034 } ITM_Type;
1035 
1036 /* ITM Trace Privilege Register Definitions */
1037 #define ITM_TPR_PRIVMASK_Pos 0U
1038 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
1040 /* ITM Trace Control Register Definitions */
1041 #define ITM_TCR_BUSY_Pos 23U
1042 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
1044 #define ITM_TCR_TraceBusID_Pos 16U
1045 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
1047 #define ITM_TCR_GTSFREQ_Pos 10U
1048 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
1050 #define ITM_TCR_TSPrescale_Pos 8U
1051 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
1053 #define ITM_TCR_SWOENA_Pos 4U
1054 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
1056 #define ITM_TCR_DWTENA_Pos 3U
1057 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
1059 #define ITM_TCR_SYNCENA_Pos 2U
1060 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
1062 #define ITM_TCR_TSENA_Pos 1U
1063 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
1065 #define ITM_TCR_ITMENA_Pos 0U
1066 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
1068 /* ITM Integration Write Register Definitions */
1069 #define ITM_IWR_ATVALIDM_Pos 0U
1070 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
1072 /* ITM Integration Read Register Definitions */
1073 #define ITM_IRR_ATREADYM_Pos 0U
1074 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
1076 /* ITM Integration Mode Control Register Definitions */
1077 #define ITM_IMCR_INTEGRATION_Pos 0U
1078 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
1080 /* ITM Lock Status Register Definitions */
1081 #define ITM_LSR_ByteAcc_Pos 2U
1082 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
1084 #define ITM_LSR_Access_Pos 1U
1085 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
1087 #define ITM_LSR_Present_Pos 0U
1088 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
1090  /* end of group CMSIS_ITM */
1091 
1092 
1103 typedef struct
1104 {
1105  __IOM uint32_t CTRL;
1106  __IOM uint32_t CYCCNT;
1107  __IOM uint32_t CPICNT;
1108  __IOM uint32_t EXCCNT;
1109  __IOM uint32_t SLEEPCNT;
1110  __IOM uint32_t LSUCNT;
1111  __IOM uint32_t FOLDCNT;
1112  __IM uint32_t PCSR;
1113  __IOM uint32_t COMP0;
1114  __IOM uint32_t MASK0;
1115  __IOM uint32_t FUNCTION0;
1116  uint32_t RESERVED0[1U];
1117  __IOM uint32_t COMP1;
1118  __IOM uint32_t MASK1;
1119  __IOM uint32_t FUNCTION1;
1120  uint32_t RESERVED1[1U];
1121  __IOM uint32_t COMP2;
1122  __IOM uint32_t MASK2;
1123  __IOM uint32_t FUNCTION2;
1124  uint32_t RESERVED2[1U];
1125  __IOM uint32_t COMP3;
1126  __IOM uint32_t MASK3;
1127  __IOM uint32_t FUNCTION3;
1128  uint32_t RESERVED3[981U];
1129  __OM uint32_t LAR;
1130  __IM uint32_t LSR;
1131 } DWT_Type;
1132 
1133 /* DWT Control Register Definitions */
1134 #define DWT_CTRL_NUMCOMP_Pos 28U
1135 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
1137 #define DWT_CTRL_NOTRCPKT_Pos 27U
1138 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
1140 #define DWT_CTRL_NOEXTTRIG_Pos 26U
1141 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
1143 #define DWT_CTRL_NOCYCCNT_Pos 25U
1144 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
1146 #define DWT_CTRL_NOPRFCNT_Pos 24U
1147 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
1149 #define DWT_CTRL_CYCEVTENA_Pos 22U
1150 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
1152 #define DWT_CTRL_FOLDEVTENA_Pos 21U
1153 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
1155 #define DWT_CTRL_LSUEVTENA_Pos 20U
1156 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
1158 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
1159 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
1161 #define DWT_CTRL_EXCEVTENA_Pos 18U
1162 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
1164 #define DWT_CTRL_CPIEVTENA_Pos 17U
1165 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
1167 #define DWT_CTRL_EXCTRCENA_Pos 16U
1168 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
1170 #define DWT_CTRL_PCSAMPLENA_Pos 12U
1171 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
1173 #define DWT_CTRL_SYNCTAP_Pos 10U
1174 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
1176 #define DWT_CTRL_CYCTAP_Pos 9U
1177 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
1179 #define DWT_CTRL_POSTINIT_Pos 5U
1180 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
1182 #define DWT_CTRL_POSTPRESET_Pos 1U
1183 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
1185 #define DWT_CTRL_CYCCNTENA_Pos 0U
1186 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
1188 /* DWT CPI Count Register Definitions */
1189 #define DWT_CPICNT_CPICNT_Pos 0U
1190 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
1192 /* DWT Exception Overhead Count Register Definitions */
1193 #define DWT_EXCCNT_EXCCNT_Pos 0U
1194 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
1196 /* DWT Sleep Count Register Definitions */
1197 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
1198 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
1200 /* DWT LSU Count Register Definitions */
1201 #define DWT_LSUCNT_LSUCNT_Pos 0U
1202 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
1204 /* DWT Folded-instruction Count Register Definitions */
1205 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
1206 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
1208 /* DWT Comparator Mask Register Definitions */
1209 #define DWT_MASK_MASK_Pos 0U
1210 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
1212 /* DWT Comparator Function Register Definitions */
1213 #define DWT_FUNCTION_MATCHED_Pos 24U
1214 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1216 #define DWT_FUNCTION_DATAVADDR1_Pos 16U
1217 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
1219 #define DWT_FUNCTION_DATAVADDR0_Pos 12U
1220 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
1222 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
1223 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1225 #define DWT_FUNCTION_LNK1ENA_Pos 9U
1226 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
1228 #define DWT_FUNCTION_DATAVMATCH_Pos 8U
1229 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
1231 #define DWT_FUNCTION_CYCMATCH_Pos 7U
1232 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
1234 #define DWT_FUNCTION_EMITRANGE_Pos 5U
1235 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
1237 #define DWT_FUNCTION_FUNCTION_Pos 0U
1238 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)
1240  /* end of group CMSIS_DWT */
1241 
1242 
1253 typedef struct
1254 {
1255  __IOM uint32_t SSPSR;
1256  __IOM uint32_t CSPSR;
1257  uint32_t RESERVED0[2U];
1258  __IOM uint32_t ACPR;
1259  uint32_t RESERVED1[55U];
1260  __IOM uint32_t SPPR;
1261  uint32_t RESERVED2[131U];
1262  __IM uint32_t FFSR;
1263  __IOM uint32_t FFCR;
1264  __IM uint32_t FSCR;
1265  uint32_t RESERVED3[759U];
1266  __IM uint32_t TRIGGER;
1267  __IM uint32_t FIFO0;
1268  __IM uint32_t ITATBCTR2;
1269  uint32_t RESERVED4[1U];
1270  __IM uint32_t ITATBCTR0;
1271  __IM uint32_t FIFO1;
1272  __IOM uint32_t ITCTRL;
1273  uint32_t RESERVED5[39U];
1274  __IOM uint32_t CLAIMSET;
1275  __IOM uint32_t CLAIMCLR;
1276  uint32_t RESERVED7[8U];
1277  __IM uint32_t DEVID;
1278  __IM uint32_t DEVTYPE;
1279 } TPI_Type;
1280 
1281 /* TPI Asynchronous Clock Prescaler Register Definitions */
1282 #define TPI_ACPR_PRESCALER_Pos 0U
1283 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
1285 /* TPI Selected Pin Protocol Register Definitions */
1286 #define TPI_SPPR_TXMODE_Pos 0U
1287 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1289 /* TPI Formatter and Flush Status Register Definitions */
1290 #define TPI_FFSR_FtNonStop_Pos 3U
1291 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1293 #define TPI_FFSR_TCPresent_Pos 2U
1294 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1296 #define TPI_FFSR_FtStopped_Pos 1U
1297 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1299 #define TPI_FFSR_FlInProg_Pos 0U
1300 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1302 /* TPI Formatter and Flush Control Register Definitions */
1303 #define TPI_FFCR_TrigIn_Pos 8U
1304 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1306 #define TPI_FFCR_EnFCont_Pos 1U
1307 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1309 /* TPI TRIGGER Register Definitions */
1310 #define TPI_TRIGGER_TRIGGER_Pos 0U
1311 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
1313 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1314 #define TPI_FIFO0_ITM_ATVALID_Pos 29U
1315 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
1317 #define TPI_FIFO0_ITM_bytecount_Pos 27U
1318 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
1320 #define TPI_FIFO0_ETM_ATVALID_Pos 26U
1321 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
1323 #define TPI_FIFO0_ETM_bytecount_Pos 24U
1324 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
1326 #define TPI_FIFO0_ETM2_Pos 16U
1327 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
1329 #define TPI_FIFO0_ETM1_Pos 8U
1330 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
1332 #define TPI_FIFO0_ETM0_Pos 0U
1333 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
1335 /* TPI ITATBCTR2 Register Definitions */
1336 #define TPI_ITATBCTR2_ATREADY_Pos 0U
1337 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)
1339 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1340 #define TPI_FIFO1_ITM_ATVALID_Pos 29U
1341 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
1343 #define TPI_FIFO1_ITM_bytecount_Pos 27U
1344 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
1346 #define TPI_FIFO1_ETM_ATVALID_Pos 26U
1347 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
1349 #define TPI_FIFO1_ETM_bytecount_Pos 24U
1350 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1352 #define TPI_FIFO1_ITM2_Pos 16U
1353 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1355 #define TPI_FIFO1_ITM1_Pos 8U
1356 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1358 #define TPI_FIFO1_ITM0_Pos 0U
1359 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
1361 /* TPI ITATBCTR0 Register Definitions */
1362 #define TPI_ITATBCTR0_ATREADY_Pos 0U
1363 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)
1365 /* TPI Integration Mode Control Register Definitions */
1366 #define TPI_ITCTRL_Mode_Pos 0U
1367 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)
1369 /* TPI DEVID Register Definitions */
1370 #define TPI_DEVID_NRZVALID_Pos 11U
1371 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1373 #define TPI_DEVID_MANCVALID_Pos 10U
1374 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1376 #define TPI_DEVID_PTINVALID_Pos 9U
1377 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1379 #define TPI_DEVID_MinBufSz_Pos 6U
1380 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1382 #define TPI_DEVID_AsynClkIn_Pos 5U
1383 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1385 #define TPI_DEVID_NrTraceInput_Pos 0U
1386 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
1388 /* TPI DEVTYPE Register Definitions */
1389 #define TPI_DEVTYPE_MajorType_Pos 4U
1390 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1392 #define TPI_DEVTYPE_SubType_Pos 0U
1393 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1395  /* end of group CMSIS_TPI */
1396 
1397 
1398 #if (__MPU_PRESENT == 1U)
1399 
1409 typedef struct
1410 {
1411  __IM uint32_t TYPE;
1412  __IOM uint32_t CTRL;
1413  __IOM uint32_t RNR;
1414  __IOM uint32_t RBAR;
1415  __IOM uint32_t RASR;
1416  __IOM uint32_t RBAR_A1;
1417  __IOM uint32_t RASR_A1;
1418  __IOM uint32_t RBAR_A2;
1419  __IOM uint32_t RASR_A2;
1420  __IOM uint32_t RBAR_A3;
1421  __IOM uint32_t RASR_A3;
1422 } MPU_Type;
1423 
1424 /* MPU Type Register Definitions */
1425 #define MPU_TYPE_IREGION_Pos 16U
1426 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1428 #define MPU_TYPE_DREGION_Pos 8U
1429 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1431 #define MPU_TYPE_SEPARATE_Pos 0U
1432 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1434 /* MPU Control Register Definitions */
1435 #define MPU_CTRL_PRIVDEFENA_Pos 2U
1436 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1438 #define MPU_CTRL_HFNMIENA_Pos 1U
1439 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1441 #define MPU_CTRL_ENABLE_Pos 0U
1442 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1444 /* MPU Region Number Register Definitions */
1445 #define MPU_RNR_REGION_Pos 0U
1446 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1448 /* MPU Region Base Address Register Definitions */
1449 #define MPU_RBAR_ADDR_Pos 5U
1450 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1452 #define MPU_RBAR_VALID_Pos 4U
1453 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1455 #define MPU_RBAR_REGION_Pos 0U
1456 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
1458 /* MPU Region Attribute and Size Register Definitions */
1459 #define MPU_RASR_ATTRS_Pos 16U
1460 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1462 #define MPU_RASR_XN_Pos 28U
1463 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1465 #define MPU_RASR_AP_Pos 24U
1466 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1468 #define MPU_RASR_TEX_Pos 19U
1469 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1471 #define MPU_RASR_S_Pos 18U
1472 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1474 #define MPU_RASR_C_Pos 17U
1475 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1477 #define MPU_RASR_B_Pos 16U
1478 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1480 #define MPU_RASR_SRD_Pos 8U
1481 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1483 #define MPU_RASR_SIZE_Pos 1U
1484 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1486 #define MPU_RASR_ENABLE_Pos 0U
1487 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/)
1489 
1490 #endif
1491 
1492 
1493 #if (__FPU_PRESENT == 1U)
1494 
1504 typedef struct
1505 {
1506  uint32_t RESERVED0[1U];
1507  __IOM uint32_t FPCCR;
1508  __IOM uint32_t FPCAR;
1509  __IOM uint32_t FPDSCR;
1510  __IM uint32_t MVFR0;
1511  __IM uint32_t MVFR1;
1512  __IM uint32_t MVFR2;
1513 } FPU_Type;
1514 
1515 /* Floating-Point Context Control Register Definitions */
1516 #define FPU_FPCCR_ASPEN_Pos 31U
1517 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1519 #define FPU_FPCCR_LSPEN_Pos 30U
1520 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1522 #define FPU_FPCCR_MONRDY_Pos 8U
1523 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1525 #define FPU_FPCCR_BFRDY_Pos 6U
1526 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1528 #define FPU_FPCCR_MMRDY_Pos 5U
1529 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1531 #define FPU_FPCCR_HFRDY_Pos 4U
1532 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1534 #define FPU_FPCCR_THREAD_Pos 3U
1535 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1537 #define FPU_FPCCR_USER_Pos 1U
1538 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1540 #define FPU_FPCCR_LSPACT_Pos 0U
1541 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
1543 /* Floating-Point Context Address Register Definitions */
1544 #define FPU_FPCAR_ADDRESS_Pos 3U
1545 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1547 /* Floating-Point Default Status Control Register Definitions */
1548 #define FPU_FPDSCR_AHP_Pos 26U
1549 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1551 #define FPU_FPDSCR_DN_Pos 25U
1552 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1554 #define FPU_FPDSCR_FZ_Pos 24U
1555 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1557 #define FPU_FPDSCR_RMode_Pos 22U
1558 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1560 /* Media and FP Feature Register 0 Definitions */
1561 #define FPU_MVFR0_FP_rounding_modes_Pos 28U
1562 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1564 #define FPU_MVFR0_Short_vectors_Pos 24U
1565 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1567 #define FPU_MVFR0_Square_root_Pos 20U
1568 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1570 #define FPU_MVFR0_Divide_Pos 16U
1571 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1573 #define FPU_MVFR0_FP_excep_trapping_Pos 12U
1574 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1576 #define FPU_MVFR0_Double_precision_Pos 8U
1577 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1579 #define FPU_MVFR0_Single_precision_Pos 4U
1580 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1582 #define FPU_MVFR0_A_SIMD_registers_Pos 0U
1583 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
1585 /* Media and FP Feature Register 1 Definitions */
1586 #define FPU_MVFR1_FP_fused_MAC_Pos 28U
1587 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1589 #define FPU_MVFR1_FP_HPFP_Pos 24U
1590 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1592 #define FPU_MVFR1_D_NaN_mode_Pos 4U
1593 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1595 #define FPU_MVFR1_FtZ_mode_Pos 0U
1596 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
1598 /* Media and FP Feature Register 2 Definitions */
1599 
1601 #endif
1602 
1603 
1614 typedef struct
1615 {
1616  __IOM uint32_t DHCSR;
1617  __OM uint32_t DCRSR;
1618  __IOM uint32_t DCRDR;
1619  __IOM uint32_t DEMCR;
1620 } CoreDebug_Type;
1621 
1622 /* Debug Halting Control and Status Register Definitions */
1623 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1624 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1626 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1627 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1629 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1630 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1632 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1633 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1635 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1636 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1638 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1639 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1641 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1642 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1644 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1645 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1647 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1648 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1650 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1651 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1653 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1654 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1656 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1657 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1659 /* Debug Core Register Selector Register Definitions */
1660 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1661 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1663 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1664 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1666 /* Debug Exception and Monitor Control Register Definitions */
1667 #define CoreDebug_DEMCR_TRCENA_Pos 24U
1668 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1670 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
1671 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1673 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
1674 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1676 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
1677 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1679 #define CoreDebug_DEMCR_MON_EN_Pos 16U
1680 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1682 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1683 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1685 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1686 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1688 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1689 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1691 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1692 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1694 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1695 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1697 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1698 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1700 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1701 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1703 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1704 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1706 
1722 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
1723 
1730 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
1731 
1742 /* Memory mapping of Cortex-M4 Hardware */
1743 #define SCS_BASE (0xE000E000UL)
1744 #define ITM_BASE (0xE0000000UL)
1745 #define DWT_BASE (0xE0001000UL)
1746 #define TPI_BASE (0xE0040000UL)
1747 #define CoreDebug_BASE (0xE000EDF0UL)
1748 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1749 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1750 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1752 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1753 #define SCB ((SCB_Type *) SCB_BASE )
1754 #define SysTick ((SysTick_Type *) SysTick_BASE )
1755 #define NVIC ((NVIC_Type *) NVIC_BASE )
1756 #define ITM ((ITM_Type *) ITM_BASE )
1757 #define DWT ((DWT_Type *) DWT_BASE )
1758 #define TPI ((TPI_Type *) TPI_BASE )
1759 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1761 #if (__MPU_PRESENT == 1U)
1762  #define MPU_BASE (SCS_BASE + 0x0D90UL)
1763  #define MPU ((MPU_Type *) MPU_BASE )
1764 #endif
1765 
1766 #if (__FPU_PRESENT == 1U)
1767  #define FPU_BASE (SCS_BASE + 0x0F30UL)
1768  #define FPU ((FPU_Type *) FPU_BASE )
1769 #endif
1770 
1775 /*******************************************************************************
1776  * Hardware Abstraction Layer
1777  Core Function Interface contains:
1778  - Core NVIC Functions
1779  - Core SysTick Functions
1780  - Core Debug Functions
1781  - Core Register Access Functions
1782  ******************************************************************************/
1790 /* ########################## NVIC functions #################################### */
1807 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1808 {
1809  uint32_t reg_value;
1810  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1811 
1812  reg_value = SCB->AIRCR; /* read old register configuration */
1813  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1814  reg_value = (reg_value |
1815  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1816  (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
1817  SCB->AIRCR = reg_value;
1818 }
1819 
1820 
1826 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1827 {
1828  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1829 }
1830 
1831 
1837 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1838 {
1839  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1840 }
1841 
1842 
1848 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1849 {
1850  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1851 }
1852 
1853 
1861 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1862 {
1863  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1864 }
1865 
1866 
1872 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1873 {
1874  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1875 }
1876 
1877 
1883 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1884 {
1885  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1886 }
1887 
1888 
1896 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1897 {
1898  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1899 }
1900 
1901 
1909 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1910 {
1911  if ((int32_t)(IRQn) < 0)
1912  {
1913  SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1914  }
1915  else
1916  {
1917  NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1918  }
1919 }
1920 
1921 
1931 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1932 {
1933 
1934  if ((int32_t)(IRQn) < 0)
1935  {
1936  return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1937  }
1938  else
1939  {
1940  return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1941  }
1942 }
1943 
1944 
1956 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1957 {
1958  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1959  uint32_t PreemptPriorityBits;
1960  uint32_t SubPriorityBits;
1961 
1962  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1963  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1964 
1965  return (
1966  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1967  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1968  );
1969 }
1970 
1971 
1983 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1984 {
1985  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1986  uint32_t PreemptPriorityBits;
1987  uint32_t SubPriorityBits;
1988 
1989  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1990  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1991 
1992  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1993  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1994 }
1995 
1996 
2001 __STATIC_INLINE void NVIC_SystemReset(void)
2002 {
2003  __DSB(); /* Ensure all outstanding memory accesses included
2004  buffered write are completed before reset */
2005  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2006  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2007  SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2008  __DSB(); /* Ensure completion of memory access */
2009 
2010  for(;;) /* wait until reset */
2011  {
2012  __NOP();
2013  }
2014 }
2015 
2019 /* ########################## FPU functions #################################### */
2035 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2036 {
2037  uint32_t mvfr0;
2038 
2039  mvfr0 = SCB->MVFR0;
2040  if ((mvfr0 & 0x00000FF0UL) == 0x220UL)
2041  {
2042  return 2UL; /* Double + Single precision FPU */
2043  }
2044  else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)
2045  {
2046  return 1UL; /* Single precision FPU */
2047  }
2048  else
2049  {
2050  return 0UL; /* No FPU */
2051  }
2052 }
2053 
2054 
2059 /* ########################## Cache functions #################################### */
2067 /* Cache Size ID Register Macros */
2068 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
2069 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
2070 
2071 
2076 __STATIC_INLINE void SCB_EnableICache (void)
2077 {
2078  #if (__ICACHE_PRESENT == 1U)
2079  __DSB();
2080  __ISB();
2081  SCB->ICIALLU = 0UL; /* invalidate I-Cache */
2082  SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
2083  __DSB();
2084  __ISB();
2085  #endif
2086 }
2087 
2088 
2093 __STATIC_INLINE void SCB_DisableICache (void)
2094 {
2095  #if (__ICACHE_PRESENT == 1U)
2096  __DSB();
2097  __ISB();
2098  SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
2099  SCB->ICIALLU = 0UL; /* invalidate I-Cache */
2100  __DSB();
2101  __ISB();
2102  #endif
2103 }
2104 
2105 
2110 __STATIC_INLINE void SCB_InvalidateICache (void)
2111 {
2112  #if (__ICACHE_PRESENT == 1U)
2113  __DSB();
2114  __ISB();
2115  SCB->ICIALLU = 0UL;
2116  __DSB();
2117  __ISB();
2118  #endif
2119 }
2120 
2121 
2126 __STATIC_INLINE void SCB_EnableDCache (void)
2127 {
2128  #if (__DCACHE_PRESENT == 1U)
2129  uint32_t ccsidr;
2130  uint32_t sets;
2131  uint32_t ways;
2132 
2133  SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
2134  __DSB();
2135 
2136  ccsidr = SCB->CCSIDR;
2137 
2138  /* invalidate D-Cache */
2139  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2140  do {
2141  ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2142  do {
2143  SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
2144  ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
2145  #if defined ( __CC_ARM )
2146  __schedule_barrier();
2147  #endif
2148  } while (ways--);
2149  } while(sets--);
2150  __DSB();
2151 
2152  SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
2153 
2154  __DSB();
2155  __ISB();
2156  #endif
2157 }
2158 
2159 
2164 __STATIC_INLINE void SCB_DisableDCache (void)
2165 {
2166  #if (__DCACHE_PRESENT == 1U)
2167  uint32_t ccsidr;
2168  uint32_t sets;
2169  uint32_t ways;
2170 
2171  SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
2172  __DSB();
2173 
2174  ccsidr = SCB->CCSIDR;
2175 
2176  SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
2177 
2178  /* clean & invalidate D-Cache */
2179  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2180  do {
2181  ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2182  do {
2183  SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
2184  ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
2185  #if defined ( __CC_ARM )
2186  __schedule_barrier();
2187  #endif
2188  } while (ways--);
2189  } while(sets--);
2190 
2191  __DSB();
2192  __ISB();
2193  #endif
2194 }
2195 
2196 
2201 __STATIC_INLINE void SCB_InvalidateDCache (void)
2202 {
2203  #if (__DCACHE_PRESENT == 1U)
2204  uint32_t ccsidr;
2205  uint32_t sets;
2206  uint32_t ways;
2207 
2208  SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
2209  __DSB();
2210 
2211  ccsidr = SCB->CCSIDR;
2212 
2213  /* invalidate D-Cache */
2214  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2215  do {
2216  ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2217  do {
2218  SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
2219  ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
2220  #if defined ( __CC_ARM )
2221  __schedule_barrier();
2222  #endif
2223  } while (ways--);
2224  } while(sets--);
2225 
2226  __DSB();
2227  __ISB();
2228  #endif
2229 }
2230 
2231 
2236 __STATIC_INLINE void SCB_CleanDCache (void)
2237 {
2238  #if (__DCACHE_PRESENT == 1U)
2239  uint32_t ccsidr;
2240  uint32_t sets;
2241  uint32_t ways;
2242 
2243  SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
2244  __DSB();
2245 
2246  ccsidr = SCB->CCSIDR;
2247 
2248  /* clean D-Cache */
2249  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2250  do {
2251  ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2252  do {
2253  SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
2254  ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
2255  #if defined ( __CC_ARM )
2256  __schedule_barrier();
2257  #endif
2258  } while (ways--);
2259  } while(sets--);
2260 
2261  __DSB();
2262  __ISB();
2263  #endif
2264 }
2265 
2266 
2271 __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
2272 {
2273  #if (__DCACHE_PRESENT == 1U)
2274  uint32_t ccsidr;
2275  uint32_t sets;
2276  uint32_t ways;
2277 
2278  SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
2279  __DSB();
2280 
2281  ccsidr = SCB->CCSIDR;
2282 
2283  /* clean & invalidate D-Cache */
2284  sets = (uint32_t)(CCSIDR_SETS(ccsidr));
2285  do {
2286  ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
2287  do {
2288  SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
2289  ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
2290  #if defined ( __CC_ARM )
2291  __schedule_barrier();
2292  #endif
2293  } while (ways--);
2294  } while(sets--);
2295 
2296  __DSB();
2297  __ISB();
2298  #endif
2299 }
2300 
2301 
2308 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
2309 {
2310  #if (__DCACHE_PRESENT == 1U)
2311  int32_t op_size = dsize;
2312  uint32_t op_addr = (uint32_t)addr;
2313  int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
2314 
2315  __DSB();
2316 
2317  while (op_size > 0) {
2318  SCB->DCIMVAC = op_addr;
2319  op_addr += linesize;
2320  op_size -= linesize;
2321  }
2322 
2323  __DSB();
2324  __ISB();
2325  #endif
2326 }
2327 
2328 
2335 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
2336 {
2337  #if (__DCACHE_PRESENT == 1)
2338  int32_t op_size = dsize;
2339  uint32_t op_addr = (uint32_t) addr;
2340  int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
2341 
2342  __DSB();
2343 
2344  while (op_size > 0) {
2345  SCB->DCCMVAC = op_addr;
2346  op_addr += linesize;
2347  op_size -= linesize;
2348  }
2349 
2350  __DSB();
2351  __ISB();
2352  #endif
2353 }
2354 
2355 
2362 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
2363 {
2364  #if (__DCACHE_PRESENT == 1U)
2365  int32_t op_size = dsize;
2366  uint32_t op_addr = (uint32_t) addr;
2367  int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
2368 
2369  __DSB();
2370 
2371  while (op_size > 0) {
2372  SCB->DCCIMVAC = op_addr;
2373  op_addr += linesize;
2374  op_size -= linesize;
2375  }
2376 
2377  __DSB();
2378  __ISB();
2379  #endif
2380 }
2381 
2382 
2387 /* ################################## SysTick function ############################################ */
2395 #if (__Vendor_SysTickConfig == 0U)
2396 
2408 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2409 {
2410  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2411  {
2412  return (1UL); /* Reload value impossible */
2413  }
2414 
2415  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2416  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2417  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2418  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2419  SysTick_CTRL_TICKINT_Msk |
2420  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2421  return (0UL); /* Function successful */
2422 }
2423 
2424 #endif
2425 
2430 /* ##################################### Debug In/Output function ########################################### */
2438 extern volatile int32_t ITM_RxBuffer;
2439 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U
2450 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2451 {
2452  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2453  ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2454  {
2455  while (ITM->PORT[0U].u32 == 0UL)
2456  {
2457  __NOP();
2458  }
2459  ITM->PORT[0U].u8 = (uint8_t)ch;
2460  }
2461  return (ch);
2462 }
2463 
2464 
2471 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
2472 {
2473  int32_t ch = -1; /* no character available */
2474 
2475  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2476  {
2477  ch = ITM_RxBuffer;
2478  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2479  }
2480 
2481  return (ch);
2482 }
2483 
2484 
2491 __STATIC_INLINE int32_t ITM_CheckChar (void)
2492 {
2493 
2494  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2495  {
2496  return (0); /* no character available */
2497  }
2498  else
2499  {
2500  return (1); /* character available */
2501  }
2502 }
2503 
2509 #ifdef __cplusplus
2510 }
2511 #endif
2512 
2513 #endif /* __CORE_CM7_H_DEPENDANT */
2514 
2515 #endif /* __CMSIS_GENERIC */
xPSR_Type::Q
uint32_t Q
Definition: core_cm7.h:392
APSR_Type::GE
uint32_t GE
Definition: core_cm7.h:330
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_cm7.h:1983
IPSR_Type::w
uint32_t w
Definition: core_cm7.h:371
SysTick_IRQn
Definition: same70j19.h:68
TCR
#define TCR
tx configuration reg
Definition: wd80x3.h:99
SCB_DCCSW_WAY_Msk
#define SCB_DCCSW_WAY_Msk
Definition: core_cm7.h:811
SCB_DCCISW_SET_Msk
#define SCB_DCCISW_SET_Msk
Definition: core_cm7.h:821
xPSR_Type::C
uint32_t C
Definition: core_cm7.h:394
core_cmFunc.h
CMSIS Cortex-M Core Function Access Header File.
SCB_InvalidateICache
__STATIC_INLINE void SCB_InvalidateICache(void)
Invalidate I-Cache.
Definition: core_cm7.h:2110
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_cm7.h:2035
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_cm7.h:2491
xPSR_Type::IT
uint32_t IT
Definition: core_cm7.h:391
SCB_DisableDCache
__STATIC_INLINE void SCB_DisableDCache(void)
Disable D-Cache.
Definition: core_cm7.h:2164
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm7.h:608
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm7.h:468
SCB_CCR_IC_Msk
#define SCB_CCR_IC_Msk
Definition: core_cm7.h:644
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm7.h:961
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_cm7.h:502
ITM
#define ITM
Definition: core_cm7.h:1756
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_cm7.h:1103
CONTROL_Type::w
uint32_t w
Definition: core_cm7.h:442
core_cmInstr.h
CMSIS Cortex-M Core Instruction Access Header File.
SCB_CleanDCache_by_Addr
__STATIC_INLINE void SCB_CleanDCache_by_Addr(uint32_t *addr, int32_t dsize)
D-Cache Clean by address.
Definition: core_cm7.h:2335
SCB_DCCISW_WAY_Msk
#define SCB_DCCISW_WAY_Msk
Definition: core_cm7.h:818
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_cm7.h:1956
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_cm7.h:2439
APSR_Type::_reserved1
uint32_t _reserved1
Definition: core_cm7.h:331
SCR
#define SCR
Scratch register.
Definition: uart.h:94
NVIC_SetPriority
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_cm7.h:1909
CONTROL_Type::_reserved0
uint32_t _reserved0
Definition: core_cm7.h:440
SCB_DCCISW_WAY_Pos
#define SCB_DCCISW_WAY_Pos
Definition: core_cm7.h:817
IPSR_Type::_reserved0
uint32_t _reserved0
Definition: core_cm7.h:369
SCB_EnableDCache
__STATIC_INLINE void SCB_EnableDCache(void)
Enable D-Cache.
Definition: core_cm7.h:2126
xPSR_Type::_reserved0
uint32_t _reserved0
Definition: core_cm7.h:387
SCB_DisableICache
__STATIC_INLINE void SCB_DisableICache(void)
Disable I-Cache.
Definition: core_cm7.h:2093
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
SCB_CleanInvalidateDCache_by_Addr
__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize)
D-Cache Clean and Invalidate by address.
Definition: core_cm7.h:2362
APSR_Type::_reserved0
uint32_t _reserved0
Definition: core_cm7.h:329
SCB_EnableICache
__STATIC_INLINE void SCB_EnableICache(void)
Enable I-Cache.
Definition: core_cm7.h:2076
SCB_InvalidateDCache
__STATIC_INLINE void SCB_InvalidateDCache(void)
Invalidate D-Cache.
Definition: core_cm7.h:2201
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm7.h:964
SCB
#define SCB
Definition: core_cm7.h:1753
NVIC_DisableIRQ
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
Definition: core_cm7.h:1848
xPSR_Type::ISR
uint32_t ISR
Definition: core_cm7.h:386
xPSR_Type::Z
uint32_t Z
Definition: core_cm7.h:395
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_cm7.h:948
SCB_DCCSW_SET_Pos
#define SCB_DCCSW_SET_Pos
Definition: core_cm7.h:813
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_cm7.h:1614
SCB_DCISW_WAY_Msk
#define SCB_DCISW_WAY_Msk
Definition: core_cm7.h:804
core_cmSimd.h
CMSIS Cortex-M SIMD Header File.
NVIC_SystemReset
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
Definition: core_cm7.h:2001
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_cm7.h:325
APSR_Type::V
uint32_t V
Definition: core_cm7.h:333
NVIC_EnableIRQ
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
Definition: core_cm7.h:1837
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_cm7.h:609
xPSR_Type::N
uint32_t N
Definition: core_cm7.h:396
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: same70j19.h:276
NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_cm7.h:1861
xPSR_Type::V
uint32_t V
Definition: core_cm7.h:393
APSR_Type::C
uint32_t C
Definition: core_cm7.h:334
SCB_CleanInvalidateDCache
__STATIC_INLINE void SCB_CleanInvalidateDCache(void)
Clean & Invalidate D-Cache.
Definition: core_cm7.h:2271
SysTick
#define SysTick
Definition: core_cm7.h:1754
SCB_DCCSW_SET_Msk
#define SCB_DCCSW_SET_Msk
Definition: core_cm7.h:814
APSR_Type::Z
uint32_t Z
Definition: core_cm7.h:335
CONTROL_Type::SPSEL
uint32_t SPSEL
Definition: core_cm7.h:438
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_cm7.h:618
xPSR_Type::GE
uint32_t GE
Definition: core_cm7.h:388
SysTick_Config
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
Definition: core_cm7.h:2408
SCB_DCISW_WAY_Pos
#define SCB_DCISW_WAY_Pos
Definition: core_cm7.h:803
SCB_DCISW_SET_Pos
#define SCB_DCISW_SET_Pos
Definition: core_cm7.h:806
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_cm7.h:433
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_cm7.h:1253
NVIC
#define NVIC
Definition: core_cm7.h:1755
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm7.h:971
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_cm7.h:908
NVIC_SetPendingIRQ
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_cm7.h:1872
xPSR_Type::_reserved1
uint32_t _reserved1
Definition: core_cm7.h:389
NVIC_ClearPendingIRQ
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_cm7.h:1883
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm7.h:364
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_cm7.h:2471
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm7.h:382
xPSR_Type::T
uint32_t T
Definition: core_cm7.h:390
NVIC_GetPriority
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_cm7.h:1931
SCB_DCCSW_WAY_Pos
#define SCB_DCCSW_WAY_Pos
Definition: core_cm7.h:810
CONTROL_Type::FPCA
uint32_t FPCA
Definition: core_cm7.h:439
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm7.h:967
SCB_CleanDCache
__STATIC_INLINE void SCB_CleanDCache(void)
Clean D-Cache.
Definition: core_cm7.h:2236
SCB_DCCISW_SET_Pos
#define SCB_DCCISW_SET_Pos
Definition: core_cm7.h:820
SCB_CCR_DC_Msk
#define SCB_CCR_DC_Msk
Definition: core_cm7.h:647
IRQn_Type
enum IRQn IRQn_Type
CONTROL_Type::nPRIV
uint32_t nPRIV
Definition: core_cm7.h:437
APSR_Type::Q
uint32_t Q
Definition: core_cm7.h:332
SCB_DCISW_SET_Msk
#define SCB_DCISW_SET_Msk
Definition: core_cm7.h:807
NVIC_GetActive
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_cm7.h:1896
NVIC_SetPriorityGrouping
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_cm7.h:1807
IRQn
IRQn
Definition: same70j19.h:57
xPSR_Type::w
uint32_t w
Definition: core_cm7.h:398
NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_cm7.h:1826
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_cm7.h:1066
APSR_Type::N
uint32_t N
Definition: core_cm7.h:336
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm7.h:621
APSR_Type::w
uint32_t w
Definition: core_cm7.h:338
SCB_InvalidateDCache_by_Addr
__STATIC_INLINE void SCB_InvalidateDCache_by_Addr(uint32_t *addr, int32_t dsize)
D-Cache Invalidate by address.
Definition: core_cm7.h:2308
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_cm7.h:1000
LSR
#define LSR
Line Status Register.
Definition: uart.h:92
IPSR_Type::ISR
uint32_t ISR
Definition: core_cm7.h:368
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_cm7.h:617
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