RTEMS  5.0.0
Data Fields

Structure type to access the Data Watchpoint and Trace Register (DWT). More...

#include <core_cm7.h>

Data Fields

__IOM uint32_t CTRL
 
__IOM uint32_t CYCCNT
 
__IOM uint32_t CPICNT
 
__IOM uint32_t EXCCNT
 
__IOM uint32_t SLEEPCNT
 
__IOM uint32_t LSUCNT
 
__IOM uint32_t FOLDCNT
 
__IM uint32_t PCSR
 
__IOM uint32_t COMP0
 
__IOM uint32_t MASK0
 
__IOM uint32_t FUNCTION0
 
uint32_t RESERVED0 [1U]
 
__IOM uint32_t COMP1
 
__IOM uint32_t MASK1
 
__IOM uint32_t FUNCTION1
 
uint32_t RESERVED1 [1U]
 
__IOM uint32_t COMP2
 
__IOM uint32_t MASK2
 
__IOM uint32_t FUNCTION2
 
uint32_t RESERVED2 [1U]
 
__IOM uint32_t COMP3
 
__IOM uint32_t MASK3
 
__IOM uint32_t FUNCTION3
 
uint32_t RESERVED3 [981U]
 
__OM uint32_t LAR
 
__IM uint32_t LSR
 

Detailed Description

Structure type to access the Data Watchpoint and Trace Register (DWT).

Field Documentation

◆ COMP0

__IOM uint32_t DWT_Type::COMP0

Offset: 0x020 (R/W) Comparator Register 0

◆ COMP1

__IOM uint32_t DWT_Type::COMP1

Offset: 0x030 (R/W) Comparator Register 1

◆ COMP2

__IOM uint32_t DWT_Type::COMP2

Offset: 0x040 (R/W) Comparator Register 2

◆ COMP3

__IOM uint32_t DWT_Type::COMP3

Offset: 0x050 (R/W) Comparator Register 3

◆ CPICNT

__IOM uint32_t DWT_Type::CPICNT

Offset: 0x008 (R/W) CPI Count Register

◆ CTRL

__IOM uint32_t DWT_Type::CTRL

Offset: 0x000 (R/W) Control Register

◆ CYCCNT

__IOM uint32_t DWT_Type::CYCCNT

Offset: 0x004 (R/W) Cycle Count Register

◆ EXCCNT

__IOM uint32_t DWT_Type::EXCCNT

Offset: 0x00C (R/W) Exception Overhead Count Register

◆ FOLDCNT

__IOM uint32_t DWT_Type::FOLDCNT

Offset: 0x018 (R/W) Folded-instruction Count Register

◆ FUNCTION0

__IOM uint32_t DWT_Type::FUNCTION0

Offset: 0x028 (R/W) Function Register 0

◆ FUNCTION1

__IOM uint32_t DWT_Type::FUNCTION1

Offset: 0x038 (R/W) Function Register 1

◆ FUNCTION2

__IOM uint32_t DWT_Type::FUNCTION2

Offset: 0x048 (R/W) Function Register 2

◆ FUNCTION3

__IOM uint32_t DWT_Type::FUNCTION3

Offset: 0x058 (R/W) Function Register 3

◆ LAR

__OM uint32_t DWT_Type::LAR

Offset: 0xFB0 ( W) Lock Access Register

◆ LSR

__IM uint32_t DWT_Type::LSR

Offset: 0xFB4 (R ) Lock Status Register

◆ LSUCNT

__IOM uint32_t DWT_Type::LSUCNT

Offset: 0x014 (R/W) LSU Count Register

◆ MASK0

__IOM uint32_t DWT_Type::MASK0

Offset: 0x024 (R/W) Mask Register 0

◆ MASK1

__IOM uint32_t DWT_Type::MASK1

Offset: 0x034 (R/W) Mask Register 1

◆ MASK2

__IOM uint32_t DWT_Type::MASK2

Offset: 0x044 (R/W) Mask Register 2

◆ MASK3

__IOM uint32_t DWT_Type::MASK3

Offset: 0x054 (R/W) Mask Register 3

◆ PCSR

__IM uint32_t DWT_Type::PCSR

Offset: 0x01C (R/ ) Program Counter Sample Register

◆ SLEEPCNT

__IOM uint32_t DWT_Type::SLEEPCNT

Offset: 0x010 (R/W) Sleep Count Register


The documentation for this struct was generated from the following file: