RTEMS  5.0.0
Data Structures | Macros
Status and Control Registers

Core Register type definitions. More...

Data Structures

union  APSR_Type
 Union type to access the Application Program Status Register (APSR). More...
 
union  IPSR_Type
 Union type to access the Interrupt Program Status Register (IPSR). More...
 
union  xPSR_Type
 Union type to access the Special-Purpose Program Status Registers (xPSR). More...
 
union  CONTROL_Type
 Union type to access the Control Registers (CONTROL). More...
 

Macros

#define APSR_N_Pos   31U
 
#define APSR_N_Msk   (1UL << APSR_N_Pos)
 
#define APSR_Z_Pos   30U
 
#define APSR_Z_Msk   (1UL << APSR_Z_Pos)
 
#define APSR_C_Pos   29U
 
#define APSR_C_Msk   (1UL << APSR_C_Pos)
 
#define APSR_V_Pos   28U
 
#define APSR_V_Msk   (1UL << APSR_V_Pos)
 
#define APSR_Q_Pos   27U
 
#define APSR_Q_Msk   (1UL << APSR_Q_Pos)
 
#define APSR_GE_Pos   16U
 
#define APSR_GE_Msk   (0xFUL << APSR_GE_Pos)
 
#define IPSR_ISR_Pos   0U
 
#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)
 
#define xPSR_N_Pos   31U
 
#define xPSR_N_Msk   (1UL << xPSR_N_Pos)
 
#define xPSR_Z_Pos   30U
 
#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)
 
#define xPSR_C_Pos   29U
 
#define xPSR_C_Msk   (1UL << xPSR_C_Pos)
 
#define xPSR_V_Pos   28U
 
#define xPSR_V_Msk   (1UL << xPSR_V_Pos)
 
#define xPSR_Q_Pos   27U
 
#define xPSR_Q_Msk   (1UL << xPSR_Q_Pos)
 
#define xPSR_IT_Pos   25U
 
#define xPSR_IT_Msk   (3UL << xPSR_IT_Pos)
 
#define xPSR_T_Pos   24U
 
#define xPSR_T_Msk   (1UL << xPSR_T_Pos)
 
#define xPSR_GE_Pos   16U
 
#define xPSR_GE_Msk   (0xFUL << xPSR_GE_Pos)
 
#define xPSR_ISR_Pos   0U
 
#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)
 
#define CONTROL_FPCA_Pos   2U
 
#define CONTROL_FPCA_Msk   (1UL << CONTROL_FPCA_Pos)
 
#define CONTROL_SPSEL_Pos   1U
 
#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)
 
#define CONTROL_nPRIV_Pos   0U
 
#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)
 

Detailed Description

Core Register type definitions.

Macro Definition Documentation

◆ APSR_C_Msk

#define APSR_C_Msk   (1UL << APSR_C_Pos)

APSR: C Mask

◆ APSR_C_Pos

#define APSR_C_Pos   29U

APSR: C Position

◆ APSR_GE_Msk

#define APSR_GE_Msk   (0xFUL << APSR_GE_Pos)

APSR: GE Mask

◆ APSR_GE_Pos

#define APSR_GE_Pos   16U

APSR: GE Position

◆ APSR_N_Msk

#define APSR_N_Msk   (1UL << APSR_N_Pos)

APSR: N Mask

◆ APSR_N_Pos

#define APSR_N_Pos   31U

APSR: N Position

◆ APSR_Q_Msk

#define APSR_Q_Msk   (1UL << APSR_Q_Pos)

APSR: Q Mask

◆ APSR_Q_Pos

#define APSR_Q_Pos   27U

APSR: Q Position

◆ APSR_V_Msk

#define APSR_V_Msk   (1UL << APSR_V_Pos)

APSR: V Mask

◆ APSR_V_Pos

#define APSR_V_Pos   28U

APSR: V Position

◆ APSR_Z_Msk

#define APSR_Z_Msk   (1UL << APSR_Z_Pos)

APSR: Z Mask

◆ APSR_Z_Pos

#define APSR_Z_Pos   30U

APSR: Z Position

◆ CONTROL_FPCA_Msk

#define CONTROL_FPCA_Msk   (1UL << CONTROL_FPCA_Pos)

CONTROL: FPCA Mask

◆ CONTROL_FPCA_Pos

#define CONTROL_FPCA_Pos   2U

CONTROL: FPCA Position

◆ CONTROL_nPRIV_Msk

#define CONTROL_nPRIV_Msk   (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

◆ CONTROL_nPRIV_Pos

#define CONTROL_nPRIV_Pos   0U

CONTROL: nPRIV Position

◆ CONTROL_SPSEL_Msk

#define CONTROL_SPSEL_Msk   (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

◆ CONTROL_SPSEL_Pos

#define CONTROL_SPSEL_Pos   1U

CONTROL: SPSEL Position

◆ IPSR_ISR_Msk

#define IPSR_ISR_Msk   (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

◆ IPSR_ISR_Pos

#define IPSR_ISR_Pos   0U

IPSR: ISR Position

◆ xPSR_C_Msk

#define xPSR_C_Msk   (1UL << xPSR_C_Pos)

xPSR: C Mask

◆ xPSR_C_Pos

#define xPSR_C_Pos   29U

xPSR: C Position

◆ xPSR_GE_Msk

#define xPSR_GE_Msk   (0xFUL << xPSR_GE_Pos)

xPSR: GE Mask

◆ xPSR_GE_Pos

#define xPSR_GE_Pos   16U

xPSR: GE Position

◆ xPSR_ISR_Msk

#define xPSR_ISR_Msk   (0x1FFUL /*<< xPSR_ISR_Pos*/)

xPSR: ISR Mask

◆ xPSR_ISR_Pos

#define xPSR_ISR_Pos   0U

xPSR: ISR Position

◆ xPSR_IT_Msk

#define xPSR_IT_Msk   (3UL << xPSR_IT_Pos)

xPSR: IT Mask

◆ xPSR_IT_Pos

#define xPSR_IT_Pos   25U

xPSR: IT Position

◆ xPSR_N_Msk

#define xPSR_N_Msk   (1UL << xPSR_N_Pos)

xPSR: N Mask

◆ xPSR_N_Pos

#define xPSR_N_Pos   31U

xPSR: N Position

◆ xPSR_Q_Msk

#define xPSR_Q_Msk   (1UL << xPSR_Q_Pos)

xPSR: Q Mask

◆ xPSR_Q_Pos

#define xPSR_Q_Pos   27U

xPSR: Q Position

◆ xPSR_T_Msk

#define xPSR_T_Msk   (1UL << xPSR_T_Pos)

xPSR: T Mask

◆ xPSR_T_Pos

#define xPSR_T_Pos   24U

xPSR: T Position

◆ xPSR_V_Msk

#define xPSR_V_Msk   (1UL << xPSR_V_Pos)

xPSR: V Mask

◆ xPSR_V_Pos

#define xPSR_V_Pos   28U

xPSR: V Position

◆ xPSR_Z_Msk

#define xPSR_Z_Msk   (1UL << xPSR_Z_Pos)

xPSR: Z Mask

◆ xPSR_Z_Pos

#define xPSR_Z_Pos   30U

xPSR: Z Position