RTEMS  5.0.0
Data Fields

Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...

#include <core_cm7.h>

Data Fields

__IOM uint32_t ISER [8U]
 
uint32_t RESERVED0 [24U]
 
__IOM uint32_t ICER [8U]
 
uint32_t RSERVED1 [24U]
 
__IOM uint32_t ISPR [8U]
 
uint32_t RESERVED2 [24U]
 
__IOM uint32_t ICPR [8U]
 
uint32_t RESERVED3 [24U]
 
__IOM uint32_t IABR [8U]
 
uint32_t RESERVED4 [56U]
 
__IOM uint8_t IP [240U]
 
uint32_t RESERVED5 [644U]
 
__OM uint32_t STIR
 

Detailed Description

Structure type to access the Nested Vectored Interrupt Controller (NVIC).

Field Documentation

◆ IABR

__IOM uint32_t NVIC_Type::IABR[8U]

Offset: 0x200 (R/W) Interrupt Active bit Register

◆ ICER

__IOM uint32_t NVIC_Type::ICER[8U]

Offset: 0x080 (R/W) Interrupt Clear Enable Register

◆ ICPR

__IOM uint32_t NVIC_Type::ICPR[8U]

Offset: 0x180 (R/W) Interrupt Clear Pending Register

◆ IP

__IOM uint8_t NVIC_Type::IP[240U]

Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

◆ ISER

__IOM uint32_t NVIC_Type::ISER[8U]

Offset: 0x000 (R/W) Interrupt Set Enable Register

◆ ISPR

__IOM uint32_t NVIC_Type::ISPR[8U]

Offset: 0x100 (R/W) Interrupt Set Pending Register

◆ STIR

__OM uint32_t NVIC_Type::STIR

Offset: 0xE00 ( /W) Software Trigger Interrupt Register


The documentation for this struct was generated from the following file: