Structure type to access the System Control Block (SCB). More...

#include <core_cm7.h>

Data Fields
__IM uint32_t	CPUID

__IOM uint32_t	ICSR

__IOM uint32_t	VTOR

__IOM uint32_t	AIRCR

__IOM uint32_t	SCR

__IOM uint32_t	CCR

__IOM uint8_t	SHPR [12U]

__IOM uint32_t	SHCSR

__IOM uint32_t	CFSR

__IOM uint32_t	HFSR

__IOM uint32_t	DFSR

__IOM uint32_t	MMFAR

__IOM uint32_t	BFAR

__IOM uint32_t	AFSR

__IM uint32_t	ID_PFR [2U]

__IM uint32_t	ID_DFR

__IM uint32_t	ID_AFR

__IM uint32_t	ID_MFR [4U]

__IM uint32_t	ID_ISAR [5U]

uint32_t	RESERVED0 [1U]

__IM uint32_t	CLIDR

__IM uint32_t	CTR

__IM uint32_t	CCSIDR

__IOM uint32_t	CSSELR

__IOM uint32_t	CPACR

uint32_t	RESERVED3 [93U]

__OM uint32_t	STIR

uint32_t	RESERVED4 [15U]

__IM uint32_t	MVFR0

__IM uint32_t	MVFR1

__IM uint32_t	MVFR2

uint32_t	RESERVED5 [1U]

__OM uint32_t	ICIALLU

uint32_t	RESERVED6 [1U]

__OM uint32_t	ICIMVAU

__OM uint32_t	DCIMVAC

__OM uint32_t	DCISW

__OM uint32_t	DCCMVAU

__OM uint32_t	DCCMVAC

__OM uint32_t	DCCSW

__OM uint32_t	DCCIMVAC

__OM uint32_t	DCCISW

uint32_t	RESERVED7 [6U]

__IOM uint32_t	ITCMCR

__IOM uint32_t	DTCMCR

__IOM uint32_t	AHBPCR

__IOM uint32_t	CACR

__IOM uint32_t	AHBSCR

uint32_t	RESERVED8 [1U]

__IOM uint32_t	ABFSR

Detailed Description

Structure type to access the System Control Block (SCB).

Field Documentation

◆ ABFSR

__IOM uint32_t SCB_Type::ABFSR

Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register

◆ AFSR

__IOM uint32_t SCB_Type::AFSR

Offset: 0x03C (R/W) Auxiliary Fault Status Register

◆ AHBPCR

__IOM uint32_t SCB_Type::AHBPCR

Offset: 0x298 (R/W) AHBP Control Register

◆ AHBSCR

__IOM uint32_t SCB_Type::AHBSCR

Offset: 0x2A0 (R/W) AHB Slave Control Register

◆ AIRCR

__IOM uint32_t SCB_Type::AIRCR

Offset: 0x00C (R/W) Application Interrupt and Reset Control Register

◆ BFAR

__IOM uint32_t SCB_Type::BFAR

Offset: 0x038 (R/W) BusFault Address Register

◆ CACR

__IOM uint32_t SCB_Type::CACR

Offset: 0x29C (R/W) L1 Cache Control Register

◆ CCR

__IOM uint32_t SCB_Type::CCR

Offset: 0x014 (R/W) Configuration Control Register

◆ CCSIDR

__IM uint32_t SCB_Type::CCSIDR

Offset: 0x080 (R/ ) Cache Size ID Register

◆ CFSR

__IOM uint32_t SCB_Type::CFSR

Offset: 0x028 (R/W) Configurable Fault Status Register

◆ CLIDR

__IM uint32_t SCB_Type::CLIDR

Offset: 0x078 (R/ ) Cache Level ID register

◆ CPACR

__IOM uint32_t SCB_Type::CPACR

Offset: 0x088 (R/W) Coprocessor Access Control Register

◆ CPUID

__IM uint32_t SCB_Type::CPUID

Offset: 0x000 (R/ ) CPUID Base Register

◆ CSSELR

__IOM uint32_t SCB_Type::CSSELR

Offset: 0x084 (R/W) Cache Size Selection Register

◆ CTR

__IM uint32_t SCB_Type::CTR

Offset: 0x07C (R/ ) Cache Type register

◆ DCCIMVAC

__OM uint32_t SCB_Type::DCCIMVAC

Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC

◆ DCCISW

__OM uint32_t SCB_Type::DCCISW

Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way

◆ DCCMVAC

__OM uint32_t SCB_Type::DCCMVAC

Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC

◆ DCCMVAU

__OM uint32_t SCB_Type::DCCMVAU

Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU

◆ DCCSW

__OM uint32_t SCB_Type::DCCSW

Offset: 0x26C ( /W) D-Cache Clean by Set-way

◆ DCIMVAC

__OM uint32_t SCB_Type::DCIMVAC

Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC

◆ DCISW

__OM uint32_t SCB_Type::DCISW

Offset: 0x260 ( /W) D-Cache Invalidate by Set-way

◆ DFSR

__IOM uint32_t SCB_Type::DFSR

Offset: 0x030 (R/W) Debug Fault Status Register

◆ DTCMCR

__IOM uint32_t SCB_Type::DTCMCR

Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers

◆ HFSR

__IOM uint32_t SCB_Type::HFSR

Offset: 0x02C (R/W) HardFault Status Register

◆ ICIALLU

__OM uint32_t SCB_Type::ICIALLU

Offset: 0x250 ( /W) I-Cache Invalidate All to PoU

◆ ICIMVAU

__OM uint32_t SCB_Type::ICIMVAU

Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU

◆ ICSR

__IOM uint32_t SCB_Type::ICSR

Offset: 0x004 (R/W) Interrupt Control and State Register

◆ ID_AFR

__IM uint32_t SCB_Type::ID_AFR

Offset: 0x04C (R/ ) Auxiliary Feature Register

◆ ID_DFR

__IM uint32_t SCB_Type::ID_DFR

Offset: 0x048 (R/ ) Debug Feature Register

◆ ID_ISAR

__IM uint32_t SCB_Type::ID_ISAR[5U]

Offset: 0x060 (R/ ) Instruction Set Attributes Register

◆ ID_MFR

__IM uint32_t SCB_Type::ID_MFR[4U]

Offset: 0x050 (R/ ) Memory Model Feature Register

◆ ID_PFR

__IM uint32_t SCB_Type::ID_PFR[2U]

Offset: 0x040 (R/ ) Processor Feature Register

◆ ITCMCR

__IOM uint32_t SCB_Type::ITCMCR

Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register

◆ MMFAR

__IOM uint32_t SCB_Type::MMFAR

Offset: 0x034 (R/W) MemManage Fault Address Register

◆ MVFR0

__IM uint32_t SCB_Type::MVFR0

Offset: 0x240 (R/ ) Media and VFP Feature Register 0

◆ MVFR1

__IM uint32_t SCB_Type::MVFR1

Offset: 0x244 (R/ ) Media and VFP Feature Register 1

◆ MVFR2

__IM uint32_t SCB_Type::MVFR2

Offset: 0x248 (R/ ) Media and VFP Feature Register 1

◆ SCR

__IOM uint32_t SCB_Type::SCR

Offset: 0x010 (R/W) System Control Register

◆ SHCSR

__IOM uint32_t SCB_Type::SHCSR

Offset: 0x024 (R/W) System Handler Control and State Register

◆ SHPR

__IOM uint8_t SCB_Type::SHPR[12U]

Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)

◆ STIR

__OM uint32_t SCB_Type::STIR

Offset: 0x200 ( /W) Software Triggered Interrupt Register

◆ VTOR

__IOM uint32_t SCB_Type::VTOR

Offset: 0x008 (R/W) Vector Table Offset Register

The documentation for this struct was generated from the following file:

bsps/arm/include/core_cm7.h

Data Fields