29 #ifndef _RTEMS_SCORE_CPU_H 30 #define _RTEMS_SCORE_CPU_H 33 #if defined(RTEMS_PARAVIRT) 34 #include <rtems/score/paravirt.h> 44 #if defined(ARM_MULTILIB_ARCH_V4) 46 #if defined(__thumb__) && !defined(__thumb2__) 47 #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg 48 #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n" 49 #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n" 50 #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg) 51 #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT 53 #define ARM_SWITCH_REGISTERS 54 #define ARM_SWITCH_TO_ARM 55 #define ARM_SWITCH_BACK 56 #define ARM_SWITCH_OUTPUT 57 #define ARM_SWITCH_ADDITIONAL_OUTPUT 65 #define ARM_PSR_N (1 << 31) 66 #define ARM_PSR_Z (1 << 30) 67 #define ARM_PSR_C (1 << 29) 68 #define ARM_PSR_V (1 << 28) 69 #define ARM_PSR_Q (1 << 27) 70 #define ARM_PSR_J (1 << 24) 71 #define ARM_PSR_GE_SHIFT 16 72 #define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT) 73 #define ARM_PSR_E (1 << 9) 74 #define ARM_PSR_A (1 << 8) 75 #define ARM_PSR_I (1 << 7) 76 #define ARM_PSR_F (1 << 6) 77 #define ARM_PSR_T (1 << 5) 78 #define ARM_PSR_M_SHIFT 0 79 #define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT) 80 #define ARM_PSR_M_USR 0x10 81 #define ARM_PSR_M_FIQ 0x11 82 #define ARM_PSR_M_IRQ 0x12 83 #define ARM_PSR_M_SVC 0x13 84 #define ARM_PSR_M_ABT 0x17 85 #define ARM_PSR_M_HYP 0x1a 86 #define ARM_PSR_M_UND 0x1b 87 #define ARM_PSR_M_SYS 0x1f 96 #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE 98 #define CPU_ISR_PASSES_FRAME_POINTER FALSE 100 #define CPU_HARDWARE_FP FALSE 102 #define CPU_SOFTWARE_FP FALSE 104 #define CPU_ALL_TASKS_ARE_FP FALSE 106 #define CPU_IDLE_TASK_IS_FP FALSE 108 #define CPU_USE_DEFERRED_FP_SWITCH FALSE 110 #define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE 112 #define CPU_STACK_GROWS_UP FALSE 114 #if defined(ARM_MULTILIB_CACHE_LINE_MAX_64) 115 #define CPU_CACHE_LINE_BYTES 64 117 #define CPU_CACHE_LINE_BYTES 32 120 #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) 122 #define CPU_MODES_INTERRUPT_MASK 0x1 124 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) 126 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 128 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE 130 #define CPU_STACK_MINIMUM_SIZE (1024 * 4) 133 #define CPU_SIZEOF_POINTER 4 136 #define CPU_ALIGNMENT 8 138 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT 141 #define CPU_STACK_ALIGNMENT 8 143 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 156 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE 158 #define CPU_MAXIMUM_PROCESSORS 32 160 #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER 161 #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44 164 #ifdef ARM_MULTILIB_VFP 165 #define ARM_CONTEXT_CONTROL_D8_OFFSET 48 168 #ifdef ARM_MULTILIB_ARCH_V4 169 #define ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 40 173 #if defined(ARM_MULTILIB_VFP) 174 #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112 175 #elif defined(ARM_MULTILIB_HAS_THREAD_ID_REGISTER) 176 #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48 178 #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 44 182 #define ARM_EXCEPTION_FRAME_SIZE 80 184 #define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52 186 #define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72 188 #define ARM_VFP_CONTEXT_SIZE 264 197 #if defined(ARM_MULTILIB_ARCH_V4) 198 uint32_t register_r4;
199 uint32_t register_r5;
200 uint32_t register_r6;
201 uint32_t register_r7;
202 uint32_t register_r8;
203 uint32_t register_r9;
204 uint32_t register_r10;
205 uint32_t register_fp;
206 uint32_t register_sp;
207 uint32_t register_lr;
208 uint32_t isr_dispatch_disable;
209 #elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M) 210 uint32_t register_r4;
211 uint32_t register_r5;
212 uint32_t register_r6;
213 uint32_t register_r7;
214 uint32_t register_r8;
215 uint32_t register_r9;
216 uint32_t register_r10;
217 uint32_t register_r11;
220 uint32_t isr_nest_level;
224 #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER 227 #ifdef ARM_MULTILIB_VFP 228 uint64_t register_d8;
229 uint64_t register_d9;
230 uint64_t register_d10;
231 uint64_t register_d11;
232 uint64_t register_d12;
233 uint64_t register_d13;
234 uint64_t register_d14;
235 uint64_t register_d15;
238 volatile bool is_executing;
246 static inline void _ARM_Data_memory_barrier(
void )
248 #ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS 249 __asm__ volatile (
"dmb" : : :
"memory" );
255 static inline void _ARM_Data_synchronization_barrier(
void )
257 #ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS 258 __asm__ volatile (
"dsb" : : :
"memory" );
264 static inline void _ARM_Instruction_synchronization_barrier(
void )
266 #ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS 267 __asm__ volatile (
"isb" : : :
"memory" );
273 #if defined(ARM_DISABLE_INLINE_ISR_DISABLE_ENABLE) 274 uint32_t arm_interrupt_disable(
void );
275 void arm_interrupt_enable( uint32_t level );
276 void arm_interrupt_flash( uint32_t level );
278 static inline uint32_t arm_interrupt_disable(
void )
282 #if defined(ARM_MULTILIB_ARCH_V4) 283 uint32_t arm_switch_reg;
301 "mrs %[level], cpsr\n" 302 "orr %[arm_switch_reg], %[level], #0x80\n" 303 "msr cpsr, %[arm_switch_reg]\n" 305 : [arm_switch_reg]
"=&r" (arm_switch_reg), [level]
"=&r" (level)
307 #elif defined(ARM_MULTILIB_ARCH_V7M) 308 uint32_t basepri = 0x80;
311 "mrs %[level], basepri\n" 312 "msr basepri_max, %[basepri]\n" 313 : [level]
"=&r" (level)
314 : [basepri]
"r" (basepri)
321 static inline void arm_interrupt_enable( uint32_t level )
323 #if defined(ARM_MULTILIB_ARCH_V4) 324 ARM_SWITCH_REGISTERS;
328 "msr cpsr, %[level]\n" 331 : [level]
"r" (level)
333 #elif defined(ARM_MULTILIB_ARCH_V7M) 335 "msr basepri, %[level]\n" 337 : [level]
"r" (level)
342 static inline void arm_interrupt_flash( uint32_t level )
344 #if defined(ARM_MULTILIB_ARCH_V4) 345 uint32_t arm_switch_reg;
349 "mrs %[arm_switch_reg], cpsr\n" 350 "msr cpsr, %[level]\n" 351 "msr cpsr, %[arm_switch_reg]\n" 353 : [arm_switch_reg]
"=&r" (arm_switch_reg)
354 : [level]
"r" (level)
356 #elif defined(ARM_MULTILIB_ARCH_V7M) 360 "mrs %[basepri], basepri\n" 361 "msr basepri, %[level]\n" 362 "msr basepri, %[basepri]\n" 363 : [basepri]
"=&r" (basepri)
364 : [level]
"r" (level)
370 #define _CPU_ISR_Disable( _isr_cookie ) \ 372 _isr_cookie = arm_interrupt_disable(); \ 375 #define _CPU_ISR_Enable( _isr_cookie ) \ 376 arm_interrupt_enable( _isr_cookie ) 378 #define _CPU_ISR_Flash( _isr_cookie ) \ 379 arm_interrupt_flash( _isr_cookie ) 383 #if defined(ARM_MULTILIB_ARCH_V4) 384 return ( level & 0x80 ) == 0;
385 #elif defined(ARM_MULTILIB_ARCH_V7M) 396 void *stack_area_begin,
397 size_t stack_area_size,
399 void (*entry_point)(
void ),
404 #define _CPU_Context_Get_SP( _context ) \ 405 (_context)->register_sp 408 static inline bool _CPU_Context_Get_is_executing(
412 return context->is_executing;
415 static inline void _CPU_Context_Set_is_executing(
420 context->is_executing = is_executing;
424 #define _CPU_Context_Restart_self( _the_context ) \ 425 _CPU_Context_restore( (_the_context) ); 427 #define _CPU_Context_Initialize_fp( _destination ) \ 429 *(*(_destination)) = _CPU_Null_fp_context; \ 432 #define _CPU_Fatal_halt( _source, _err ) \ 435 uint32_t _error = _err; \ 436 _CPU_ISR_Disable( _level ); \ 438 __asm__ volatile ("mov r0, %0\n" \ 450 typedef void ( *CPU_ISR_handler )( void );
454 CPU_ISR_handler new_handler,
455 CPU_ISR_handler *old_handler
466 #if defined(ARM_MULTILIB_ARCH_V7M) 469 #define _CPU_Start_multitasking _ARMV7M_Start_multitasking 473 uint32_t _CPU_SMP_Initialize(
void );
475 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
477 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
479 void _CPU_SMP_Prepare_start_multitasking(
void );
481 static inline uint32_t _CPU_SMP_Get_current_processor(
void )
487 "mrc p15, 0, %[mpidr], c0, c0, 5\n" 488 : [mpidr]
"=&r" (mpidr)
491 return mpidr & 0xffU;
494 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
496 static inline void _ARM_Send_event(
void )
498 __asm__ volatile (
"sev" : : :
"memory" );
501 static inline void _ARM_Wait_for_event(
void )
503 __asm__ volatile (
"wfe" : : :
"memory" );
506 static inline void _CPU_SMP_Processor_event_broadcast(
void )
508 _ARM_Data_synchronization_barrier();
512 static inline void _CPU_SMP_Processor_event_receive(
void )
514 _ARM_Wait_for_event();
515 _ARM_Data_memory_barrier();
520 static inline uint32_t CPU_swap_u32( uint32_t value )
522 #if defined(__thumb2__) 529 #elif defined(__thumb__) 530 uint32_t byte1, byte2, byte3, byte4, swapped;
532 byte4 = (value >> 24) & 0xff;
533 byte3 = (value >> 16) & 0xff;
534 byte2 = (value >> 8) & 0xff;
535 byte1 = value & 0xff;
537 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
540 uint32_t tmp = value;
541 __asm__ volatile (
"EOR %1, %0, %0, ROR #16\n" 542 "BIC %1, %1, #0xff0000\n" 543 "MOV %0, %0, ROR #8\n" 544 "EOR %0, %0, %1, LSR #8\n" 545 :
"=r" (value),
"=r" (tmp)
546 :
"0" (value),
"1" (tmp));
553 #if defined(__thumb2__) 561 return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU));
571 static inline CPU_Counter_ticks _CPU_Counter_difference(
572 CPU_Counter_ticks second,
573 CPU_Counter_ticks first
576 return second - first;
581 #if defined(ARM_MULTILIB_ARCH_V4) 584 ARM_EXCEPTION_RESET = 0,
585 ARM_EXCEPTION_UNDEF = 1,
586 ARM_EXCEPTION_SWI = 2,
587 ARM_EXCEPTION_PREF_ABORT = 3,
588 ARM_EXCEPTION_DATA_ABORT = 4,
589 ARM_EXCEPTION_RESERVED = 5,
590 ARM_EXCEPTION_IRQ = 6,
591 ARM_EXCEPTION_FIQ = 7,
593 ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff
594 } Arm_symbolic_exception_name;
599 uint32_t register_fpexc;
600 uint32_t register_fpscr;
601 uint64_t register_d0;
602 uint64_t register_d1;
603 uint64_t register_d2;
604 uint64_t register_d3;
605 uint64_t register_d4;
606 uint64_t register_d5;
607 uint64_t register_d6;
608 uint64_t register_d7;
609 uint64_t register_d8;
610 uint64_t register_d9;
611 uint64_t register_d10;
612 uint64_t register_d11;
613 uint64_t register_d12;
614 uint64_t register_d13;
615 uint64_t register_d14;
616 uint64_t register_d15;
617 uint64_t register_d16;
618 uint64_t register_d17;
619 uint64_t register_d18;
620 uint64_t register_d19;
621 uint64_t register_d20;
622 uint64_t register_d21;
623 uint64_t register_d22;
624 uint64_t register_d23;
625 uint64_t register_d24;
626 uint64_t register_d25;
627 uint64_t register_d26;
628 uint64_t register_d27;
629 uint64_t register_d28;
630 uint64_t register_d29;
631 uint64_t register_d30;
632 uint64_t register_d31;
636 uint32_t register_r0;
637 uint32_t register_r1;
638 uint32_t register_r2;
639 uint32_t register_r3;
640 uint32_t register_r4;
641 uint32_t register_r5;
642 uint32_t register_r6;
643 uint32_t register_r7;
644 uint32_t register_r8;
645 uint32_t register_r9;
646 uint32_t register_r10;
647 uint32_t register_r11;
648 uint32_t register_r12;
649 uint32_t register_sp;
652 #if defined(ARM_MULTILIB_ARCH_V4) 653 uint32_t register_cpsr;
654 Arm_symbolic_exception_name vector;
655 #elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M) 656 uint32_t register_xpsr;
660 uint32_t reserved_for_stack_alignment;
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
void _CPU_ISR_Set_level(uint32_t level)
Sets the hardware interrupt level by the level value.
Definition: cpu.c:57
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
Thread register context.
Definition: cpu.h:196
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:65
void _CPU_Context_Initialize(Context_Control *context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
Initializes the CPU context.
Definition: epiphany-context-initialize.c:40
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
#define CPU_swap_u16(value)
Definition: cpu.h:817
SPARC basic context.
Definition: cpu.h:242
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1202
#define RTEMS_NO_RETURN
Definition: basedefs.h:101
uint32_t _CPU_ISR_Get_level(void)
Definition: cpu.c:88
unsigned context
Definition: tlb.h:108
bool _CPU_ISR_Is_enabled(uint32_t level)
Returns true if interrupts are enabled in the specified ISR level, otherwise returns false...
Definition: cpu.h:381
void _CPU_Context_restore(Context_Control *new_context) RTEMS_NO_RETURN
Definition: cpu_asm.c:111
uintptr_t CPU_Uint32ptr
Definition: cpu.h:668
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
SPARC specific RTEMS ISR installer.
Definition: cpu.h:605
The set of registers that specifies the complete processor state.
Definition: cpu.h:635
ARM Assembler Support API.
#define RTEMS_COMPILER_MEMORY_BARRIER()
Definition: basedefs.h:76