RTEMS  5.0.0
cpu.h
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1 
7 /*
8  * This include file contains information pertaining to the ARM
9  * processor.
10  *
11  * Copyright (c) 2009, 2017 embedded brains GmbH
12  *
13  * Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com>
14  *
15  * Copyright (c) 2006 OAR Corporation
16  *
17  * Copyright (c) 2002 Advent Networks, Inc.
18  * Jay Monkman <jmonkman@adventnetworks.com>
19  *
20  * COPYRIGHT (c) 2000 Canon Research Centre France SA.
21  * Emmanuel Raguet, mailto:raguet@crf.canon.fr
22  *
23  * The license and distribution terms for this file may be
24  * found in the file LICENSE in this distribution or at
25  * http://www.rtems.org/license/LICENSE.
26  *
27  */
28 
29 #ifndef _RTEMS_SCORE_CPU_H
30 #define _RTEMS_SCORE_CPU_H
31 
32 #include <rtems/score/basedefs.h>
33 #if defined(RTEMS_PARAVIRT)
34 #include <rtems/score/paravirt.h>
35 #endif
36 #include <rtems/score/arm.h>
37 
44 #if defined(ARM_MULTILIB_ARCH_V4)
45 
46 #if defined(__thumb__) && !defined(__thumb2__)
47  #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg
48  #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n"
49  #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n"
50  #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg)
51  #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT
52 #else
53  #define ARM_SWITCH_REGISTERS
54  #define ARM_SWITCH_TO_ARM
55  #define ARM_SWITCH_BACK
56  #define ARM_SWITCH_OUTPUT
57  #define ARM_SWITCH_ADDITIONAL_OUTPUT
58 #endif
59 
65 #define ARM_PSR_N (1 << 31)
66 #define ARM_PSR_Z (1 << 30)
67 #define ARM_PSR_C (1 << 29)
68 #define ARM_PSR_V (1 << 28)
69 #define ARM_PSR_Q (1 << 27)
70 #define ARM_PSR_J (1 << 24)
71 #define ARM_PSR_GE_SHIFT 16
72 #define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT)
73 #define ARM_PSR_E (1 << 9)
74 #define ARM_PSR_A (1 << 8)
75 #define ARM_PSR_I (1 << 7)
76 #define ARM_PSR_F (1 << 6)
77 #define ARM_PSR_T (1 << 5)
78 #define ARM_PSR_M_SHIFT 0
79 #define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT)
80 #define ARM_PSR_M_USR 0x10
81 #define ARM_PSR_M_FIQ 0x11
82 #define ARM_PSR_M_IRQ 0x12
83 #define ARM_PSR_M_SVC 0x13
84 #define ARM_PSR_M_ABT 0x17
85 #define ARM_PSR_M_HYP 0x1a
86 #define ARM_PSR_M_UND 0x1b
87 #define ARM_PSR_M_SYS 0x1f
88 
91 #endif /* defined(ARM_MULTILIB_ARCH_V4) */
92 
93 /*
94  * The ARM uses the PIC interrupt model.
95  */
96 #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
97 
98 #define CPU_ISR_PASSES_FRAME_POINTER FALSE
99 
100 #define CPU_HARDWARE_FP FALSE
101 
102 #define CPU_SOFTWARE_FP FALSE
103 
104 #define CPU_ALL_TASKS_ARE_FP FALSE
105 
106 #define CPU_IDLE_TASK_IS_FP FALSE
107 
108 #define CPU_USE_DEFERRED_FP_SWITCH FALSE
109 
110 #define CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE
111 
112 #define CPU_STACK_GROWS_UP FALSE
113 
114 #if defined(ARM_MULTILIB_CACHE_LINE_MAX_64)
115  #define CPU_CACHE_LINE_BYTES 64
116 #else
117  #define CPU_CACHE_LINE_BYTES 32
118 #endif
119 
120 #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
121 
122 #define CPU_MODES_INTERRUPT_MASK 0x1
123 
124 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
125 
126 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
127 
128 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
129 
130 #define CPU_STACK_MINIMUM_SIZE (1024 * 4)
131 
132 /* AAPCS, section 4.1, Fundamental Data Types */
133 #define CPU_SIZEOF_POINTER 4
134 
135 /* AAPCS, section 4.1, Fundamental Data Types */
136 #define CPU_ALIGNMENT 8
137 
138 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
139 
140 /* AAPCS, section 5.2.1.2, Stack constraints at a public interface */
141 #define CPU_STACK_ALIGNMENT 8
142 
143 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
144 
145 /*
146  * Bitfield handler macros.
147  *
148  * If we had a particularly fast function for finding the first
149  * bit set in a word, it would go here. Since we don't (*), we'll
150  * just use the universal macros.
151  *
152  * (*) On ARM V5 and later, there's a CLZ function which could be
153  * used to implement much quicker than the default macro.
154  */
155 
156 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
157 
158 #define CPU_MAXIMUM_PROCESSORS 32
159 
160 #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
161  #define ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET 44
162 #endif
163 
164 #ifdef ARM_MULTILIB_VFP
165  #define ARM_CONTEXT_CONTROL_D8_OFFSET 48
166 #endif
167 
168 #ifdef ARM_MULTILIB_ARCH_V4
169  #define ARM_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 40
170 #endif
171 
172 #ifdef RTEMS_SMP
173  #if defined(ARM_MULTILIB_VFP)
174  #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112
175  #elif defined(ARM_MULTILIB_HAS_THREAD_ID_REGISTER)
176  #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 48
177  #else
178  #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 44
179  #endif
180 #endif
181 
182 #define ARM_EXCEPTION_FRAME_SIZE 80
183 
184 #define ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52
185 
186 #define ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72
187 
188 #define ARM_VFP_CONTEXT_SIZE 264
189 
190 #ifndef ASM
191 
192 #ifdef __cplusplus
193 extern "C" {
194 #endif
195 
196 typedef struct {
197 #if defined(ARM_MULTILIB_ARCH_V4)
198  uint32_t register_r4;
199  uint32_t register_r5;
200  uint32_t register_r6;
201  uint32_t register_r7;
202  uint32_t register_r8;
203  uint32_t register_r9;
204  uint32_t register_r10;
205  uint32_t register_fp;
206  uint32_t register_sp;
207  uint32_t register_lr;
208  uint32_t isr_dispatch_disable;
209 #elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M)
210  uint32_t register_r4;
211  uint32_t register_r5;
212  uint32_t register_r6;
213  uint32_t register_r7;
214  uint32_t register_r8;
215  uint32_t register_r9;
216  uint32_t register_r10;
217  uint32_t register_r11;
218  void *register_lr;
219  void *register_sp;
220  uint32_t isr_nest_level;
221 #else
222  void *register_sp;
223 #endif
224 #ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
225  uint32_t thread_id;
226 #endif
227 #ifdef ARM_MULTILIB_VFP
228  uint64_t register_d8;
229  uint64_t register_d9;
230  uint64_t register_d10;
231  uint64_t register_d11;
232  uint64_t register_d12;
233  uint64_t register_d13;
234  uint64_t register_d14;
235  uint64_t register_d15;
236 #endif
237 #ifdef RTEMS_SMP
238  volatile bool is_executing;
239 #endif
241 
242 typedef struct {
243  /* Not supported */
245 
246 static inline void _ARM_Data_memory_barrier( void )
247 {
248 #ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
249  __asm__ volatile ( "dmb" : : : "memory" );
250 #else
252 #endif
253 }
254 
255 static inline void _ARM_Data_synchronization_barrier( void )
256 {
257 #ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
258  __asm__ volatile ( "dsb" : : : "memory" );
259 #else
261 #endif
262 }
263 
264 static inline void _ARM_Instruction_synchronization_barrier( void )
265 {
266 #ifdef ARM_MULTILIB_HAS_BARRIER_INSTRUCTIONS
267  __asm__ volatile ( "isb" : : : "memory" );
268 #else
270 #endif
271 }
272 
273 #if defined(ARM_DISABLE_INLINE_ISR_DISABLE_ENABLE)
274 uint32_t arm_interrupt_disable( void );
275 void arm_interrupt_enable( uint32_t level );
276 void arm_interrupt_flash( uint32_t level );
277 #else
278 static inline uint32_t arm_interrupt_disable( void )
279 {
280  uint32_t level;
281 
282 #if defined(ARM_MULTILIB_ARCH_V4)
283  uint32_t arm_switch_reg;
284 
285  /*
286  * Disable only normal interrupts (IRQ).
287  *
288  * In order to support fast interrupts (FIQ) such that they can do something
289  * useful, we have to disable the operating system support for FIQs. Having
290  * operating system support for them would require that FIQs are disabled
291  * during critical sections of the operating system and application. At this
292  * level IRQs and FIQs would be equal. It is true that FIQs could interrupt
293  * the non critical sections of IRQs, so here they would have a small
294  * advantage. Without operating system support, the FIQs can execute at any
295  * time (of course not during the service of another FIQ). If someone needs
296  * operating system support for a FIQ, she can trigger a software interrupt and
297  * service the request in a two-step process.
298  */
299  __asm__ volatile (
300  ARM_SWITCH_TO_ARM
301  "mrs %[level], cpsr\n"
302  "orr %[arm_switch_reg], %[level], #0x80\n"
303  "msr cpsr, %[arm_switch_reg]\n"
304  ARM_SWITCH_BACK
305  : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level)
306  );
307 #elif defined(ARM_MULTILIB_ARCH_V7M)
308  uint32_t basepri = 0x80;
309 
310  __asm__ volatile (
311  "mrs %[level], basepri\n"
312  "msr basepri_max, %[basepri]\n"
313  : [level] "=&r" (level)
314  : [basepri] "r" (basepri)
315  );
316 #endif
317 
318  return level;
319 }
320 
321 static inline void arm_interrupt_enable( uint32_t level )
322 {
323 #if defined(ARM_MULTILIB_ARCH_V4)
324  ARM_SWITCH_REGISTERS;
325 
326  __asm__ volatile (
327  ARM_SWITCH_TO_ARM
328  "msr cpsr, %[level]\n"
329  ARM_SWITCH_BACK
330  : ARM_SWITCH_OUTPUT
331  : [level] "r" (level)
332  );
333 #elif defined(ARM_MULTILIB_ARCH_V7M)
334  __asm__ volatile (
335  "msr basepri, %[level]\n"
336  :
337  : [level] "r" (level)
338  );
339 #endif
340 }
341 
342 static inline void arm_interrupt_flash( uint32_t level )
343 {
344 #if defined(ARM_MULTILIB_ARCH_V4)
345  uint32_t arm_switch_reg;
346 
347  __asm__ volatile (
348  ARM_SWITCH_TO_ARM
349  "mrs %[arm_switch_reg], cpsr\n"
350  "msr cpsr, %[level]\n"
351  "msr cpsr, %[arm_switch_reg]\n"
352  ARM_SWITCH_BACK
353  : [arm_switch_reg] "=&r" (arm_switch_reg)
354  : [level] "r" (level)
355  );
356 #elif defined(ARM_MULTILIB_ARCH_V7M)
357  uint32_t basepri;
358 
359  __asm__ volatile (
360  "mrs %[basepri], basepri\n"
361  "msr basepri, %[level]\n"
362  "msr basepri, %[basepri]\n"
363  : [basepri] "=&r" (basepri)
364  : [level] "r" (level)
365  );
366 #endif
367 }
368 #endif /* !ARM_DISABLE_INLINE_ISR_DISABLE_ENABLE */
369 
370 #define _CPU_ISR_Disable( _isr_cookie ) \
371  do { \
372  _isr_cookie = arm_interrupt_disable(); \
373  } while (0)
374 
375 #define _CPU_ISR_Enable( _isr_cookie ) \
376  arm_interrupt_enable( _isr_cookie )
377 
378 #define _CPU_ISR_Flash( _isr_cookie ) \
379  arm_interrupt_flash( _isr_cookie )
380 
382 {
383 #if defined(ARM_MULTILIB_ARCH_V4)
384  return ( level & 0x80 ) == 0;
385 #elif defined(ARM_MULTILIB_ARCH_V7M)
386  return level == 0;
387 #endif
388 }
389 
390 void _CPU_ISR_Set_level( uint32_t level );
391 
392 uint32_t _CPU_ISR_Get_level( void );
393 
395  Context_Control *the_context,
396  void *stack_area_begin,
397  size_t stack_area_size,
398  uint32_t new_level,
399  void (*entry_point)( void ),
400  bool is_fp,
401  void *tls_area
402 );
403 
404 #define _CPU_Context_Get_SP( _context ) \
405  (_context)->register_sp
406 
407 #ifdef RTEMS_SMP
408  static inline bool _CPU_Context_Get_is_executing(
409  const Context_Control *context
410  )
411  {
412  return context->is_executing;
413  }
414 
415  static inline void _CPU_Context_Set_is_executing(
416  Context_Control *context,
417  bool is_executing
418  )
419  {
420  context->is_executing = is_executing;
421  }
422 #endif
423 
424 #define _CPU_Context_Restart_self( _the_context ) \
425  _CPU_Context_restore( (_the_context) );
426 
427 #define _CPU_Context_Initialize_fp( _destination ) \
428  do { \
429  *(*(_destination)) = _CPU_Null_fp_context; \
430  } while (0)
431 
432 #define _CPU_Fatal_halt( _source, _err ) \
433  do { \
434  uint32_t _level; \
435  uint32_t _error = _err; \
436  _CPU_ISR_Disable( _level ); \
437  (void) _level; \
438  __asm__ volatile ("mov r0, %0\n" \
439  : "=r" (_error) \
440  : "0" (_error) \
441  : "r0" ); \
442  while (1); \
443  } while (0);
444 
448 void _CPU_Initialize( void );
449 
450 typedef void ( *CPU_ISR_handler )( void );
451 
453  uint32_t vector,
454  CPU_ISR_handler new_handler,
455  CPU_ISR_handler *old_handler
456 );
457 
462 
463 void _CPU_Context_restore( Context_Control *new_context )
465 
466 #if defined(ARM_MULTILIB_ARCH_V7M)
467  void _ARMV7M_Start_multitasking( Context_Control *heir )
469  #define _CPU_Start_multitasking _ARMV7M_Start_multitasking
470 #endif
471 
472 #ifdef RTEMS_SMP
473  uint32_t _CPU_SMP_Initialize( void );
474 
475  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
476 
477  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
478 
479  void _CPU_SMP_Prepare_start_multitasking( void );
480 
481  static inline uint32_t _CPU_SMP_Get_current_processor( void )
482  {
483  uint32_t mpidr;
484 
485  /* Use ARMv7 Multiprocessor Affinity Register (MPIDR) */
486  __asm__ volatile (
487  "mrc p15, 0, %[mpidr], c0, c0, 5\n"
488  : [mpidr] "=&r" (mpidr)
489  );
490 
491  return mpidr & 0xffU;
492  }
493 
494  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
495 
496  static inline void _ARM_Send_event( void )
497  {
498  __asm__ volatile ( "sev" : : : "memory" );
499  }
500 
501  static inline void _ARM_Wait_for_event( void )
502  {
503  __asm__ volatile ( "wfe" : : : "memory" );
504  }
505 
506  static inline void _CPU_SMP_Processor_event_broadcast( void )
507  {
508  _ARM_Data_synchronization_barrier();
509  _ARM_Send_event();
510  }
511 
512  static inline void _CPU_SMP_Processor_event_receive( void )
513  {
514  _ARM_Wait_for_event();
515  _ARM_Data_memory_barrier();
516  }
517 #endif
518 
519 
520 static inline uint32_t CPU_swap_u32( uint32_t value )
521 {
522 #if defined(__thumb2__)
523  __asm__ volatile (
524  "rev %0, %0"
525  : "=r" (value)
526  : "0" (value)
527  );
528  return value;
529 #elif defined(__thumb__)
530  uint32_t byte1, byte2, byte3, byte4, swapped;
531 
532  byte4 = (value >> 24) & 0xff;
533  byte3 = (value >> 16) & 0xff;
534  byte2 = (value >> 8) & 0xff;
535  byte1 = value & 0xff;
536 
537  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
538  return swapped;
539 #else
540  uint32_t tmp = value; /* make compiler warnings go away */
541  __asm__ volatile ("EOR %1, %0, %0, ROR #16\n"
542  "BIC %1, %1, #0xff0000\n"
543  "MOV %0, %0, ROR #8\n"
544  "EOR %0, %0, %1, LSR #8\n"
545  : "=r" (value), "=r" (tmp)
546  : "0" (value), "1" (tmp));
547  return value;
548 #endif
549 }
550 
551 static inline uint16_t CPU_swap_u16( uint16_t value )
552 {
553 #if defined(__thumb2__)
554  __asm__ volatile (
555  "rev16 %0, %0"
556  : "=r" (value)
557  : "0" (value)
558  );
559  return value;
560 #else
561  return (uint16_t) (((value & 0xffU) << 8) | ((value >> 8) & 0xffU));
562 #endif
563 }
564 
565 typedef uint32_t CPU_Counter_ticks;
566 
567 uint32_t _CPU_Counter_frequency( void );
568 
569 CPU_Counter_ticks _CPU_Counter_read( void );
570 
571 static inline CPU_Counter_ticks _CPU_Counter_difference(
572  CPU_Counter_ticks second,
573  CPU_Counter_ticks first
574 )
575 {
576  return second - first;
577 }
578 
579 void *_CPU_Thread_Idle_body( uintptr_t ignored );
580 
581 #if defined(ARM_MULTILIB_ARCH_V4)
582 
583 typedef enum {
584  ARM_EXCEPTION_RESET = 0,
585  ARM_EXCEPTION_UNDEF = 1,
586  ARM_EXCEPTION_SWI = 2,
587  ARM_EXCEPTION_PREF_ABORT = 3,
588  ARM_EXCEPTION_DATA_ABORT = 4,
589  ARM_EXCEPTION_RESERVED = 5,
590  ARM_EXCEPTION_IRQ = 6,
591  ARM_EXCEPTION_FIQ = 7,
592  MAX_EXCEPTIONS = 8,
593  ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff
594 } Arm_symbolic_exception_name;
595 
596 #endif /* defined(ARM_MULTILIB_ARCH_V4) */
597 
598 typedef struct {
599  uint32_t register_fpexc;
600  uint32_t register_fpscr;
601  uint64_t register_d0;
602  uint64_t register_d1;
603  uint64_t register_d2;
604  uint64_t register_d3;
605  uint64_t register_d4;
606  uint64_t register_d5;
607  uint64_t register_d6;
608  uint64_t register_d7;
609  uint64_t register_d8;
610  uint64_t register_d9;
611  uint64_t register_d10;
612  uint64_t register_d11;
613  uint64_t register_d12;
614  uint64_t register_d13;
615  uint64_t register_d14;
616  uint64_t register_d15;
617  uint64_t register_d16;
618  uint64_t register_d17;
619  uint64_t register_d18;
620  uint64_t register_d19;
621  uint64_t register_d20;
622  uint64_t register_d21;
623  uint64_t register_d22;
624  uint64_t register_d23;
625  uint64_t register_d24;
626  uint64_t register_d25;
627  uint64_t register_d26;
628  uint64_t register_d27;
629  uint64_t register_d28;
630  uint64_t register_d29;
631  uint64_t register_d30;
632  uint64_t register_d31;
634 
635 typedef struct {
636  uint32_t register_r0;
637  uint32_t register_r1;
638  uint32_t register_r2;
639  uint32_t register_r3;
640  uint32_t register_r4;
641  uint32_t register_r5;
642  uint32_t register_r6;
643  uint32_t register_r7;
644  uint32_t register_r8;
645  uint32_t register_r9;
646  uint32_t register_r10;
647  uint32_t register_r11;
648  uint32_t register_r12;
649  uint32_t register_sp;
650  void *register_lr;
651  void *register_pc;
652 #if defined(ARM_MULTILIB_ARCH_V4)
653  uint32_t register_cpsr;
654  Arm_symbolic_exception_name vector;
655 #elif defined(ARM_MULTILIB_ARCH_V6M) || defined(ARM_MULTILIB_ARCH_V7M)
656  uint32_t register_xpsr;
657  uint32_t vector;
658 #endif
659  const ARM_VFP_context *vfp_context;
660  uint32_t reserved_for_stack_alignment;
662 
664 
665 void _ARM_Exception_default( CPU_Exception_frame *frame );
666 
668 typedef uintptr_t CPU_Uint32ptr;
669 
670 #ifdef __cplusplus
671 }
672 #endif
673 
674 #endif /* ASM */
675 
678 #endif /* _RTEMS_SCORE_CPU_H */
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
void _CPU_ISR_Set_level(uint32_t level)
Sets the hardware interrupt level by the level value.
Definition: cpu.c:57
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
Thread register context.
Definition: cpu.h:196
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:65
void _CPU_Context_Initialize(Context_Control *context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
Initializes the CPU context.
Definition: epiphany-context-initialize.c:40
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
#define CPU_swap_u16(value)
Definition: cpu.h:817
SPARC basic context.
Definition: cpu.h:242
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1202
#define RTEMS_NO_RETURN
Definition: basedefs.h:101
uint32_t _CPU_ISR_Get_level(void)
Definition: cpu.c:88
unsigned context
Definition: tlb.h:108
bool _CPU_ISR_Is_enabled(uint32_t level)
Returns true if interrupts are enabled in the specified ISR level, otherwise returns false...
Definition: cpu.h:381
void _CPU_Context_restore(Context_Control *new_context) RTEMS_NO_RETURN
Definition: cpu_asm.c:111
uintptr_t CPU_Uint32ptr
Definition: cpu.h:668
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
Basic Definitions.
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
SPARC specific RTEMS ISR installer.
Definition: cpu.h:605
The set of registers that specifies the complete processor state.
Definition: cpu.h:635
Definition: cpu.h:598
ARM Assembler Support API.
#define RTEMS_COMPILER_MEMORY_BARRIER()
Definition: basedefs.h:76