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#define | CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
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#define | CPU_ISR_PASSES_FRAME_POINTER FALSE |
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#define | CPU_HARDWARE_FP FALSE |
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#define | CPU_SOFTWARE_FP FALSE |
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#define | CPU_ALL_TASKS_ARE_FP FALSE |
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#define | CPU_IDLE_TASK_IS_FP FALSE |
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#define | CPU_USE_DEFERRED_FP_SWITCH FALSE |
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#define | CPU_ENABLE_ROBUST_THREAD_DISPATCH TRUE |
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#define | CPU_STACK_GROWS_UP FALSE |
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#define | CPU_CACHE_LINE_BYTES 32 |
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#define | CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |
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#define | CPU_MODES_INTERRUPT_MASK 0x1 |
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#define | CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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#define | CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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#define | CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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#define | CPU_STACK_MINIMUM_SIZE (1024 * 4) |
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#define | CPU_SIZEOF_POINTER 4 |
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#define | CPU_ALIGNMENT 8 |
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#define | CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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#define | CPU_STACK_ALIGNMENT 8 |
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#define | CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
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#define | CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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#define | CPU_MAXIMUM_PROCESSORS 32 |
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#define | ARM_EXCEPTION_FRAME_SIZE 80 |
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#define | ARM_EXCEPTION_FRAME_REGISTER_SP_OFFSET 52 |
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#define | ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET 72 |
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#define | ARM_VFP_CONTEXT_SIZE 264 |
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#define | _CPU_ISR_Disable(_isr_cookie) |
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#define | _CPU_ISR_Enable(_isr_cookie) arm_interrupt_enable( _isr_cookie ) |
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#define | _CPU_ISR_Flash(_isr_cookie) arm_interrupt_flash( _isr_cookie ) |
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#define | _CPU_Context_Get_SP(_context) (_context)->register_sp |
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#define | _CPU_Context_Restart_self(_the_context) _CPU_Context_restore( (_the_context) ); |
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#define | _CPU_Context_Initialize_fp(_destination) |
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#define | _CPU_Fatal_halt(_source, _err) |
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ARM Architecture Support API.