GPC_CPU_MODE_CTRL Peripheral Access Layer

Modules
	GPC_CPU_MODE_CTRL Register Masks

Data Structures
struct	GPC_CPU_MODE_CTRL_Type

Macros
#define	GPC_CPU_MODE_CTRL_0_BASE   (0x40C00000u)
#define	GPC_CPU_MODE_CTRL_0   ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_0_BASE)
#define	GPC_CPU_MODE_CTRL_1_BASE   (0x40C00800u)
#define	GPC_CPU_MODE_CTRL_1   ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
#define	GPC_CPU_MODE_CTRL_BASE_ADDRS   { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
#define	GPC_CPU_MODE_CTRL_BASE_PTRS   { GPC_CPU_MODE_CTRL_0, GPC_CPU_MODE_CTRL_1 }
#define	GPC_CPU_MODE_CTRL_0_BASE   (0x40C00000u)
#define	GPC_CPU_MODE_CTRL_0   ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_0_BASE)
#define	GPC_CPU_MODE_CTRL_1_BASE   (0x40C00800u)
#define	GPC_CPU_MODE_CTRL_1   ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
#define	GPC_CPU_MODE_CTRL_BASE_ADDRS   { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
#define	GPC_CPU_MODE_CTRL_BASE_PTRS   { GPC_CPU_MODE_CTRL_0, GPC_CPU_MODE_CTRL_1 }

Detailed Description

Macro Definition Documentation

GPC_CPU_MODE_CTRL_0 [1/2]

#define GPC_CPU_MODE_CTRL_0   ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_0_BASE)

Peripheral GPC_CPU_MODE_CTRL_0 base pointer

GPC_CPU_MODE_CTRL_0 [2/2]

#define GPC_CPU_MODE_CTRL_0   ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_0_BASE)

Peripheral GPC_CPU_MODE_CTRL_0 base pointer

GPC_CPU_MODE_CTRL_0_BASE [1/2]

#define GPC_CPU_MODE_CTRL_0_BASE   (0x40C00000u)

Peripheral GPC_CPU_MODE_CTRL_0 base address

GPC_CPU_MODE_CTRL_0_BASE [2/2]

#define GPC_CPU_MODE_CTRL_0_BASE   (0x40C00000u)

Peripheral GPC_CPU_MODE_CTRL_0 base address

GPC_CPU_MODE_CTRL_1 [1/2]

#define GPC_CPU_MODE_CTRL_1   ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)

Peripheral GPC_CPU_MODE_CTRL_1 base pointer

GPC_CPU_MODE_CTRL_1 [2/2]

#define GPC_CPU_MODE_CTRL_1   ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)

Peripheral GPC_CPU_MODE_CTRL_1 base pointer

GPC_CPU_MODE_CTRL_1_BASE [1/2]

#define GPC_CPU_MODE_CTRL_1_BASE   (0x40C00800u)

Peripheral GPC_CPU_MODE_CTRL_1 base address

GPC_CPU_MODE_CTRL_1_BASE [2/2]

#define GPC_CPU_MODE_CTRL_1_BASE   (0x40C00800u)

Peripheral GPC_CPU_MODE_CTRL_1 base address

GPC_CPU_MODE_CTRL_BASE_ADDRS [1/2]

#define GPC_CPU_MODE_CTRL_BASE_ADDRS   { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }

Array initializer of GPC_CPU_MODE_CTRL peripheral base addresses

GPC_CPU_MODE_CTRL_BASE_ADDRS [2/2]

#define GPC_CPU_MODE_CTRL_BASE_ADDRS   { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }

Array initializer of GPC_CPU_MODE_CTRL peripheral base addresses

GPC_CPU_MODE_CTRL_BASE_PTRS [1/2]

#define GPC_CPU_MODE_CTRL_BASE_PTRS   { GPC_CPU_MODE_CTRL_0, GPC_CPU_MODE_CTRL_1 }

Array initializer of GPC_CPU_MODE_CTRL peripheral base pointers

GPC_CPU_MODE_CTRL_BASE_PTRS [2/2]

#define GPC_CPU_MODE_CTRL_BASE_PTRS   { GPC_CPU_MODE_CTRL_0, GPC_CPU_MODE_CTRL_1 }

Array initializer of GPC_CPU_MODE_CTRL peripheral base pointers