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RTEMS 5.2
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Go to the source code of this file.
Data Structures | |
struct | Context_Control |
Thread register context. More... | |
struct | Context_Control_fp |
SPARC basic context. More... | |
struct | CPU_Interrupt_frame |
Interrupt stack frame (ISF). More... | |
Macros | |
#define | CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
#define | CPU_ISR_PASSES_FRAME_POINTER FALSE |
#define | CPU_SOFTWARE_FP FALSE |
#define | CPU_HARDWARE_FP FALSE |
#define | CPU_ALL_TASKS_ARE_FP FALSE |
#define | CPU_IDLE_TASK_IS_FP FALSE |
#define | CPU_USE_DEFERRED_FP_SWITCH TRUE |
#define | CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
#define | CPU_STACK_GROWS_UP FALSE |
#define | CPU_CACHE_LINE_BYTES 16 |
#define | CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |
#define | CPU_MODES_INTERRUPT_MASK 0x0000000f |
#define | CPU_MAXIMUM_PROCESSORS 32 |
#define | _CPU_Context_Get_SP(_context) (_context)->r15 |
#define | CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
#define | CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
#define | CPU_INTERRUPT_NUMBER_OF_VECTORS 256 |
#define | CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
#define | CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
#define | CPU_STACK_MINIMUM_SIZE 4096 |
#define | CPU_SIZEOF_POINTER 4 |
#define | CPU_ALIGNMENT 4 |
#define | CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
#define | CPU_STACK_ALIGNMENT CPU_ALIGNMENT |
#define | CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
#define | _CPU_Initialize_vectors() |
#define | _CPU_ISR_Disable(_level) sh_disable_interrupts( _level ) |
#define | _CPU_ISR_Enable(_level) sh_enable_interrupts( _level) |
#define | _CPU_ISR_Flash(_level) sh_flash_interrupts( _level) |
#define | _CPU_ISR_Set_level(_newlevel) sh_set_interrupt_level(_newlevel) |
#define | _CPU_Context_Restart_self(_the_context) _CPU_Context_restore( (_the_context) ); |
#define | _CPU_Context_Initialize_fp(_destination) { } |
#define | _CPU_Fatal_halt(_source, _error) |
#define | CPU_USE_GENERIC_BITFIELD_CODE TRUE |
Typedefs | |
typedef void(* | CPU_ISR_raw_handler) (void) |
typedef void(* | CPU_ISR_handler) (uint32_t) |
typedef CPU_Interrupt_frame | CPU_Exception_frame |
typedef uint32_t | CPU_Counter_ticks |
typedef uintptr_t | CPU_Uint32ptr |
typedef void | sh_isr |
typedef void(* | sh_isr_entry) (void) |
Functions | |
void | CPU_delay (uint32_t microseconds) |
RTEMS_INLINE_ROUTINE bool | _CPU_ISR_Is_enabled (uint32_t level) |
Returns true if interrupts are enabled in the specified ISR level, otherwise returns false. More... | |
uint32_t | _CPU_ISR_Get_level (void) |
Returns the interrupt level of the executing thread. More... | |
void | _CPU_Context_Initialize (Context_Control *_the_context, void *_stack_base, uint32_t _size, uint32_t _isr, void(*_entry_point)(void), int _is_fp, void *_tls_area) |
void | _CPU_Initialize (void) |
CPU initialization. More... | |
void | _CPU_ISR_install_raw_handler (uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler) |
void | _CPU_ISR_install_vector (uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler) |
void * | _CPU_Thread_Idle_body (uintptr_t ignored) |
void | _CPU_Context_switch (Context_Control *run, Context_Control *heir) |
CPU switch context. More... | |
void | _CPU_Context_restore (Context_Control *new_context) RTEMS_NO_RETURN |
void | _CPU_Context_save_fp (Context_Control_fp **fp_context_ptr) |
void | _CPU_Context_restore_fp (Context_Control_fp **fp_context_ptr) |
void | _CPU_Exception_frame_print (const CPU_Exception_frame *frame) |
Prints the exception frame via printk(). More... | |
uint32_t | _CPU_Counter_frequency (void) |
Returns the current CPU counter frequency in Hz. More... | |
CPU_Counter_ticks | _CPU_Counter_read (void) |
Returns the current CPU counter value. More... | |
Variables | |
CPU_ISR_raw_handler | _Hardware_isr_Table [] |
#define _CPU_Fatal_halt | ( | _source, | |
_error | |||
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typedef uintptr_t CPU_Uint32ptr |
Type that can store a 32-bit integer or a pointer.
typedef void sh_isr |
Types related to SH specific ISRs