19 #ifndef _RTEMS_SCORE_CPU_H 20 #define _RTEMS_SCORE_CPU_H 26 #include <rtems/score/types.h> 31 #define CPU_INLINE_ENABLE_DISPATCH TRUE 44 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE 51 #if ( M68K_HAS_SEPARATE_STACKS == 1) 52 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0 53 #define CPU_HAS_HARDWARE_INTERRUPT_STACK 1 55 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1 56 #define CPU_HAS_HARDWARE_INTERRUPT_STACK 0 58 #define CPU_ALLOCATE_INTERRUPT_STACK 1 66 #define CPU_ISR_PASSES_FRAME_POINTER 0 77 #if ( M68K_HAS_FPU == 1 ) || ( M68K_HAS_EMAC == 1 ) 78 #define CPU_HARDWARE_FP TRUE 79 #define CPU_SOFTWARE_FP FALSE 81 #define CPU_HARDWARE_FP FALSE 82 #if defined( __GNUC__ ) 83 #define CPU_SOFTWARE_FP TRUE 85 #define CPU_SOFTWARE_FP FALSE 96 #define CPU_ALL_TASKS_ARE_FP FALSE 97 #define CPU_IDLE_TASK_IS_FP FALSE 98 #define CPU_USE_DEFERRED_FP_SWITCH TRUE 100 #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE 101 #define CPU_STACK_GROWS_UP FALSE 102 #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (4))) 104 #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE 111 #define CPU_BIG_ENDIAN TRUE 112 #define CPU_LITTLE_ENDIAN FALSE 114 #define CPU_PER_CPU_CONTROL_SIZE 0 116 #if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ ) 117 #if defined( __mc68060__ ) 118 #define M68K_FP_STATE_SIZE 16 120 #define M68K_FP_STATE_SIZE 216 146 #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 ) 151 #define _CPU_Context_Get_SP( _context ) \ 158 #if ( CPU_SOFTWARE_FP == TRUE ) 166 uint16_t _exception_bits;
167 uint16_t _trap_enable_bits;
168 uint16_t _sticky_bits;
169 uint16_t _rounding_mode;
171 uint16_t _last_operation;
185 #define _CPU_Context_Fp_start( _base, _offset ) \ 186 ((void *) _Addresses_Add_offset( (_base), (_offset) ) ) 188 #define _CPU_Context_Initialize_fp( _fp_area ) \ 190 Context_Control_fp *_fp; \ 191 _fp = *(Context_Control_fp **)_fp_area; \ 192 _fp->_exception_bits = 0; \ 193 _fp->_trap_enable_bits = 0; \ 194 _fp->_sticky_bits = 0; \ 195 _fp->_rounding_mode = 0; \ 197 _fp->_last_operation = 0; \ 198 _fp->_operand1.df = 0; \ 199 _fp->_operand2.df = 0; \ 203 #if ( CPU_HARDWARE_FP == TRUE ) 204 #if defined( __mcoldfire__ ) 208 #if ( M68K_HAS_FPU == 1 ) 214 extern uint32_t _CPU_cacr_shadow;
224 uint32_t emac_accext01;
225 uint32_t emac_accext23;
227 #if ( M68K_HAS_FPU == 1 ) 228 uint16_t fp_state_format;
229 uint16_t fp_state_fpcr;
231 uint32_t fp_state_fpsr;
244 #define _CPU_Context_Fp_start( _base, _offset ) \ 245 ((void *) _Addresses_Add_offset( (_base), (_offset) )) 253 #define _CPU_Context_Initialize_fp( _fp_area ) \ 254 memset( *(_fp_area), 0, sizeof( Context_Control_fp ) ) 267 uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112];
270 #define _CPU_Context_Fp_start( _base, _offset ) \ 272 (void *) _Addresses_Add_offset( \ 274 (_offset) + CPU_CONTEXT_FP_SIZE - 4 \ 278 #define _CPU_Context_Initialize_fp( _fp_area ) \ 280 uint32_t *_fp_context = (uint32_t *)*(_fp_area); \ 281 *(--(_fp_context)) = 0; \ 282 *(_fp_area) = (void *)(_fp_context); \ 302 uint32_t d0, d1, d2, d3, d4, d5, d6, d7;
303 uint32_t a0, a1, a2, a3, a4, a5, a6, a7;
310 #if ( M68K_HAS_VBR == 0 ) 326 uint32_t isr_handler;
329 #define M68K_MOVE_A7 0x3F3C 330 #define M68K_JMP 0x4EF9 346 #define CPU_MODES_INTERRUPT_LEVEL 0x00000007 347 #define CPU_MODES_INTERRUPT_MASK 0x00000007 353 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) 359 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024 365 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256 366 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) 373 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE 379 #define CPU_STACK_MINIMUM_SIZE M68K_CPU_STACK_MINIMUM_SIZE 384 #define CPU_PRIORITY_MAXIMUM M68K_CPU_PRIORITY_MAXIMUM 386 #define CPU_SIZEOF_POINTER 4 392 #define CPU_ALIGNMENT 4 393 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT 394 #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT 401 #define CPU_STACK_ALIGNMENT 0 418 #define _CPU_Initialize_vectors() 420 #define _CPU_ISR_Disable( _level ) \ 421 m68k_disable_interrupts( _level ) 423 #define _CPU_ISR_Enable( _level ) \ 424 m68k_enable_interrupts( _level ) 426 #define _CPU_ISR_Flash( _level ) \ 427 m68k_flash_interrupts( _level ) 429 #define _CPU_ISR_Set_level( _newlevel ) \ 430 m68k_set_interrupt_level( _newlevel ) 448 void *stack_area_begin,
449 size_t stack_area_size,
451 void (*entry_point)(
void ),
476 #if ( defined(__mcoldfire__) ) 477 #define _CPU_Fatal_halt( _source, _error ) \ 478 { __asm__ volatile( "move.w %%sr,%%d0\n\t" \ 480 "move.w %%d0,%%sr\n\t" \ 481 "move.l %1,%%d0\n\t" \ 482 "move.l #0xDEADBEEF,%%d1\n\t" \ 485 : "0" (_error), "d"(0x0700) \ 489 #define _CPU_Fatal_halt( _source, _error ) \ 490 { __asm__ volatile( "movl %0,%%d0; " \ 491 "orw #0x0700,%%sr; " \ 492 "stop #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \ 512 #define CPU_USE_GENERIC_BITFIELD_CODE FALSE 513 #define CPU_USE_GENERIC_BITFIELD_DATA FALSE 515 #if ( M68K_HAS_BFFFO != 1 ) 519 extern const unsigned char _CPU_m68k_BFFFO_table[256];
522 #if ( M68K_HAS_BFFFO == 1 ) 524 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ 525 __asm__ volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value)); 527 #elif ( __mcfisaaplus__ ) 529 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ 541 #if ( defined(__mcoldfire__) ) 543 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ 545 register int dumby; \ 552 " move.b (%3,%1),%0\n" \ 554 "1: move.w %2,%1\n" \ 555 " move.b (%3,%1),%0\n" \ 557 "0: and.l #0xff,%0\n" \ 558 : "=&d" ((_output)), "=&d" ((dumby)) \ 559 : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ 562 #elif ( M68K_HAS_EXTB_L == 1 ) 563 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ 565 register int dumby; \ 567 __asm__ volatile ( " move.w %2,%1\n" \ 570 " move.b (%3,%1.w),%0\n" \ 573 "1: moveq.l #8,%0\n" \ 574 " add.b (%3,%2.w),%0\n" \ 576 : "=&d" ((_output)), "=&d" ((dumby)) \ 577 : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ 581 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ 583 register int dumby; \ 585 __asm__ volatile ( " move.w %2,%1\n" \ 588 " move.b (%3,%1.w),%0\n" \ 589 " and.l #0x000000ff,%0\n"\ 591 "1: moveq.l #8,%0\n" \ 592 " add.b (%3,%2.w),%0\n" \ 594 : "=&d" ((_output)), "=&d" ((dumby)) \ 595 : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \ 614 #define _CPU_Priority_Mask( _bit_number ) \ 615 ( 0x8000 >> (_bit_number) ) 617 #define _CPU_Priority_bits_index( _priority ) \ 676 void _CPU_Context_Restart_self(
723 CPU_Counter_ticks _CPU_Counter_read(
void );
726 CPU_Counter_ticks second,
727 CPU_Counter_ticks first
730 return second - first;
733 #if (M68K_HAS_FPSP_PACKAGE == 1) 759 void M68KFPSPInstallExceptionHandlers (
void);
void _CPU_Context_save_fp(Context_Control_fp **fp_context_ptr)
This routine saves the floating point context passed to it.
Definition: m68k/cpu.c:167
void _CPU_ISR_install_vector(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs an interrupt vector.
Definition: avr/cpu.c:69
void _CPU_Context_validate(uintptr_t pattern)
Initializes and validates the CPU context with values derived from the pattern parameter.
Definition: score/cpu/mips/rtems/score/cpu.h:1109
uint32_t _CPU_ISR_Get_level(void)
Return the current interrupt disable level for this task in the format used by the interrupt level po...
Definition: avr/cpu.c:39
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: no_cpu/cpu_asm.c:92
void _CPU_Context_volatile_clobber(uintptr_t pattern)
Clobbers all volatile registers with values derived from the pattern parameter.
Definition: score/cpu/mips/rtems/score/cpu.h:1104
This defines the minimal set of integer and processor state registers that must be saved during a vol...
Definition: score/cpu/arm/rtems/score/cpu.h:248
void _CPU_Context_restore_fp(Context_Control_fp **fp_context_ptr)
This routine restores the floating point context passed to it.
Definition: m68k/cpu.c:176
Definition: score/cpu/m68k/rtems/score/cpu.h:322
void _CPU_Initialize(void)
CPU initialization.
Definition: avr/cpu.c:26
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: score/cpu/no_cpu/rtems/score/cpu.h:1461
This defines the set of integer and processor state registers that must be saved during an interrupt...
Definition: score/cpu/avr/rtems/score/cpu.h:425
void _CPU_Install_interrupt_stack(void)
This routine installs the hardware interrupt stack pointer.
Definition: avr/cpu.c:101
CPU_Counter_ticks _CPU_Counter_difference(CPU_Counter_ticks second, CPU_Counter_ticks first)
Returns the difference between the second and first CPU counter value.
Definition: score/cpu/mips/rtems/score/cpu.h:1160
This defines the complete set of floating point registers that must be saved during any context switc...
Definition: score/cpu/arm/rtems/score/cpu.h:294
void _CPU_ISR_install_raw_handler(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs a "raw" interrupt handler directly into the processor's vector table...
Definition: avr/cpu.c:57
#define RTEMS_COMPILER_NO_RETURN_ATTRIBUTE
The following macro is a compiler specific way to indicate that the method will NOT return to the cal...
Definition: basedefs.h:162
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
This method prints the CPU exception frame.
Definition: arm-exception-frame-print.c:46
Motorola M68K CPU Dependent Source.
void * _CPU_Thread_Idle_body(uintptr_t ignored)
This routine is the CPU dependent IDLE thread body.
Definition: avr/cpu.c:125
void _CPU_Context_Initialize(Context_Control *the_context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
Initializes the CPU context.
Definition: epiphany-context-initialize.c:41
The set of registers that specifies the complete processor state.
Definition: score/cpu/arm/rtems/score/cpu.h:671
#define SCORE_EXTERN
The following ensures that all data is declared in the space of the initialization routine for either...
Definition: basedefs.h:81
void * proc_ptr
XXX: Eventually proc_ptr needs to disappear!!!
Definition: basedefs.h:329