RTEMS CPU Kit with SuperCore
score/cpu/m68k/rtems/score/cpu.h
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1 
10 /*
11  * COPYRIGHT (c) 1989-2011.
12  * On-Line Applications Research Corporation (OAR).
13  *
14  * The license and distribution terms for this file may be
15  * found in the file LICENSE in this distribution or at
16  * http://www.rtems.org/license/LICENSE.
17  */
18 
19 #ifndef _RTEMS_SCORE_CPU_H
20 #define _RTEMS_SCORE_CPU_H
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
26 #include <rtems/score/types.h>
27 #include <rtems/score/m68k.h>
28 
29 /* conditional compilation parameters */
30 
31 #define CPU_INLINE_ENABLE_DISPATCH TRUE
32 
33 /*
34  * Does the CPU follow the simple vectored interrupt model?
35  *
36  * If TRUE, then RTEMS allocates the vector table it internally manages.
37  * If FALSE, then the BSP is assumed to allocate and manage the vector
38  * table
39  *
40  * M68K Specific Information:
41  *
42  * XXX document implementation including references if appropriate
43  */
44 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
45 
46 /*
47  * Use the m68k's hardware interrupt stack support and have the
48  * interrupt manager allocate the memory for it.
49  */
50 
51 #if ( M68K_HAS_SEPARATE_STACKS == 1)
52 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
53 #define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
54 #else
55 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
56 #define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
57 #endif
58 #define CPU_ALLOCATE_INTERRUPT_STACK 1
59 
60 /*
61  * Does the RTEMS invoke the user's ISR with the vector number and
62  * a pointer to the saved interrupt frame (1) or just the vector
63  * number (0)?
64  */
65 
66 #define CPU_ISR_PASSES_FRAME_POINTER 0
67 
68 /*
69  * Some family members have no FP, some have an FPU such as the
70  * MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
71  *
72  * NOTE: If on a CPU without hardware FP, then one can use software
73  * emulation. The gcc software FP emulation code has data which
74  * must be contexted switched on a per task basis.
75  */
76 
77 #if ( M68K_HAS_FPU == 1 ) || ( M68K_HAS_EMAC == 1 )
78  #define CPU_HARDWARE_FP TRUE
79  #define CPU_SOFTWARE_FP FALSE
80 #else
81  #define CPU_HARDWARE_FP FALSE
82  #if defined( __GNUC__ )
83  #define CPU_SOFTWARE_FP TRUE
84  #else
85  #define CPU_SOFTWARE_FP FALSE
86  #endif
87 #endif
88 
89 /*
90  * All tasks are not by default floating point tasks on this CPU.
91  * The IDLE task does not have a floating point context on this CPU.
92  * It is safe to use the deferred floating point context switch
93  * algorithm on this CPU.
94  */
95 
96 #define CPU_ALL_TASKS_ARE_FP FALSE
97 #define CPU_IDLE_TASK_IS_FP FALSE
98 #define CPU_USE_DEFERRED_FP_SWITCH TRUE
99 
100 #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
101 #define CPU_STACK_GROWS_UP FALSE
102 #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (4)))
103 
104 #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
105 
106 /*
107  * Define what is required to specify how the network to host conversion
108  * routines are handled.
109  */
110 
111 #define CPU_BIG_ENDIAN TRUE
112 #define CPU_LITTLE_ENDIAN FALSE
113 
114 #define CPU_PER_CPU_CONTROL_SIZE 0
115 
116 #if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ )
117  #if defined( __mc68060__ )
118  #define M68K_FP_STATE_SIZE 16
119  #else
120  #define M68K_FP_STATE_SIZE 216
121  #endif
122 #endif
123 
124 #ifndef ASM
125 
126 /* structures */
127 
128 /*
129  * Basic integer context for the m68k family.
130  */
131 
132 typedef struct {
133  uint32_t sr; /* (sr) status register */
134  uint32_t d2; /* (d2) data register 2 */
135  uint32_t d3; /* (d3) data register 3 */
136  uint32_t d4; /* (d4) data register 4 */
137  uint32_t d5; /* (d5) data register 5 */
138  uint32_t d6; /* (d6) data register 6 */
139  uint32_t d7; /* (d7) data register 7 */
140  void *a2; /* (a2) address register 2 */
141  void *a3; /* (a3) address register 3 */
142  void *a4; /* (a4) address register 4 */
143  void *a5; /* (a5) address register 5 */
144  void *a6; /* (a6) address register 6 */
145  void *a7_msp; /* (a7) master stack pointer */
146  #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
147  uint8_t fpu_dis;
148  #endif
150 
151 #define _CPU_Context_Get_SP( _context ) \
152  (_context)->a7_msp
153 
154 /*
155  * Floating point context areas and support routines
156  */
157 
158 #if ( CPU_SOFTWARE_FP == TRUE )
159  /*
160  * This is the same as gcc's view of the software FP condition code
161  * register _fpCCR. The implementation of the emulation code is
162  * in the gcc-VERSION/config/m68k directory. This structure is
163  * correct as of gcc 2.7.2.2.
164  */
165  typedef struct {
166  uint16_t _exception_bits;
167  uint16_t _trap_enable_bits;
168  uint16_t _sticky_bits;
169  uint16_t _rounding_mode;
170  uint16_t _format;
171  uint16_t _last_operation;
172  union {
173  float sf;
174  double df;
175  } _operand1;
176  union {
177  float sf;
178  double df;
179  } _operand2;
181 
182  /*
183  * This software FP implementation is only for GCC.
184  */
185  #define _CPU_Context_Fp_start( _base, _offset ) \
186  ((void *) _Addresses_Add_offset( (_base), (_offset) ) )
187 
188  #define _CPU_Context_Initialize_fp( _fp_area ) \
189  { \
190  Context_Control_fp *_fp; \
191  _fp = *(Context_Control_fp **)_fp_area; \
192  _fp->_exception_bits = 0; \
193  _fp->_trap_enable_bits = 0; \
194  _fp->_sticky_bits = 0; \
195  _fp->_rounding_mode = 0; /* ROUND_TO_NEAREST */ \
196  _fp->_format = 0; /* NIL */ \
197  _fp->_last_operation = 0; /* NOOP */ \
198  _fp->_operand1.df = 0; \
199  _fp->_operand2.df = 0; \
200  }
201 #endif
202 
203 #if ( CPU_HARDWARE_FP == TRUE )
204  #if defined( __mcoldfire__ )
205  /* We need memset() to initialize the FP context */
206  #include <string.h>
207 
208  #if ( M68K_HAS_FPU == 1 )
209  /*
210  * The Cache Control Register (CACR) has write-only access. It is also
211  * used to enable and disable the FPU. We need to maintain a copy of
212  * this register to allow per thread values.
213  */
214  extern uint32_t _CPU_cacr_shadow;
215  #endif
216 
217  /* We assume that each ColdFire core with a FPU has also an EMAC unit */
218  typedef struct {
219  uint32_t emac_macsr;
220  uint32_t emac_acc0;
221  uint32_t emac_acc1;
222  uint32_t emac_acc2;
223  uint32_t emac_acc3;
224  uint32_t emac_accext01;
225  uint32_t emac_accext23;
226  uint32_t emac_mask;
227  #if ( M68K_HAS_FPU == 1 )
228  uint16_t fp_state_format;
229  uint16_t fp_state_fpcr;
230  double fp_state_op;
231  uint32_t fp_state_fpsr;
232 
233  /*
234  * We need to save the FP Instruction Address Register (FPIAR), because
235  * a context switch can occur within a FP exception before the handler
236  * was able to save this register.
237  */
238  uint32_t fp_fpiar;
239 
240  double fp_data [8];
241  #endif
243 
244  #define _CPU_Context_Fp_start( _base, _offset ) \
245  ((void *) _Addresses_Add_offset( (_base), (_offset) ))
246 
247  /*
248  * The reset value for all context relevant registers except the FP data
249  * registers is zero. The reset value of the FP data register is NAN. The
250  * restore of the reset FP state will reset the FP data registers, so the
251  * initial value of them can be arbitrary here.
252  */
253  #define _CPU_Context_Initialize_fp( _fp_area ) \
254  memset( *(_fp_area), 0, sizeof( Context_Control_fp ) )
255  #else
256  /*
257  * FP context save area for the M68881/M68882 and 68060 numeric
258  * coprocessors.
259  */
260  typedef struct {
261  /*
262  * M68K_FP_STATE_SIZE bytes for FSAVE/FRESTORE
263  * 96 bytes for FMOVEM FP0-7
264  * 12 bytes for FMOVEM CREGS
265  * 4 bytes for non-null flag
266  */
267  uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112];
269 
270  #define _CPU_Context_Fp_start( _base, _offset ) \
271  ( \
272  (void *) _Addresses_Add_offset( \
273  (_base), \
274  (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
275  ) \
276  )
277 
278  #define _CPU_Context_Initialize_fp( _fp_area ) \
279  { \
280  uint32_t *_fp_context = (uint32_t *)*(_fp_area); \
281  *(--(_fp_context)) = 0; \
282  *(_fp_area) = (void *)(_fp_context); \
283  }
284  #endif
285 #endif
286 
287 /*
288  * The following structures define the set of information saved
289  * on the current stack by RTEMS upon receipt of each exc/interrupt.
290  * These are not used by m68k handlers.
291  * The exception frame is for rdbg.
292  */
293 
294 typedef struct {
295  uint32_t vecnum; /* vector number */
297 
298 typedef struct {
299  uint32_t vecnum; /* vector number */
300  uint32_t sr; /* status register */
301  uint32_t pc; /* program counter */
302  uint32_t d0, d1, d2, d3, d4, d5, d6, d7;
303  uint32_t a0, a1, a2, a3, a4, a5, a6, a7;
305 
306 /* variables */
307 
308 extern void* _VBR;
309 
310 #if ( M68K_HAS_VBR == 0 )
311 
312 /*
313  * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
314  * pushed onto the stack. This is not is the same order as VBR processors.
315  * The ISR handler takes the format and uses it for dispatching the user
316  * handler.
317  *
318  * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
319  *
320  */
321 
322 typedef struct {
323  uint16_t move_a7; /* move #FORMAT_ID,%a7@- */
324  uint16_t format_id;
325  uint16_t jmp; /* jmp _ISR_Handlers */
326  uint32_t isr_handler;
328 
329 #define M68K_MOVE_A7 0x3F3C
330 #define M68K_JMP 0x4EF9
331 
332  /* points to jsr-exception-table in targets wo/ VBR register */
333 SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256];
334 
335 #endif /* M68K_HAS_VBR */
336 
337 #endif /* ASM */
338 
339 /* constants */
340 
341 /*
342  * This defines the number of levels and the mask used to pick those
343  * bits out of a thread mode.
344  */
345 
346 #define CPU_MODES_INTERRUPT_LEVEL 0x00000007 /* interrupt level in mode */
347 #define CPU_MODES_INTERRUPT_MASK 0x00000007 /* interrupt level in mode */
348 
349 /*
350  * context size area for floating point
351  */
352 
353 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
354 
355 /*
356  * extra stack required by the MPCI receive server thread
357  */
358 
359 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
360 
361 /*
362  * m68k family supports 256 distinct vectors.
363  */
364 
365 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 256
366 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
367 
368 /*
369  * This is defined if the port has a special way to report the ISR nesting
370  * level. Most ports maintain the variable _ISR_Nest_level.
371  */
372 
373 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
374 
375 /*
376  * Minimum size of a thread's stack.
377  */
378 
379 #define CPU_STACK_MINIMUM_SIZE M68K_CPU_STACK_MINIMUM_SIZE
380 
381 /*
382  * Maximum priority of a thread. Note based from 0 which is the idle task.
383  */
384 #define CPU_PRIORITY_MAXIMUM M68K_CPU_PRIORITY_MAXIMUM
385 
386 #define CPU_SIZEOF_POINTER 4
387 
388 /*
389  * m68k is pretty tolerant of alignment. Just put things on 4 byte boundaries.
390  */
391 
392 #define CPU_ALIGNMENT 4
393 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
394 #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
395 
396 /*
397  * On m68k thread stacks require no further alignment after allocation
398  * from the Workspace.
399  */
400 
401 #define CPU_STACK_ALIGNMENT 0
402 
403 #ifndef ASM
404 
405 /* macros */
406 
407 /*
408  * ISR handler macros
409  *
410  * These macros perform the following functions:
411  * + initialize the RTEMS vector table
412  * + disable all maskable CPU interrupts
413  * + restore previous interrupt level (enable)
414  * + temporarily restore interrupts (flash)
415  * + set a particular level
416  */
417 
418 #define _CPU_Initialize_vectors()
419 
420 #define _CPU_ISR_Disable( _level ) \
421  m68k_disable_interrupts( _level )
422 
423 #define _CPU_ISR_Enable( _level ) \
424  m68k_enable_interrupts( _level )
425 
426 #define _CPU_ISR_Flash( _level ) \
427  m68k_flash_interrupts( _level )
428 
429 #define _CPU_ISR_Set_level( _newlevel ) \
430  m68k_set_interrupt_level( _newlevel )
431 
432 uint32_t _CPU_ISR_Get_level( void );
433 
434 /* end of ISR handler macros */
435 
436 /*
437  * Context handler macros
438  *
439  * These macros perform the following functions:
440  * + initialize a context area
441  * + restart the current thread
442  * + calculate the initial pointer into a FP context area
443  * + initialize an FP context area
444  */
445 
447  Context_Control *the_context,
448  void *stack_area_begin,
449  size_t stack_area_size,
450  uint32_t new_level,
451  void (*entry_point)( void ),
452  bool is_fp,
453  void *tls_area
454 );
455 
456 /* end of Context handler macros */
457 
458 /*
459  * _CPU_Thread_Idle_body
460  *
461  * This routine is the CPU dependent IDLE thread body.
462  *
463  * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
464  * is TRUE.
465  */
466 
467 void *_CPU_Thread_Idle_body( uintptr_t ignored );
468 
469 /*
470  * Fatal Error manager macros
471  *
472  * These macros perform the following functions:
473  * + disable interrupts and halt the CPU
474  */
475 
476 #if ( defined(__mcoldfire__) )
477 #define _CPU_Fatal_halt( _source, _error ) \
478  { __asm__ volatile( "move.w %%sr,%%d0\n\t" \
479  "or.l %2,%%d0\n\t" \
480  "move.w %%d0,%%sr\n\t" \
481  "move.l %1,%%d0\n\t" \
482  "move.l #0xDEADBEEF,%%d1\n\t" \
483  "halt" \
484  : "=g" (_error) \
485  : "0" (_error), "d"(0x0700) \
486  : "d0", "d1" ); \
487  }
488 #else
489 #define _CPU_Fatal_halt( _source, _error ) \
490  { __asm__ volatile( "movl %0,%%d0; " \
491  "orw #0x0700,%%sr; " \
492  "stop #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
493  }
494 #endif
495 
496 /* end of Fatal Error manager macros */
497 
498 /*
499  * Bitfield handler macros
500  *
501  * These macros perform the following functions:
502  * + scan for the highest numbered (MSB) set in a 16 bit bitfield
503  *
504  * NOTE:
505  *
506  * It appears that on the M68020 bitfield are always 32 bits wide
507  * when in a register. This code forces the bitfield to be in
508  * memory (it really always is anyway). This allows us to
509  * have a real 16 bit wide bitfield which operates "correctly."
510  */
511 
512 #define CPU_USE_GENERIC_BITFIELD_CODE FALSE
513 #define CPU_USE_GENERIC_BITFIELD_DATA FALSE
514 
515 #if ( M68K_HAS_BFFFO != 1 )
516 /*
517  * Lookup table for BFFFO simulation
518  */
519 extern const unsigned char _CPU_m68k_BFFFO_table[256];
520 #endif
521 
522 #if ( M68K_HAS_BFFFO == 1 )
523 
524 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \
525  __asm__ volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
526 
527 #elif ( __mcfisaaplus__ )
528  /* This is simplified by the fact that RTEMS never calls it with _value=0 */
529 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \
530  __asm__ volatile ( \
531  " swap %0\n" \
532  " ff1.l %0\n" \
533  : "=d" ((_output)) \
534  : "0" ((_value)) \
535  : "cc" ) ;
536 
537 #else
538 /* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
539  _CPU_Priority_bits_index is not needed), handles the 0 case, and
540  does not molest _value -- jsg */
541 #if ( defined(__mcoldfire__) )
542 
543 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \
544  { \
545  register int dumby; \
546  \
547  __asm__ volatile ( \
548  " clr.l %1\n" \
549  " move.w %2,%1\n" \
550  " lsr.l #8,%1\n" \
551  " beq.s 1f\n" \
552  " move.b (%3,%1),%0\n" \
553  " bra.s 0f\n" \
554  "1: move.w %2,%1\n" \
555  " move.b (%3,%1),%0\n" \
556  " addq.l #8,%0\n" \
557  "0: and.l #0xff,%0\n" \
558  : "=&d" ((_output)), "=&d" ((dumby)) \
559  : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
560  : "cc" ) ; \
561  }
562 #elif ( M68K_HAS_EXTB_L == 1 )
563 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \
564  { \
565  register int dumby; \
566  \
567  __asm__ volatile ( " move.w %2,%1\n" \
568  " lsr.w #8,%1\n" \
569  " beq.s 1f\n" \
570  " move.b (%3,%1.w),%0\n" \
571  " extb.l %0\n" \
572  " bra.s 0f\n" \
573  "1: moveq.l #8,%0\n" \
574  " add.b (%3,%2.w),%0\n" \
575  "0:\n" \
576  : "=&d" ((_output)), "=&d" ((dumby)) \
577  : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
578  : "cc" ) ; \
579  }
580 #else
581 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \
582  { \
583  register int dumby; \
584  \
585  __asm__ volatile ( " move.w %2,%1\n" \
586  " lsr.w #8,%1\n" \
587  " beq.s 1f\n" \
588  " move.b (%3,%1.w),%0\n" \
589  " and.l #0x000000ff,%0\n"\
590  " bra.s 0f\n" \
591  "1: moveq.l #8,%0\n" \
592  " add.b (%3,%2.w),%0\n" \
593  "0:\n" \
594  : "=&d" ((_output)), "=&d" ((dumby)) \
595  : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
596  : "cc" ) ; \
597  }
598 #endif
599 
600 #endif
601 
602 /* end of Bitfield handler macros */
603 
604 /*
605  * Priority handler macros
606  *
607  * These macros perform the following functions:
608  * + return a mask with the bit for this major/minor portion of
609  * of thread priority set.
610  * + translate the bit number returned by "Bitfield_find_first_bit"
611  * into an index into the thread ready chain bit maps
612  */
613 
614 #define _CPU_Priority_Mask( _bit_number ) \
615  ( 0x8000 >> (_bit_number) )
616 
617 #define _CPU_Priority_bits_index( _priority ) \
618  (_priority)
619 
620 /* end of Priority handler macros */
621 
622 /* functions */
623 
624 /*
625  * _CPU_Initialize
626  *
627  * This routine performs CPU dependent initialization.
628  */
629 
630 void _CPU_Initialize(void);
631 
632 /*
633  * _CPU_ISR_install_raw_handler
634  *
635  * This routine installs a "raw" interrupt handler directly into the
636  * processor's vector table.
637  */
638 
640  uint32_t vector,
641  proc_ptr new_handler,
642  proc_ptr *old_handler
643 );
644 
645 /*
646  * _CPU_ISR_install_vector
647  *
648  * This routine installs an interrupt vector.
649  */
650 
652  uint32_t vector,
653  proc_ptr new_handler,
654  proc_ptr *old_handler
655 );
656 
657 /*
658  * _CPU_Install_interrupt_stack
659  *
660  * This routine installs the hardware interrupt stack pointer.
661  */
662 
663 void _CPU_Install_interrupt_stack( void );
664 
665 /*
666  * _CPU_Context_switch
667  *
668  * This routine switches from the run context to the heir context.
669  */
670 
672  Context_Control *run,
673  Context_Control *heir
674 );
675 
676 void _CPU_Context_Restart_self(
677  Context_Control *the_context
679 
680 /*
681  * _CPU_Context_save_fp
682  *
683  * This routine saves the floating point context passed to it.
684  */
685 
687  Context_Control_fp **fp_context_ptr
688 );
689 
690 /*
691  * _CPU_Context_restore_fp
692  *
693  * This routine restores the floating point context passed to it.
694  */
695 
697  Context_Control_fp **fp_context_ptr
698 );
699 
700 static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
701 {
702  /* TODO */
703 }
704 
705 static inline void _CPU_Context_validate( uintptr_t pattern )
706 {
707  while (1) {
708  /* TODO */
709  }
710 }
711 
718  const CPU_Exception_frame *frame
719 );
720 
721 typedef uint32_t CPU_Counter_ticks;
722 
723 CPU_Counter_ticks _CPU_Counter_read( void );
724 
725 static inline CPU_Counter_ticks _CPU_Counter_difference(
726  CPU_Counter_ticks second,
727  CPU_Counter_ticks first
728 )
729 {
730  return second - first;
731 }
732 
733 #if (M68K_HAS_FPSP_PACKAGE == 1)
734 /*
735  * Hooks for the Floating Point Support Package (FPSP) provided by Motorola
736  *
737  * NOTES:
738  *
739  * Motorola 68k family CPU's before the 68040 used a coprocessor
740  * (68881 or 68882) to handle floating point. The 68040 has internal
741  * floating point support -- but *not* the complete support provided by
742  * the 68881 or 68882. The leftover functions are taken care of by the
743  * M68040 Floating Point Support Package. Quoting from the MC68040
744  * Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
745  *
746  * "When used with the M68040FPSP, the MC68040 FPU is fully
747  * compliant with IEEE floating-point standards."
748  *
749  * M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
750  * is invoked early in the application code to ensure that proper FP
751  * behavior is installed. This is not left to the BSP to call, since
752  * this would force all applications using that BSP to use FPSP which
753  * is not necessarily desirable.
754  *
755  * There is a similar package for the 68060 but RTEMS does not yet
756  * support the 68060.
757  */
758 
759 void M68KFPSPInstallExceptionHandlers (void);
760 
761 SCORE_EXTERN int (*_FPSP_install_raw_handler)(
762  uint32_t vector,
763  proc_ptr new_handler,
764  proc_ptr *old_handler
765 );
766 
767 #endif
768 
769 
770 #endif
771 
772 #ifdef __cplusplus
773 }
774 #endif
775 
776 #endif
void _CPU_Context_save_fp(Context_Control_fp **fp_context_ptr)
This routine saves the floating point context passed to it.
Definition: m68k/cpu.c:167
void _CPU_ISR_install_vector(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs an interrupt vector.
Definition: avr/cpu.c:69
void _CPU_Context_validate(uintptr_t pattern)
Initializes and validates the CPU context with values derived from the pattern parameter.
Definition: score/cpu/mips/rtems/score/cpu.h:1109
uint32_t _CPU_ISR_Get_level(void)
Return the current interrupt disable level for this task in the format used by the interrupt level po...
Definition: avr/cpu.c:39
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: no_cpu/cpu_asm.c:92
void _CPU_Context_volatile_clobber(uintptr_t pattern)
Clobbers all volatile registers with values derived from the pattern parameter.
Definition: score/cpu/mips/rtems/score/cpu.h:1104
This defines the minimal set of integer and processor state registers that must be saved during a vol...
Definition: score/cpu/arm/rtems/score/cpu.h:248
void _CPU_Context_restore_fp(Context_Control_fp **fp_context_ptr)
This routine restores the floating point context passed to it.
Definition: m68k/cpu.c:176
Definition: score/cpu/m68k/rtems/score/cpu.h:322
void _CPU_Initialize(void)
CPU initialization.
Definition: avr/cpu.c:26
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: score/cpu/no_cpu/rtems/score/cpu.h:1461
This defines the set of integer and processor state registers that must be saved during an interrupt...
Definition: score/cpu/avr/rtems/score/cpu.h:425
void _CPU_Install_interrupt_stack(void)
This routine installs the hardware interrupt stack pointer.
Definition: avr/cpu.c:101
CPU_Counter_ticks _CPU_Counter_difference(CPU_Counter_ticks second, CPU_Counter_ticks first)
Returns the difference between the second and first CPU counter value.
Definition: score/cpu/mips/rtems/score/cpu.h:1160
This defines the complete set of floating point registers that must be saved during any context switc...
Definition: score/cpu/arm/rtems/score/cpu.h:294
void _CPU_ISR_install_raw_handler(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs a "raw" interrupt handler directly into the processor&#39;s vector table...
Definition: avr/cpu.c:57
#define RTEMS_COMPILER_NO_RETURN_ATTRIBUTE
The following macro is a compiler specific way to indicate that the method will NOT return to the cal...
Definition: basedefs.h:162
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
This method prints the CPU exception frame.
Definition: arm-exception-frame-print.c:46
Motorola M68K CPU Dependent Source.
void * _CPU_Thread_Idle_body(uintptr_t ignored)
This routine is the CPU dependent IDLE thread body.
Definition: avr/cpu.c:125
void _CPU_Context_Initialize(Context_Control *the_context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
Initializes the CPU context.
Definition: epiphany-context-initialize.c:41
The set of registers that specifies the complete processor state.
Definition: score/cpu/arm/rtems/score/cpu.h:671
#define SCORE_EXTERN
The following ensures that all data is declared in the space of the initialization routine for either...
Definition: basedefs.h:81
void * proc_ptr
XXX: Eventually proc_ptr needs to disappear!!!
Definition: basedefs.h:329