19 #ifndef _RTEMS_SCORE_CPU_H 20 #define _RTEMS_SCORE_CPU_H 26 #include <rtems/score/types.h> 52 #define CPU_INLINE_ENABLE_DISPATCH FALSE 81 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE 94 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE 114 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE 128 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE 139 #define CPU_ISR_PASSES_FRAME_POINTER 1 176 #define CPU_HARDWARE_FP FALSE 177 #define CPU_SOFTWARE_FP FALSE 203 #define CPU_ALL_TASKS_ARE_FP FALSE 220 #define CPU_IDLE_TASK_IS_FP FALSE 251 #define CPU_USE_DEFERRED_FP_SWITCH TRUE 277 #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE 290 #define CPU_STACK_GROWS_UP FALSE 315 #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) 317 #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE 340 #define CPU_BIG_ENDIAN TRUE 355 #define CPU_LITTLE_ENDIAN FALSE 369 #define CPU_MODES_INTERRUPT_MASK 0x00000001 371 #define CPU_PER_CPU_CONTROL_SIZE 0 463 #define _CPU_Context_Get_SP( _context ) \ 471 } Context_Control_fp;
551 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) 562 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 572 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 577 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) 583 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE 596 #define CPU_STACK_MINIMUM_SIZE (1024*4) 598 #define CPU_SIZEOF_POINTER 4 610 #define CPU_ALIGNMENT 4 635 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT 653 #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT 665 #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT 683 #define _CPU_Initialize_vectors() 695 #define _CPU_ISR_Disable( _isr_cookie ) \ 696 lm32_disable_interrupts( _isr_cookie ); 709 #define _CPU_ISR_Enable( _isr_cookie ) \ 710 lm32_enable_interrupts( _isr_cookie ); 724 #define _CPU_ISR_Flash( _isr_cookie ) \ 725 lm32_flash_interrupts( _isr_cookie ); 742 #define _CPU_ISR_Set_level( new_level ) \ 744 _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 ); \ 798 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ 799 _isr, _entry_point, _is_fp, _tls_area ) \ 801 uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \ 805 (_the_context)->gp = (uint32_t)_gp; \ 806 (_the_context)->fp = (uint32_t)_stack; \ 807 (_the_context)->sp = (uint32_t)_stack; \ 808 (_the_context)->ra = (uint32_t)(_entry_point); \ 826 #define _CPU_Context_Restart_self( _the_context ) \ 827 _CPU_Context_restore( (_the_context) ); 851 #define _CPU_Context_Fp_start( _base, _offset ) 877 *(*(_destination)) = _CPU_Null_fp_context; \
894 #define _CPU_Fatal_halt( _source, _error ) \ 914 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE 924 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE 990 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) 991 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ 1010 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) 1012 #define _CPU_Priority_Mask( _bit_number ) \ 1013 ( 1 << (_bit_number) ) 1030 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) 1032 #define _CPU_Priority_bits_index( _priority ) \ 1167 Context_Control_fp **fp_context_ptr
1184 Context_Control_fp **fp_context_ptr
1234 static inline uint32_t CPU_swap_u32(
1238 uint32_t byte1, byte2, byte3, byte4, swapped;
1240 byte4 = (value >> 24) & 0xff;
1241 byte3 = (value >> 16) & 0xff;
1242 byte2 = (value >> 8) & 0xff;
1243 byte1 = value & 0xff;
1245 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1256 static inline uint16_t CPU_swap_u16(uint16_t v)
1258 return v << 8 | v >> 8;
1263 CPU_Counter_ticks _CPU_Counter_read(
void );
1266 CPU_Counter_ticks second,
1267 CPU_Counter_ticks first
1270 return second - first;
void _CPU_ISR_install_vector(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs an interrupt vector.
Definition: avr/cpu.c:69
void _CPU_Context_validate(uintptr_t pattern)
Initializes and validates the CPU context with values derived from the pattern parameter.
Definition: score/cpu/mips/rtems/score/cpu.h:1109
uint32_t _CPU_ISR_Get_level(void)
Return the current interrupt disable level for this task in the format used by the interrupt level po...
Definition: avr/cpu.c:39
void _CPU_Context_restore(Context_Control *new_context)
This routine is generally used only to restart self in an efficient manner.
Definition: no_cpu/cpu_asm.c:112
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: no_cpu/cpu_asm.c:92
void _CPU_Context_volatile_clobber(uintptr_t pattern)
Clobbers all volatile registers with values derived from the pattern parameter.
Definition: score/cpu/mips/rtems/score/cpu.h:1104
#define _CPU_Context_Initialize_fp(_destination)
This routine initializes the FP context area passed to it to.
Definition: score/cpu/lm32/rtems/score/cpu.h:874
This defines the minimal set of integer and processor state registers that must be saved during a vol...
Definition: score/cpu/arm/rtems/score/cpu.h:248
void _CPU_Initialize(void)
This routine performs CPU dependent initialization.
Definition: avr/cpu.c:26
uint32_t r12
r12 – may be global pointer
Definition: score/cpu/lm32/rtems/score/cpu.h:433
LM32 Set up Basic CPU Dependency Settings Based on Compiler Settings.
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: score/cpu/no_cpu/rtems/score/cpu.h:1461
This defines the set of integer and processor state registers that must be saved during an interrupt...
Definition: score/cpu/avr/rtems/score/cpu.h:425
RTEMS_INLINE_ROUTINE void * _Addresses_Add_offset(const void *base, uintptr_t offset)
Add offset to an address.
Definition: address.h:50
void _CPU_Context_restore_fp(Context_Control_fp **fp_context_ptr)
This routine restores the floating point context passed to it.
Definition: m68k/cpu.c:176
void _CPU_Install_interrupt_stack(void)
This routine installs the hardware interrupt stack pointer.
Definition: avr/cpu.c:101
CPU_Counter_ticks _CPU_Counter_difference(CPU_Counter_ticks second, CPU_Counter_ticks first)
Returns the difference between the second and first CPU counter value.
Definition: score/cpu/mips/rtems/score/cpu.h:1160
void _CPU_Context_save_fp(Context_Control_fp **fp_context_ptr)
This routine saves the floating point context passed to it.
Definition: m68k/cpu.c:167
void _CPU_ISR_install_raw_handler(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs a "raw" interrupt handler directly into the processor's vector table...
Definition: avr/cpu.c:57
#define RTEMS_COMPILER_NO_RETURN_ATTRIBUTE
The following macro is a compiler specific way to indicate that the method will NOT return to the cal...
Definition: basedefs.h:162
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: arm-exception-frame-print.c:46
void * _CPU_Thread_Idle_body(uintptr_t ignored)
This routine is the CPU dependent IDLE thread body.
Definition: avr/cpu.c:125
#define SCORE_EXTERN
The following ensures that all data is declared in the space of the initialization routine for either...
Definition: basedefs.h:81
void * proc_ptr
XXX: Eventually proc_ptr needs to disappear!!!
Definition: basedefs.h:329
uint32_t r11
r11 – temporary register
Definition: score/cpu/lm32/rtems/score/cpu.h:432
uint32_t sp
This will contain the stack pointer.
Definition: score/cpu/lm32/rtems/score/cpu.h:449