RTEMS CPU Kit with SuperCore
score/cpu/lm32/rtems/score/cpu.h
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1 
10 /*
11  * COPYRIGHT (c) 1989-2008.
12  * On-Line Applications Research Corporation (OAR).
13  *
14  * The license and distribution terms for this file may be
15  * found in the file LICENSE in this distribution or at
16  * http://www.rtems.org/license/LICENSE.
17  */
18 
19 #ifndef _RTEMS_SCORE_CPU_H
20 #define _RTEMS_SCORE_CPU_H
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
26 #include <rtems/score/types.h>
27 #include <rtems/score/lm32.h>
28 
29 /* conditional compilation parameters */
30 
52 #define CPU_INLINE_ENABLE_DISPATCH FALSE
53 
81 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
82 
94 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
95 
114 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
115 
128 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
129 
139 #define CPU_ISR_PASSES_FRAME_POINTER 1
140 
176 #define CPU_HARDWARE_FP FALSE
177 #define CPU_SOFTWARE_FP FALSE
178 
203 #define CPU_ALL_TASKS_ARE_FP FALSE
204 
220 #define CPU_IDLE_TASK_IS_FP FALSE
221 
251 #define CPU_USE_DEFERRED_FP_SWITCH TRUE
252 
277 #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
278 
290 #define CPU_STACK_GROWS_UP FALSE
291 
315 #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32)))
316 
317 #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
318 
340 #define CPU_BIG_ENDIAN TRUE
341 
355 #define CPU_LITTLE_ENDIAN FALSE
356 
369 #define CPU_MODES_INTERRUPT_MASK 0x00000001
370 
371 #define CPU_PER_CPU_CONTROL_SIZE 0
372 
373 /*
374  * Processor defined structures required for cpukit/score.
375  *
376  * Port Specific Information:
377  *
378  * XXX document implementation including references if appropriate
379  */
380 
381 /* may need to put some structures here. */
382 
431 typedef struct {
432  uint32_t r11;
433  uint32_t r12;
434  uint32_t r13;
435  uint32_t r14;
436  uint32_t r15;
437  uint32_t r16;
438  uint32_t r17;
439  uint32_t r18;
440  uint32_t r19;
441  uint32_t r20;
442  uint32_t r21;
443  uint32_t r22;
444  uint32_t r23;
445  uint32_t r24;
446  uint32_t r25;
447  uint32_t gp;
448  uint32_t fp;
449  uint32_t sp;
450  uint32_t ra;
451  uint32_t ie;
452  uint32_t epc;
454 
463 #define _CPU_Context_Get_SP( _context ) \
464  (_context)->sp
465 
470 typedef struct {
471 } Context_Control_fp;
472 
478 typedef struct {
479  uint32_t r1;
480  uint32_t r2;
481  uint32_t r3;
482  uint32_t r4;
483  uint32_t r5;
484  uint32_t r6;
485  uint32_t r7;
486  uint32_t r8;
487  uint32_t r9;
488  uint32_t r10;
489  uint32_t ra;
490  uint32_t ba;
491  uint32_t ea;
493 
504 #if 0
505 SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;
506 #endif
507 
530 /*
531  * Nothing prevents the porter from declaring more CPU specific variables.
532  *
533  * Port Specific Information:
534  *
535  * XXX document implementation including references if appropriate
536  */
537 
538 /* XXX: if needed, put more variables here */
539 
551 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
552 
562 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
563 
572 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
573 
577 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
578 
583 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
584 
596 #define CPU_STACK_MINIMUM_SIZE (1024*4)
597 
598 #define CPU_SIZEOF_POINTER 4
599 
610 #define CPU_ALIGNMENT 4
611 
635 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
636 
653 #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
654 
665 #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
666 
667 /*
668  * ISR handler macros
669  */
670 
683 #define _CPU_Initialize_vectors()
684 
695 #define _CPU_ISR_Disable( _isr_cookie ) \
696  lm32_disable_interrupts( _isr_cookie );
697 
709 #define _CPU_ISR_Enable( _isr_cookie ) \
710  lm32_enable_interrupts( _isr_cookie );
711 
724 #define _CPU_ISR_Flash( _isr_cookie ) \
725  lm32_flash_interrupts( _isr_cookie );
726 
742 #define _CPU_ISR_Set_level( new_level ) \
743  { \
744  _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 ); \
745  }
746 
757 uint32_t _CPU_ISR_Get_level( void );
758 
759 /* end of ISR handler macros */
760 
763 /* Context handler macros */
764 
796 extern char _gp[];
797 
798 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
799  _isr, _entry_point, _is_fp, _tls_area ) \
800  do { \
801  uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \
802  \
803  (void) _is_fp; /* avoid warning for being unused */ \
804  (void) _isr; /* avoid warning for being unused */ \
805  (_the_context)->gp = (uint32_t)_gp; \
806  (_the_context)->fp = (uint32_t)_stack; \
807  (_the_context)->sp = (uint32_t)_stack; \
808  (_the_context)->ra = (uint32_t)(_entry_point); \
809  } while ( 0 )
810 
826 #define _CPU_Context_Restart_self( _the_context ) \
827  _CPU_Context_restore( (_the_context) );
828 
851 #define _CPU_Context_Fp_start( _base, _offset )
852 #if 0
853  ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
854 #endif
855 
874 #define _CPU_Context_Initialize_fp( _destination )
875 #if 0
876  { \
877  *(*(_destination)) = _CPU_Null_fp_context; \
878  }
879 #endif
880 
881 /* end of Context handler macros */
882 
883 /* Fatal Error manager macros */
884 
894 #define _CPU_Fatal_halt( _source, _error ) \
895  { \
896  }
897 
898 /* end of Fatal Error manager macros */
899 
900 /* Bitfield handler macros */
901 
914 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
915 
924 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
925 
990 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
991 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \
992  { \
993  (_output) = 0; /* do something to prevent warnings */ \
994  }
995 #endif
996 
997 /* end of Bitfield handler macros */
998 
1010 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1011 
1012 #define _CPU_Priority_Mask( _bit_number ) \
1013  ( 1 << (_bit_number) )
1014 
1015 #endif
1016 
1030 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1031 
1032 #define _CPU_Priority_bits_index( _priority ) \
1033  (_priority)
1034 
1035 #endif
1036 
1037 /* end of Priority handler macros */
1038 
1039 /* functions */
1040 
1048 void _CPU_Initialize(void);
1049 
1068  uint32_t vector,
1069  proc_ptr new_handler,
1070  proc_ptr *old_handler
1071 );
1072 
1085  uint32_t vector,
1086  proc_ptr new_handler,
1087  proc_ptr *old_handler
1088 );
1089 
1100 void _CPU_Install_interrupt_stack( void );
1101 
1114 void *_CPU_Thread_Idle_body( uintptr_t ignored );
1115 
1127 void _CPU_Context_switch(
1128  Context_Control *run,
1129  Context_Control *heir
1130 );
1131 
1150  Context_Control *new_context
1152 
1167  Context_Control_fp **fp_context_ptr
1168 );
1169 
1184  Context_Control_fp **fp_context_ptr
1185 );
1186 
1187 static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
1188 {
1189  /* TODO */
1190 }
1191 
1192 static inline void _CPU_Context_validate( uintptr_t pattern )
1193 {
1194  while (1) {
1195  /* TODO */
1196  }
1197 }
1198 
1201 /* FIXME */
1202 typedef CPU_Interrupt_frame CPU_Exception_frame;
1203 
1204 void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1205 
1234 static inline uint32_t CPU_swap_u32(
1235  uint32_t value
1236 )
1237 {
1238  uint32_t byte1, byte2, byte3, byte4, swapped;
1239 
1240  byte4 = (value >> 24) & 0xff;
1241  byte3 = (value >> 16) & 0xff;
1242  byte2 = (value >> 8) & 0xff;
1243  byte1 = value & 0xff;
1244 
1245  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1246  return swapped;
1247 }
1248 
1256 static inline uint16_t CPU_swap_u16(uint16_t v)
1257 {
1258  return v << 8 | v >> 8;
1259 }
1260 
1261 typedef uint32_t CPU_Counter_ticks;
1262 
1263 CPU_Counter_ticks _CPU_Counter_read( void );
1264 
1265 static inline CPU_Counter_ticks _CPU_Counter_difference(
1266  CPU_Counter_ticks second,
1267  CPU_Counter_ticks first
1268 )
1269 {
1270  return second - first;
1271 }
1272 
1273 #ifdef __cplusplus
1274 }
1275 #endif
1276 
1277 #endif
void _CPU_ISR_install_vector(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs an interrupt vector.
Definition: avr/cpu.c:69
void _CPU_Context_validate(uintptr_t pattern)
Initializes and validates the CPU context with values derived from the pattern parameter.
Definition: score/cpu/mips/rtems/score/cpu.h:1109
uint32_t _CPU_ISR_Get_level(void)
Return the current interrupt disable level for this task in the format used by the interrupt level po...
Definition: avr/cpu.c:39
void _CPU_Context_restore(Context_Control *new_context)
This routine is generally used only to restart self in an efficient manner.
Definition: no_cpu/cpu_asm.c:112
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: no_cpu/cpu_asm.c:92
void _CPU_Context_volatile_clobber(uintptr_t pattern)
Clobbers all volatile registers with values derived from the pattern parameter.
Definition: score/cpu/mips/rtems/score/cpu.h:1104
#define _CPU_Context_Initialize_fp(_destination)
This routine initializes the FP context area passed to it to.
Definition: score/cpu/lm32/rtems/score/cpu.h:874
This defines the minimal set of integer and processor state registers that must be saved during a vol...
Definition: score/cpu/arm/rtems/score/cpu.h:248
void _CPU_Initialize(void)
This routine performs CPU dependent initialization.
Definition: avr/cpu.c:26
uint32_t r12
r12 – may be global pointer
Definition: score/cpu/lm32/rtems/score/cpu.h:433
LM32 Set up Basic CPU Dependency Settings Based on Compiler Settings.
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: score/cpu/no_cpu/rtems/score/cpu.h:1461
This defines the set of integer and processor state registers that must be saved during an interrupt...
Definition: score/cpu/avr/rtems/score/cpu.h:425
RTEMS_INLINE_ROUTINE void * _Addresses_Add_offset(const void *base, uintptr_t offset)
Add offset to an address.
Definition: address.h:50
void _CPU_Context_restore_fp(Context_Control_fp **fp_context_ptr)
This routine restores the floating point context passed to it.
Definition: m68k/cpu.c:176
void _CPU_Install_interrupt_stack(void)
This routine installs the hardware interrupt stack pointer.
Definition: avr/cpu.c:101
CPU_Counter_ticks _CPU_Counter_difference(CPU_Counter_ticks second, CPU_Counter_ticks first)
Returns the difference between the second and first CPU counter value.
Definition: score/cpu/mips/rtems/score/cpu.h:1160
void _CPU_Context_save_fp(Context_Control_fp **fp_context_ptr)
This routine saves the floating point context passed to it.
Definition: m68k/cpu.c:167
void _CPU_ISR_install_raw_handler(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs a "raw" interrupt handler directly into the processor&#39;s vector table...
Definition: avr/cpu.c:57
#define RTEMS_COMPILER_NO_RETURN_ATTRIBUTE
The following macro is a compiler specific way to indicate that the method will NOT return to the cal...
Definition: basedefs.h:162
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: arm-exception-frame-print.c:46
void * _CPU_Thread_Idle_body(uintptr_t ignored)
This routine is the CPU dependent IDLE thread body.
Definition: avr/cpu.c:125
#define SCORE_EXTERN
The following ensures that all data is declared in the space of the initialization routine for either...
Definition: basedefs.h:81
void * proc_ptr
XXX: Eventually proc_ptr needs to disappear!!!
Definition: basedefs.h:329
uint32_t r11
r11 – temporary register
Definition: score/cpu/lm32/rtems/score/cpu.h:432
uint32_t sp
This will contain the stack pointer.
Definition: score/cpu/lm32/rtems/score/cpu.h:449