19 #ifndef _RTEMS_SCORE_CPU_H 20 #define _RTEMS_SCORE_CPU_H 26 #include <rtems/score/types.h> 55 #define CPU_INLINE_ENABLE_DISPATCH FALSE 61 #define RTEMS_USE_16_BIT_OBJECT 91 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE 104 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE 125 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE 140 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE 162 #define CPU_HARDWARE_FP FALSE 177 #define CPU_ALL_TASKS_ARE_FP FALSE 195 #define CPU_IDLE_TASK_IS_FP FALSE 227 #define CPU_USE_DEFERRED_FP_SWITCH TRUE 257 #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE 271 #define CPU_STACK_GROWS_UP FALSE 297 #define CPU_STRUCTURE_ALIGNMENT 299 #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE 306 #define CPU_BIG_ENDIAN TRUE 307 #define CPU_LITTLE_ENDIAN FALSE 319 #define CPU_MODES_INTERRUPT_MASK 0x00000001 321 #define CPU_PER_CPU_CONTROL_SIZE 0 376 } CPU_Per_CPU_control;
378 #define nogap __attribute__ ((packed)) 393 #define _CPU_Context_Get_SP( _context ) \ 397 double some_float_register[2];
401 uint32_t special_interrupt_register;
438 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) 452 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 463 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 64 464 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) 471 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE 482 #define CPU_STACK_MINIMUM_SIZE (1536) 484 #if defined(__H8300H__) || defined(__H8300S__) || defined(__H8300SX__) 485 #define CPU_SIZEOF_POINTER 4 487 #define CPU_SIZEOF_POINTER 2 499 #define CPU_ALIGNMENT 8 517 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT 535 #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT 550 #define CPU_STACK_ALIGNMENT 2 560 #define _CPU_Initialize_vectors() 566 #if (__GNUC__ == 2 && __GNUC_MINOR__ == 7 ) 574 #define _CPU_ISR_Disable( _isr_cookie ) \ 576 __asm__ volatile( "stc.w ccr, @-er7 ;\n orc #0xC0,ccr ;\n mov.w @er7+,%0" : : "r" (_isr_cookie) ); \ 587 #define _CPU_ISR_Enable( _isr_cookie ) \ 589 __asm__ volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr" : : "r" (_isr_cookie) ); \ 601 #define _CPU_ISR_Flash( _isr_cookie ) \ 603 __asm__ volatile( "mov.w %0,@-er7 ;\n ldc.w @er7+, ccr ;\n orc #0xC0,ccr" : : "r" (_isr_cookie) ); \ 619 #if defined(__H8300H__) || defined(__H8300S__) 620 #define _CPU_ISR_Disable( _isr_cookie ) \ 622 unsigned char __ccr; \ 623 __asm__ volatile( "stc ccr, %0 ; orc #0x80,ccr " \ 625 (_isr_cookie) = __ccr; \ 628 #define _CPU_ISR_Disable( _isr_cookie ) \ 645 #if defined(__H8300H__) || defined(__H8300S__) 646 #define _CPU_ISR_Enable( _isr_cookie ) \ 648 unsigned char __ccr = (unsigned char) (_isr_cookie); \ 649 __asm__ volatile( "ldc %0, ccr" : : "m" (__ccr) ); \ 652 #define _CPU_ISR_Enable( _isr_cookie ) \ 654 (_isr_cookie) = (_isr_cookie); \ 669 #if defined(__H8300H__) || defined(__H8300S__) 670 #define _CPU_ISR_Flash( _isr_cookie ) \ 672 unsigned char __ccr = (unsigned char) (_isr_cookie); \ 673 __asm__ volatile( "ldc %0, ccr ; orc #0x80,ccr " : : "m" (__ccr) ); \ 676 #define _CPU_ISR_Flash( _isr_cookie ) \ 678 _CPU_ISR_Enable( _isr_cookie ); \ 679 _CPU_ISR_Disable( _isr_cookie ); \ 701 #define _CPU_ISR_Set_level( _new_level ) \ 703 if ( _new_level ) __asm__ volatile ( "orc #0x80,ccr\n" ); \ 704 else __asm__ volatile ( "andc #0x7f,ccr\n" ); \ 741 #define CPU_CCR_INTERRUPTS_ON 0x80 742 #define CPU_CCR_INTERRUPTS_OFF 0x00 744 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ 745 _isr, _entry_point, _is_fp, _tls_area ) \ 750 if ( (_isr) ) (_the_context)->ccr = CPU_CCR_INTERRUPTS_OFF; \ 751 else (_the_context)->ccr = CPU_CCR_INTERRUPTS_ON; \ 754 _stack = ((uintptr_t)(_stack_base)) + (_size) - 4; \ 755 *((proc_ptr *)(_stack)) = (_entry_point); \ 756 (_the_context)->er7 = (void *) _stack; \ 757 (_the_context)->er6 = (void *) _stack; \ 758 (_the_context)->er5 = 0; \ 759 (_the_context)->er4 = 1; \ 760 (_the_context)->er3 = 2; \ 778 #define _CPU_Context_Restart_self( _the_context ) \ 779 _CPU_Context_restore( (_the_context) ); 799 #define _CPU_Context_Fp_start( _base, _offset ) \ 800 ( (void *) (_base) + (_offset) ) 818 #define _CPU_Context_Initialize_fp( _destination ) \ 820 *(*(_destination)) = _CPU_Null_fp_context; \ 837 #define _CPU_Fatal_halt( _source, _error ) \ 838 printk("Fatal Error %d.%d Halted\n",_source, _error); \ 905 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE 906 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE 908 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) 910 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ 929 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) 931 #define _CPU_Priority_Mask( _bit_number ) \ 932 ( 1 << (_bit_number) ) 947 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) 949 #define _CPU_Priority_bits_index( _priority ) \ 1134 static inline uint32_t CPU_swap_u32(
1138 uint32_t byte1, byte2, byte3, byte4, swapped;
1140 byte4 = (value >> 24) & 0xff;
1141 byte3 = (value >> 16) & 0xff;
1142 byte2 = (value >> 8) & 0xff;
1143 byte1 = value & 0xff;
1145 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1149 #define CPU_swap_u16( value ) \ 1150 (((value&0xff) << 8) | ((value >> 8)&0xff)) 1157 CPU_Counter_ticks second,
1158 CPU_Counter_ticks first
1161 return second - first;
1165 extern void H8BD_Install_IRQ(
void _CPU_ISR_install_vector(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs an interrupt vector.
Definition: cpu.c:69
void _CPU_Context_validate(uintptr_t pattern)
Initializes and validates the CPU context with values derived from the pattern parameter.
Definition: cpu.h:1109
uint32_t _CPU_ISR_Get_level(void)
Return the current interrupt disable level for this task in the format used by the interrupt level po...
Definition: cpu.c:39
void _CPU_Context_restore(Context_Control *new_context)
This routine is generally used only to restart self in an efficient manner.
Definition: cpu_asm.c:112
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:92
void _CPU_Context_volatile_clobber(uintptr_t pattern)
Clobbers all volatile registers with values derived from the pattern parameter.
Definition: cpu.h:1104
Information Required to Build RTEMS for a Particular Member of the Hitachi H8/300 Family...
This defines the minimal set of integer and processor state registers that must be saved during a vol...
Definition: cpu.h:248
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:26
void _CPU_Install_interrupt_stack(void)
This routine installs the hardware interrupt stack pointer.
Definition: cpu.c:101
SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context
This variable is optional.
Definition: cpu.h:494
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1461
This defines the set of integer and processor state registers that must be saved during an interrupt...
Definition: cpu.h:425
void _CPU_ISR_install_raw_handler(uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler)
This routine installs a "raw" interrupt handler directly into the processor's vector table...
Definition: cpu.c:57
void _CPU_Context_restore_fp(Context_Control_fp **fp_context_ptr)
This routine restores the floating point context passed to it.
Definition: cpu.c:176
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: cpu.c:96
CPU_Counter_ticks _CPU_Counter_difference(CPU_Counter_ticks second, CPU_Counter_ticks first)
Returns the difference between the second and first CPU counter value.
Definition: cpu.h:1160
This defines the complete set of floating point registers that must be saved during any context switc...
Definition: cpu.h:294
Interface to Kernel Print Methods.
void _CPU_Context_save_fp(Context_Control_fp **fp_context_ptr)
This routine saves the floating point context passed to it.
Definition: cpu.c:167
#define RTEMS_COMPILER_NO_RETURN_ATTRIBUTE
The following macro is a compiler specific way to indicate that the method will NOT return to the cal...
Definition: basedefs.h:162
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: arm-exception-frame-print.c:46
void * _CPU_Thread_Idle_body(uintptr_t ignored)
This routine is the CPU dependent IDLE thread body.
Definition: cpu.c:125
#define SCORE_EXTERN
The following ensures that all data is declared in the space of the initialization routine for either...
Definition: basedefs.h:81
void * proc_ptr
XXX: Eventually proc_ptr needs to disappear!!!
Definition: basedefs.h:329