RTEMS  5.0.0
cpu.h
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1 
10 /*
11  * This include file contains information pertaining to the XXX
12  * processor.
13  *
14  * @note This file is part of a porting template that is intended
15  * to be used as the starting point when porting RTEMS to a new
16  * CPU family. The following needs to be done when using this as
17  * the starting point for a new port:
18  *
19  * + Anywhere there is an XXX, it should be replaced
20  * with information about the CPU family being ported to.
21  *
22  * + At the end of each comment section, there is a heading which
23  * says "Port Specific Information:". When porting to RTEMS,
24  * add CPU family specific information in this section
25  */
26 
27 /*
28  * COPYRIGHT (c) 1989-2008.
29  * On-Line Applications Research Corporation (OAR).
30  *
31  * The license and distribution terms for this file may be
32  * found in the file LICENSE in this distribution or at
33  * http://www.rtems.org/license/LICENSE.
34  */
35 
36 #ifndef _RTEMS_SCORE_CPU_H
37 #define _RTEMS_SCORE_CPU_H
38 
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42 
43 #include <rtems/score/basedefs.h>
44 #include <rtems/score/no_cpu.h>
45 
46 /* conditional compilation parameters */
47 
59 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
60 
70 #define CPU_ISR_PASSES_FRAME_POINTER FALSE
71 
107 #if ( NO_CPU_HAS_FPU == 1 )
108 #define CPU_HARDWARE_FP TRUE
109 #else
110 #define CPU_HARDWARE_FP FALSE
111 #endif
112 #define CPU_SOFTWARE_FP FALSE
113 
138 #define CPU_ALL_TASKS_ARE_FP TRUE
139 
155 #define CPU_IDLE_TASK_IS_FP FALSE
156 
186 #define CPU_USE_DEFERRED_FP_SWITCH TRUE
187 
198 #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
199 
211 #define CPU_STACK_GROWS_UP TRUE
212 
218 #define CPU_CACHE_LINE_BYTES 32
219 
231 #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
232 
244 #define CPU_MODES_INTERRUPT_MASK 0x00000001
245 
250 #define CPU_MAXIMUM_PROCESSORS 32
251 
252 /*
253  * Processor defined structures required for cpukit/score.
254  *
255  * Port Specific Information:
256  *
257  * XXX document implementation including references if appropriate
258  */
259 
260 /* may need to put some structures here. */
261 
315 typedef struct {
326 
331  uint32_t stack_pointer;
332 
333 #ifdef RTEMS_SMP
334 
378  volatile bool is_executing;
379 #endif
381 
391 #define _CPU_Context_Get_SP( _context ) \
392  (_context)->stack_pointer
393 
400 typedef struct {
402  double some_float_register;
404 
412 typedef struct {
418  uint32_t special_interrupt_register;
420 
432 
451 /*
452  * Nothing prevents the porter from declaring more CPU specific variables.
453  *
454  * Port Specific Information:
455  *
456  * XXX document implementation including references if appropriate
457  */
458 
459 /* XXX: if needed, put more variables here */
460 
473 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
474 
484 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
485 
496 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
497 
508 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
509 
516 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
517 
528 #define CPU_STACK_MINIMUM_SIZE (1024*4)
529 
537 #define CPU_SIZEOF_POINTER 4
538 
550 #define CPU_ALIGNMENT 8
551 
574 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
575 
589 #define CPU_STACK_ALIGNMENT 0
590 
597 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
598 
599 /*
600  * ISR handler macros
601  */
602 
612 #define _CPU_Initialize_vectors()
613 
626 #define _CPU_ISR_Disable( _isr_cookie ) \
627  { \
628  (_isr_cookie) = 0; /* do something to prevent warnings */ \
629  }
630 
644 #define _CPU_ISR_Enable( _isr_cookie ) \
645  { \
646  }
647 
662 #define _CPU_ISR_Flash( _isr_cookie ) \
663  { \
664  }
665 
676 {
677  return false;
678 }
679 
697 #define _CPU_ISR_Set_level( new_level ) \
698  { \
699  }
700 
713 uint32_t _CPU_ISR_Get_level( void );
714 
715 /* end of ISR handler macros */
716 
717 /* Context handler macros */
718 
734 #define _CPU_Context_Destroy( _the_thread, _the_context ) \
735  { \
736  }
737 
775 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
776  _isr, _entry_point, _is_fp, _tls_area ) \
777  { \
778  }
779 
795 #define _CPU_Context_Restart_self( _the_context ) \
796  _CPU_Context_restore( (_the_context) );
797 
816 #define _CPU_Context_Initialize_fp( _destination ) \
817  { \
818  *(*(_destination)) = _CPU_Null_fp_context; \
819  }
820 
821 /* end of Context handler macros */
822 
823 /* Fatal Error manager macros */
824 
834 #define _CPU_Fatal_halt( _source, _error ) \
835  { \
836  }
837 
838 /* end of Fatal Error manager macros */
839 
840 /* Bitfield handler macros */
841 
857 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
858 
923 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
924 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \
925  { \
926  (_output) = 0; /* do something to prevent warnings */ \
927  }
928 #endif
929 
932 /* end of Bitfield handler macros */
933 
943 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
944 
945 #define _CPU_Priority_Mask( _bit_number ) \
946  ( 1 << (_bit_number) )
947 
948 #endif
949 
964 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
965 
966 #define _CPU_Priority_bits_index( _priority ) \
967  (_priority)
968 
969 #endif
970 
971 /* end of Priority handler macros */
972 
973 /* functions */
974 
982 void _CPU_Initialize(void);
983 
984 typedef void ( *CPU_ISR_raw_handler )( void );
985 
1003  uint32_t vector,
1004  CPU_ISR_raw_handler new_handler,
1005  CPU_ISR_raw_handler *old_handler
1006 );
1007 
1008 typedef void ( *CPU_ISR_handler )( uint32_t );
1009 
1027  uint32_t vector,
1028  CPU_ISR_handler new_handler,
1029  CPU_ISR_handler *old_handler
1030 );
1031 
1039 void *_CPU_Thread_Idle_body( uintptr_t ignored );
1040 
1053 void _CPU_Context_switch(
1054  Context_Control *run,
1055  Context_Control *heir
1056 );
1057 
1073  Context_Control *new_context
1074 ) RTEMS_NO_RETURN;
1075 
1092  Context_Control_fp **fp_context_ptr
1093 );
1094 
1111  Context_Control_fp **fp_context_ptr
1112 );
1113 
1123 typedef struct {
1124  uint32_t processor_state_register;
1125  uint32_t integer_registers [1];
1126  double float_registers [1];
1128 
1134 void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1135 
1173 static inline uint32_t CPU_swap_u32(
1174  uint32_t value
1175 )
1176 {
1177  uint32_t byte1, byte2, byte3, byte4, swapped;
1178 
1179  byte4 = (value >> 24) & 0xff;
1180  byte3 = (value >> 16) & 0xff;
1181  byte2 = (value >> 8) & 0xff;
1182  byte1 = value & 0xff;
1183 
1184  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1185  return swapped;
1186 }
1187 
1194 #define CPU_swap_u16( value ) \
1195  (((value&0xff) << 8) | ((value >> 8)&0xff))
1196 
1202 typedef uint32_t CPU_Counter_ticks;
1203 
1209 uint32_t _CPU_Counter_frequency( void );
1210 
1221 CPU_Counter_ticks _CPU_Counter_read( void );
1222 
1235 static inline CPU_Counter_ticks _CPU_Counter_difference(
1236  CPU_Counter_ticks second,
1237  CPU_Counter_ticks first
1238 )
1239 {
1240  return second - first;
1241 }
1242 
1243 #ifdef RTEMS_SMP
1244 
1257  uint32_t _CPU_SMP_Initialize( void );
1258 
1272  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1273 
1288  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1289 
1300  void _CPU_SMP_Prepare_start_multitasking( void );
1301 
1309  static inline uint32_t _CPU_SMP_Get_current_processor( void )
1310  {
1311  return 123;
1312  }
1313 
1322  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1323 
1335  static inline void _CPU_SMP_Processor_event_broadcast( void )
1336  {
1337  __asm__ volatile ( "" : : : "memory" );
1338  }
1339 
1348  static inline void _CPU_SMP_Processor_event_receive( void )
1349  {
1350  __asm__ volatile ( "" : : : "memory" );
1351  }
1352 
1358  static inline bool _CPU_Context_Get_is_executing(
1359  const Context_Control *context
1360  )
1361  {
1362  return context->is_executing;
1363  }
1364 
1371  static inline void _CPU_Context_Set_is_executing(
1373  bool is_executing
1374  )
1375  {
1376  context->is_executing = is_executing;
1377  }
1378 
1380 typedef uintptr_t CPU_Uint32ptr;
1381 
1382 #endif
1383 
1384 #ifdef __cplusplus
1385 }
1386 #endif
1387 
1388 #endif
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
uint32_t some_integer_register
Definition: cpu.h:320
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
Thread register context.
Definition: cpu.h:196
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:65
void _CPU_Context_restore_fp(Context_Control_fp **fp_context_ptr)
Definition: cpu.c:207
Interrupt stack frame (ISF).
Definition: cpu.h:306
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
uint32_t stack_pointer
Definition: cpu.h:331
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
SPARC basic context.
Definition: cpu.h:242
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1202
#define RTEMS_NO_RETURN
Definition: basedefs.h:101
uint32_t _CPU_ISR_Get_level(void)
Definition: cpu.c:88
unsigned context
Definition: tlb.h:108
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.h:703
bool _CPU_ISR_Is_enabled(uint32_t level)
Returns true if interrupts are enabled in the specified ISR level, otherwise returns false...
Definition: cpu.h:381
void _CPU_Context_restore(Context_Control *new_context) RTEMS_NO_RETURN
Definition: cpu_asm.c:111
uintptr_t CPU_Uint32ptr
Definition: cpu.h:668
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
Basic Definitions.
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
SPARC specific RTEMS ISR installer.
Definition: cpu.h:605
void _CPU_Context_save_fp(Context_Control_fp **fp_context_ptr)
Definition: cpu.c:198
The set of registers that specifies the complete processor state.
Definition: cpu.h:635
Context_Control_fp _CPU_Null_fp_context
Definition: cpu.c:45
uint32_t some_system_register
Definition: cpu.h:325