36 #ifndef _RTEMS_SCORE_CPU_H 37 #define _RTEMS_SCORE_CPU_H 44 #include <rtems/score/no_cpu.h> 59 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE 70 #define CPU_ISR_PASSES_FRAME_POINTER FALSE 107 #if ( NO_CPU_HAS_FPU == 1 ) 108 #define CPU_HARDWARE_FP TRUE 110 #define CPU_HARDWARE_FP FALSE 112 #define CPU_SOFTWARE_FP FALSE 138 #define CPU_ALL_TASKS_ARE_FP TRUE 155 #define CPU_IDLE_TASK_IS_FP FALSE 186 #define CPU_USE_DEFERRED_FP_SWITCH TRUE 198 #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE 211 #define CPU_STACK_GROWS_UP TRUE 218 #define CPU_CACHE_LINE_BYTES 32 231 #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) 244 #define CPU_MODES_INTERRUPT_MASK 0x00000001 250 #define CPU_MAXIMUM_PROCESSORS 32 378 volatile bool is_executing;
391 #define _CPU_Context_Get_SP( _context ) \ 392 (_context)->stack_pointer 402 double some_float_register;
418 uint32_t special_interrupt_register;
473 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) 484 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 496 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 508 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) 516 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE 528 #define CPU_STACK_MINIMUM_SIZE (1024*4) 537 #define CPU_SIZEOF_POINTER 4 550 #define CPU_ALIGNMENT 8 574 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT 589 #define CPU_STACK_ALIGNMENT 0 597 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES 612 #define _CPU_Initialize_vectors() 626 #define _CPU_ISR_Disable( _isr_cookie ) \ 644 #define _CPU_ISR_Enable( _isr_cookie ) \ 662 #define _CPU_ISR_Flash( _isr_cookie ) \ 697 #define _CPU_ISR_Set_level( new_level ) \ 734 #define _CPU_Context_Destroy( _the_thread, _the_context ) \ 775 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ 776 _isr, _entry_point, _is_fp, _tls_area ) \ 795 #define _CPU_Context_Restart_self( _the_context ) \ 796 _CPU_Context_restore( (_the_context) ); 816 #define _CPU_Context_Initialize_fp( _destination ) \ 818 *(*(_destination)) = _CPU_Null_fp_context; \ 834 #define _CPU_Fatal_halt( _source, _error ) \ 857 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE 923 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) 924 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ 943 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) 945 #define _CPU_Priority_Mask( _bit_number ) \ 946 ( 1 << (_bit_number) ) 964 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) 966 #define _CPU_Priority_bits_index( _priority ) \ 984 typedef void ( *CPU_ISR_raw_handler )( void );
1004 CPU_ISR_raw_handler new_handler,
1005 CPU_ISR_raw_handler *old_handler
1008 typedef void ( *CPU_ISR_handler )( uint32_t );
1028 CPU_ISR_handler new_handler,
1029 CPU_ISR_handler *old_handler
1124 uint32_t processor_state_register;
1125 uint32_t integer_registers [1];
1126 double float_registers [1];
1173 static inline uint32_t CPU_swap_u32(
1177 uint32_t byte1, byte2, byte3, byte4, swapped;
1179 byte4 = (value >> 24) & 0xff;
1180 byte3 = (value >> 16) & 0xff;
1181 byte2 = (value >> 8) & 0xff;
1182 byte1 = value & 0xff;
1184 swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1194 #define CPU_swap_u16( value ) \ 1195 (((value&0xff) << 8) | ((value >> 8)&0xff)) 1235 static inline CPU_Counter_ticks _CPU_Counter_difference(
1236 CPU_Counter_ticks second,
1237 CPU_Counter_ticks first
1240 return second - first;
1257 uint32_t _CPU_SMP_Initialize(
void );
1272 bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1288 void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1300 void _CPU_SMP_Prepare_start_multitasking(
void );
1309 static inline uint32_t _CPU_SMP_Get_current_processor(
void )
1322 void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1335 static inline void _CPU_SMP_Processor_event_broadcast(
void )
1337 __asm__ volatile (
"" : : :
"memory" );
1348 static inline void _CPU_SMP_Processor_event_receive(
void )
1350 __asm__ volatile (
"" : : :
"memory" );
1358 static inline bool _CPU_Context_Get_is_executing(
1362 return context->is_executing;
1371 static inline void _CPU_Context_Set_is_executing(
1376 context->is_executing = is_executing;
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
uint32_t some_integer_register
Definition: cpu.h:320
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
Thread register context.
Definition: cpu.h:196
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:65
void _CPU_Context_restore_fp(Context_Control_fp **fp_context_ptr)
Definition: cpu.c:207
Interrupt stack frame (ISF).
Definition: cpu.h:306
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
uint32_t stack_pointer
Definition: cpu.h:331
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
SPARC basic context.
Definition: cpu.h:242
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1202
#define RTEMS_NO_RETURN
Definition: basedefs.h:101
uint32_t _CPU_ISR_Get_level(void)
Definition: cpu.c:88
unsigned context
Definition: tlb.h:108
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_raw_handler(uint32_t vector, CPU_ISR_raw_handler new_handler, CPU_ISR_raw_handler *old_handler)
SPARC specific raw ISR installer.
Definition: cpu.h:703
bool _CPU_ISR_Is_enabled(uint32_t level)
Returns true if interrupts are enabled in the specified ISR level, otherwise returns false...
Definition: cpu.h:381
void _CPU_Context_restore(Context_Control *new_context) RTEMS_NO_RETURN
Definition: cpu_asm.c:111
uintptr_t CPU_Uint32ptr
Definition: cpu.h:668
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
RTEMS_INLINE_ROUTINE void _CPU_ISR_install_vector(uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
SPARC specific RTEMS ISR installer.
Definition: cpu.h:605
void _CPU_Context_save_fp(Context_Control_fp **fp_context_ptr)
Definition: cpu.c:198
The set of registers that specifies the complete processor state.
Definition: cpu.h:635
Context_Control_fp _CPU_Null_fp_context
Definition: cpu.c:45
uint32_t some_system_register
Definition: cpu.h:325