Generic BSP Interrupt Support. More...

Modules
	Interrupt Support
	Intel Cyclone V Interrupt Support.

	Interrupt Support

Files
file	irq.c
	Interrupt support.

file	irq.h
	Dummy interrupt definitions.

file	irq-dispatch.c
	GDB ARM Simulator interrupt support.

file	irq.c
	GDB ARM Simulator interrupt support.

file	irq.h
	LPC176X interrupt definitions.

file	irq.c
	LPC176X interrupt support.

file	irq.h
	LPC24XX interrupt definitions.

file	irq-dispatch.c
	LPC24XX interrupt support.

file	irq.c
	LPC24XX interrupt support.

file	irq-generic.h
	Generic BSP interrupt support API.

file	irq-info.h
	Generic BSP interrupt information API.

file	irq.h
	BSP interrupt support for LM32.

file	irq.h
	interrupt definitions.

file	irq.h
	interrupt definitions.

file	irq.h
	jmr3904 interrupt definitions.

file	irq.h
	Malta Interrupt Definitions.

file	irq.h
	interrupt definitions.

file	irq.h
	interrupt definitions.

file	irq.c
	Interrupt support.

file	irq-generic.c
	Generic BSP interrupt support implementation.

file	irq-info.c
	Generic BSP interrupt information implementation.

file	irq-legacy.c
	Generic BSP interrupt support legacy implementation.

file	irq-lock.c
	BSP interrupt support lock implementation.

file	irq-server.c
	Generic BSP interrupt server implementation.

file	irq-shell.c
	Generic BSP interrupt shell implementation.

Macros
#define	DUMMY_IRQ_WDT 0

#define	DUMMY_IRQ_SOFTWARE 1

#define	DUMMY_IRQ_ARM_CORE_0 2

#define	DUMMY_IRQ_ARM_CORE_1 3

#define	DUMMY_IRQ_TIMER_0 4

#define	DUMMY_IRQ_TIMER_1 5

#define	DUMMY_IRQ_UART_0 6

#define	DUMMY_IRQ_UART_1 7

#define	DUMMY_IRQ_PWM 8

#define	DUMMY_IRQ_I2C_0 9

#define	DUMMY_IRQ_SPI_SSP_0 10

#define	DUMMY_IRQ_SSP_1 11

#define	DUMMY_IRQ_PLL 12

#define	DUMMY_IRQ_RTC 13

#define	DUMMY_IRQ_EINT_0 14

#define	DUMMY_IRQ_EINT_1 15

#define	DUMMY_IRQ_EINT_2 16

#define	DUMMY_IRQ_EINT_3 17

#define	DUMMY_IRQ_ADC_0 18

#define	DUMMY_IRQ_I2C_1 19

#define	DUMMY_IRQ_BOD 20

#define	DUMMY_IRQ_ETHERNET 21

#define	DUMMY_IRQ_USB 22

#define	DUMMY_IRQ_CAN 23

#define	DUMMY_IRQ_SD_MMC 24

#define	DUMMY_IRQ_DMA 25

#define	DUMMY_IRQ_TIMER_2 26

#define	DUMMY_IRQ_TIMER_3 27

#define	DUMMY_IRQ_UART_2 28

#define	DUMMY_IRQ_UART_3 29

#define	DUMMY_IRQ_I2C_2 30

#define	DUMMY_IRQ_I2S 31

#define	DUMMY_IRQ_PRIORITY_VALUE_MIN 0U

#define	DUMMY_IRQ_PRIORITY_VALUE_MAX 15U

#define	BSP_INTERRUPT_VECTOR_MIN DUMMY_IRQ_WDT
	Minimum vector number.

#define	BSP_INTERRUPT_VECTOR_MAX DUMMY_IRQ_I2S
	Maximum vector number.

#define	BSP_INTERRUPT_VECTOR_MIN 0U

#define	LPC176X_IRQ_WDT 0U

#define	LPC176X_IRQ_TIMER_0 1U

#define	LPC176X_IRQ_TIMER_1 2U

#define	LPC176X_IRQ_TIMER_2 3U

#define	LPC176X_IRQ_TIMER_3 4U

#define	LPC176X_IRQ_UART_0 5U

#define	LPC176X_IRQ_UART_1 6U

#define	LPC176X_IRQ_UART_2 7U

#define	LPC176X_IRQ_UART_3 8U

#define	LPC176X_IRQ_PWM_1 9U

#define	LPC176X_IRQ_PLL 16U

#define	LPC176X_IRQ_RTC 17U

#define	LPC176X_IRQ_EINT_0 18U

#define	LPC176X_IRQ_EINT_1 19U

#define	LPC176X_IRQ_EINT_2 20U

#define	LPC176X_IRQ_EINT_3 21U

#define	LPC176X_IRQ_ADC_0 22U

#define	LPC176X_IRQ_BOD 23U

#define	LPC176X_IRQ_USB 24U

#define	LPC176X_IRQ_CAN 25U

#define	LPC176X_IRQ_DMA 26U

#define	LPC176X_IRQ_I2S 27U

#define	LPC176X_IRQ_SD_MMC 29U

#define	LPC176X_IRQ_MCPWM 30U

#define	LPC176X_IRQ_QEI 31U

#define	LPC176X_IRQ_PLL_ALT 32U

#define	LPC176X_IRQ_USB_ACTIVITY 33U

#define	LPC176X_IRQ_CAN_ACTIVITY 34U

#define	LPC176X_IRQ_UART_4 35U

#define	LPC176X_IRQ_GPIO 38U

#define	LPC176X_IRQ_PWM 39U

#define	LPC176X_IRQ_EEPROM 40U

#define	BSP_INTERRUPT_VECTOR_MAX 40

#define	LPC176X_IRQ_PRIORITY_VALUE_MIN 0U

#define	LPC176X_IRQ_PRIORITY_VALUE_MAX 31U

#define	LPC176X_IRQ_PRIORITY_COUNT ( LPC176X_IRQ_PRIORITY_VALUE_MAX + 1U )

#define	LPC176X_IRQ_PRIORITY_HIGHEST LPC176X_IRQ_PRIORITY_VALUE_MIN

#define	LPC176X_IRQ_PRIORITY_LOWEST LPC176X_IRQ_PRIORITY_VALUE_MAX

#define	BSP_INTERRUPT_VECTOR_MIN 0

#define	LPC24XX_IRQ_WDT 0

#define	LPC24XX_IRQ_TIMER_0 1

#define	LPC24XX_IRQ_TIMER_1 2

#define	LPC24XX_IRQ_TIMER_2 3

#define	LPC24XX_IRQ_TIMER_3 4

#define	LPC24XX_IRQ_UART_0 5

#define	LPC24XX_IRQ_UART_1 6

#define	LPC24XX_IRQ_UART_2 7

#define	LPC24XX_IRQ_UART_3 8

#define	LPC24XX_IRQ_PWM_1 9

#define	LPC24XX_IRQ_I2C_0 10

#define	LPC24XX_IRQ_I2C_1 11

#define	LPC24XX_IRQ_I2C_2 12

#define	LPC24XX_IRQ_SPI_SSP_0 14

#define	LPC24XX_IRQ_SSP_1 15

#define	LPC24XX_IRQ_PLL 16

#define	LPC24XX_IRQ_RTC 17

#define	LPC24XX_IRQ_EINT_0 18

#define	LPC24XX_IRQ_EINT_1 19

#define	LPC24XX_IRQ_EINT_2 20

#define	LPC24XX_IRQ_EINT_3 21

#define	LPC24XX_IRQ_ADC_0 22

#define	LPC24XX_IRQ_BOD 23

#define	LPC24XX_IRQ_USB 24

#define	LPC24XX_IRQ_CAN 25

#define	LPC24XX_IRQ_DMA 26

#define	LPC24XX_IRQ_I2S 27

#define	LPC24XX_IRQ_ETHERNET 28

#define	LPC24XX_IRQ_SD_MMC 29

#define	LPC24XX_IRQ_MCPWM 30

#define	LPC24XX_IRQ_QEI 31

#define	LPC24XX_IRQ_PLL_ALT 32

#define	LPC24XX_IRQ_USB_ACTIVITY 33

#define	LPC24XX_IRQ_CAN_ACTIVITY 34

#define	LPC24XX_IRQ_UART_4 35

#define	LPC24XX_IRQ_SSP_2 36

#define	LPC24XX_IRQ_LCD 37

#define	LPC24XX_IRQ_GPIO 38

#define	LPC24XX_IRQ_PWM 39

#define	LPC24XX_IRQ_EEPROM 40

#define	BSP_INTERRUPT_VECTOR_MAX 40

#define	LPC24XX_IRQ_PRIORITY_VALUE_MIN 0

#define	LPC24XX_IRQ_PRIORITY_VALUE_MAX 31

#define	LPC24XX_IRQ_PRIORITY_COUNT (LPC24XX_IRQ_PRIORITY_VALUE_MAX + 1)

#define	LPC24XX_IRQ_PRIORITY_HIGHEST LPC24XX_IRQ_PRIORITY_VALUE_MIN

#define	LPC24XX_IRQ_PRIORITY_LOWEST LPC24XX_IRQ_PRIORITY_VALUE_MAX

#define	BSP_INTERRUPT_VECTOR_MIN 0
	Minimum vector number.

#define	BSP_INTERRUPT_VECTOR_MAX 31
	Maximum vector number.

#define	BSP_INTERRUPT_VECTOR_MIN 0

#define	AU1X00_IRQ_SW0 (MIPS_INTERRUPT_BASE + 0)

#define	AU1X00_IRQ_SW1 (MIPS_INTERRUPT_BASE + 1)

#define	AU1X00_IRQ_IC0_REQ0 (MIPS_INTERRUPT_BASE + 2)

#define	AU1X00_IRQ_IC0_REQ1 (MIPS_INTERRUPT_BASE + 3)

#define	AU1X00_IRQ_IC1_REQ0 (MIPS_INTERRUPT_BASE + 4)

#define	AU1X00_IRQ_IC1_REQ1 (MIPS_INTERRUPT_BASE + 5)

#define	AU1X00_IRQ_PERF (MIPS_INTERRUPT_BASE + 6)

#define	AU1X00_IRQ_CNT (MIPS_INTERRUPT_BASE + 7)

#define	AU1X00_IRQ_IC0_BASE (MIPS_INTERRUPT_BASE + 8)

#define	AU1X00_IRQ_UART0 (MIPS_INTERRUPT_BASE + 8)

#define	AU1X00_IRQ_INTA (MIPS_INTERRUPT_BASE + 9)

#define	AU1X00_IRQ_INTB (MIPS_INTERRUPT_BASE + 10)

#define	AU1X00_IRQ_UART3 (MIPS_INTERRUPT_BASE + 11)

#define	AU1X00_IRQ_INTC (MIPS_INTERRUPT_BASE + 12)

#define	AU1X00_IRQ_INTD (MIPS_INTERRUPT_BASE + 13)

#define	AU1X00_IRQ_DMA0 (MIPS_INTERRUPT_BASE + 14)

#define	AU1X00_IRQ_DMA1 (MIPS_INTERRUPT_BASE + 15)

#define	AU1X00_IRQ_DMA2 (MIPS_INTERRUPT_BASE + 16)

#define	AU1X00_IRQ_DMA3 (MIPS_INTERRUPT_BASE + 17)

#define	AU1X00_IRQ_DMA4 (MIPS_INTERRUPT_BASE + 18)

#define	AU1X00_IRQ_DMA5 (MIPS_INTERRUPT_BASE + 19)

#define	AU1X00_IRQ_DMA6 (MIPS_INTERRUPT_BASE + 20)

#define	AU1X00_IRQ_DMA7 (MIPS_INTERRUPT_BASE + 21)

#define	AU1X00_IRQ_TOY_TICK (MIPS_INTERRUPT_BASE + 22)

#define	AU1X00_IRQ_TOY_MATCH0 (MIPS_INTERRUPT_BASE + 23)

#define	AU1X00_IRQ_TOY_MATCH1 (MIPS_INTERRUPT_BASE + 24)

#define	AU1X00_IRQ_TOY_MATCH2 (MIPS_INTERRUPT_BASE + 25)

#define	AU1X00_IRQ_RTC_TICK (MIPS_INTERRUPT_BASE + 26)

#define	AU1X00_IRQ_RTC_MATCH0 (MIPS_INTERRUPT_BASE + 27)

#define	AU1X00_IRQ_RTC_MATCH1 (MIPS_INTERRUPT_BASE + 28)

#define	AU1X00_IRQ_RTC_MATCH2 (MIPS_INTERRUPT_BASE + 29)

#define	AU1X00_IRQ_PCI_ERR (MIPS_INTERRUPT_BASE + 30)

#define	AU1X00_IRQ_RSV0 (MIPS_INTERRUPT_BASE + 31)

#define	AU1X00_IRQ_USB_DEV (MIPS_INTERRUPT_BASE + 32)

#define	AU1X00_IRQ_USB_SUSPEND (MIPS_INTERRUPT_BASE + 33)

#define	AU1X00_IRQ_USB_HOST (MIPS_INTERRUPT_BASE + 34)

#define	AU1X00_IRQ_AC97_ACSYNC (MIPS_INTERRUPT_BASE + 35)

#define	AU1X00_IRQ_MAC0 (MIPS_INTERRUPT_BASE + 36)

#define	AU1X00_IRQ_MAC1 (MIPS_INTERRUPT_BASE + 37)

#define	AU1X00_IRQ_RSV1 (MIPS_INTERRUPT_BASE + 38)

#define	AU1X00_IRQ_AC97_CMD (MIPS_INTERRUPT_BASE + 39)

#define	AU1X00_IRQ_IC1_BASE (MIPS_INTERRUPT_BASE + 40)

#define	AU1X00_IRQ_GPIO0 (MIPS_INTERRUPT_BASE + 40)

#define	AU1X00_IRQ_GPIO1 (MIPS_INTERRUPT_BASE + 41)

#define	AU1X00_IRQ_GPIO2 (MIPS_INTERRUPT_BASE + 42)

#define	AU1X00_IRQ_GPIO3 (MIPS_INTERRUPT_BASE + 43)

#define	AU1X00_IRQ_GPIO4 (MIPS_INTERRUPT_BASE + 44)

#define	AU1X00_IRQ_GPIO5 (MIPS_INTERRUPT_BASE + 45)

#define	AU1X00_IRQ_GPIO6 (MIPS_INTERRUPT_BASE + 46)

#define	AU1X00_IRQ_GPIO7 (MIPS_INTERRUPT_BASE + 47)

#define	AU1X00_IRQ_GPIO8 (MIPS_INTERRUPT_BASE + 48)

#define	AU1X00_IRQ_GPIO9 (MIPS_INTERRUPT_BASE + 49)

#define	AU1X00_IRQ_GPIO10 (MIPS_INTERRUPT_BASE + 50)

#define	AU1X00_IRQ_GPIO11 (MIPS_INTERRUPT_BASE + 51)

#define	AU1X00_IRQ_GPIO12 (MIPS_INTERRUPT_BASE + 52)

#define	AU1X00_IRQ_GPIO13 (MIPS_INTERRUPT_BASE + 53)

#define	AU1X00_IRQ_GPIO14 (MIPS_INTERRUPT_BASE + 54)

#define	AU1X00_IRQ_GPIO15 (MIPS_INTERRUPT_BASE + 55)

#define	AU1X00_IRQ_GPIO200 (MIPS_INTERRUPT_BASE + 56)

#define	AU1X00_IRQ_GPIO201 (MIPS_INTERRUPT_BASE + 57)

#define	AU1X00_IRQ_GPIO202 (MIPS_INTERRUPT_BASE + 58)

#define	AU1X00_IRQ_GPIO203 (MIPS_INTERRUPT_BASE + 59)

#define	AU1X00_IRQ_GPIO20 (MIPS_INTERRUPT_BASE + 60)

#define	AU1X00_IRQ_GPIO204 (MIPS_INTERRUPT_BASE + 61)

#define	AU1X00_IRQ_GPIO205 (MIPS_INTERRUPT_BASE + 62)

#define	AU1X00_IRQ_GPIO23 (MIPS_INTERRUPT_BASE + 63)

#define	AU1X00_IRQ_GPIO24 (MIPS_INTERRUPT_BASE + 64)

#define	AU1X00_IRQ_GPIO25 (MIPS_INTERRUPT_BASE + 65)

#define	AU1X00_IRQ_GPIO26 (MIPS_INTERRUPT_BASE + 66)

#define	AU1X00_IRQ_GPIO27 (MIPS_INTERRUPT_BASE + 67)

#define	AU1X00_IRQ_GPIO28 (MIPS_INTERRUPT_BASE + 68)

#define	AU1X00_IRQ_GPIO206 (MIPS_INTERRUPT_BASE + 69)

#define	AU1X00_IRQ_GPIO207 (MIPS_INTERRUPT_BASE + 70)

#define	AU1X00_IRQ_GPIO208_215 (MIPS_INTERRUPT_BASE + 71)

#define	AU1X00_MAXIMUM_VECTORS (MIPS_INTERRUPT_BASE + 72)

#define	BSP_INTERRUPT_VECTOR_MAX AU1X00_MAXIMUM_VECTORS

#define	BSP_INTERRUPT_VECTOR_MIN 0

#define	RM5231_MAXIMUM_VECTORS (MIPS_INTERRUPT_BASE+8)

#define	BSP_INTERRUPT_VECTOR_MAX RM5231_MAXIMUM_VECTORS

#define	BSP_INTERRUPT_VECTOR_MIN 0

#define	TX3904_IRQ_INT1 MIPS_INTERRUPT_BASE+0

#define	TX3904_IRQ_INT2 MIPS_INTERRUPT_BASE+1

#define	TX3904_IRQ_INT3 MIPS_INTERRUPT_BASE+2

#define	TX3904_IRQ_INT4 MIPS_INTERRUPT_BASE+3

#define	TX3904_IRQ_INT5 MIPS_INTERRUPT_BASE+4

#define	TX3904_IRQ_INT6 MIPS_INTERRUPT_BASE+5

#define	TX3904_IRQ_INT7 MIPS_INTERRUPT_BASE+6

#define	TX3904_IRQ_DMAC3 MIPS_INTERRUPT_BASE+7

#define	TX3904_IRQ_DMAC2 MIPS_INTERRUPT_BASE+8

#define	TX3904_IRQ_DMAC1 MIPS_INTERRUPT_BASE+9

#define	TX3904_IRQ_DMAC0 MIPS_INTERRUPT_BASE+10

#define	TX3904_IRQ_SIO0 MIPS_INTERRUPT_BASE+11

#define	TX3904_IRQ_SIO1 MIPS_INTERRUPT_BASE+12

#define	TX3904_IRQ_TMR0 MIPS_INTERRUPT_BASE+13

#define	TX3904_IRQ_TMR1 MIPS_INTERRUPT_BASE+14

#define	TX3904_IRQ_TMR2 MIPS_INTERRUPT_BASE+15

#define	TX3904_IRQ_INT0 MIPS_INTERRUPT_BASE+16

#define	TX3904_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+17

#define	TX3904_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+18

#define	TX3904_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+19

#define	BSP_INTERRUPT_VECTOR_MAX TX3904_MAXIMUM_VECTORS

#define	BSP_INTERRUPT_VECTOR_MIN 0

#define	MALTA_CPU_INT_START MIPS_INTERRUPT_BASE+0

#define	MALTA_CPU_INT_SW0 MALTA_CPU_INT_START+0

#define	MALTA_CPU_INT_SW2 MALTA_CPU_INT_START+1

#define	MALTA_CPU_INT0 MALTA_CPU_INT_START+2

#define	MALTA_CPU_INT1 MALTA_CPU_INT_START+3

#define	MALTA_CPU_INT2 MALTA_CPU_INT_START+4

#define	MALTA_CPU_INT3 MALTA_CPU_INT_START+5

#define	MALTA_CPU_INT4 MALTA_CPU_INT_START+6

#define	MALTA_CPU_INT5 MALTA_CPU_INT_START+7

#define	MALTA_CPU_INT_LAST MALTA_CPU_INT5

#define	MALTA_SB_IRQ_START MALTA_CPU_INT_LAST+1

#define	MALTA_SB_IRQ_0 MALTA_SB_IRQ_START+0

#define	MALTA_SB_IRQ_1 MALTA_SB_IRQ_START+1

#define	MALTA_SB_IRQ_2 MALTA_SB_IRQ_START+2

#define	MALTA_SB_IRQ_3 MALTA_SB_IRQ_START+3

#define	MALTA_SB_IRQ_4 MALTA_SB_IRQ_START+4

#define	MALTA_SB_IRQ_5 MALTA_SB_IRQ_START+5

#define	MALTA_SB_IRQ_6 MALTA_SB_IRQ_START+6

#define	MALTA_SB_IRQ_7 MALTA_SB_IRQ_START+7

#define	MALTA_SB_IRQ_8 MALTA_SB_IRQ_START+8

#define	MALTA_SB_IRQ_9 MALTA_SB_IRQ_START+9

#define	MALTA_SB_IRQ_10 MALTA_SB_IRQ_START+10

#define	MALTA_SB_IRQ_11 MALTA_SB_IRQ_START+11

#define	MALTA_SB_IRQ_12 MALTA_SB_IRQ_START+12

#define	MALTA_SB_IRQ_13 MALTA_SB_IRQ_START+13

#define	MALTA_SB_IRQ_14 MALTA_SB_IRQ_START+14

#define	MALTA_SB_IRQ_15 MALTA_SB_IRQ_START+15

#define	MALTA_SB_IRQ_LAST MALTA_SB_IRQ_15

#define	MALTA_PCI_ADP_START MALTA_SB_IRQ_LAST+1

#define	MALTA_PCI_ADP20 MALTA_PCI_ADP_START+0

#define	MALTA_PCI_ADP21 MALTA_PCI_ADP_START+1

#define	MALTA_PCI_ADP22 MALTA_PCI_ADP_START+2

#define	MALTA_PCI_ADP27 MALTA_PCI_ADP_START+3

#define	MALTA_PCI_ADP28 MALTA_PCI_ADP_START+4

#define	MALTA_PCI_ADP29 MALTA_PCI_ADP_START+5

#define	MALTA_PCI_ADP30 MALTA_PCI_ADP_START+6

#define	MALTA_PCI_ADP31 MALTA_PCI_ADP_START+7

#define	MALTA_PCI_ADP_LAST MALTA_PCI_ADP31

#define	BSP_INTERRUPT_VECTOR_MAX MALTA_PCI_ADP_LAST

#define	MALTA_INT_SOUTHBRIDGE_INTR MALTA_CPU_INT0

#define	MALTA_INT_SOUTHBRIDGE_SMI MALTA_CPU_INT1

#define	MALTA_INT_TTY2 MALTA_CPU_INT2

#define	MALTA_INT_COREHI MALTA_CPU_INT3

#define	MALTA_INT_CORELO MALTA_CPU_INT4

#define	MALTA_INT_TICKER MALTA_CPU_INT5

#define	MALTA_IRQ_TIMER_SOUTH_BRIDGE MALTA_SB_IRQ_0

#define	MALTA_IRQ_KEYBOARD_SUPERIO MALTA_SB_IRQ_1

#define	MALTA_IRQ_RESERVED1_SOUTH_BRIDGE MALTA_SB_IRQ_2

#define	MALTA_IRQ_TTY1 MALTA_SB_IRQ_3

#define	MALTA_IRQ_TTY0 MALTA_SB_IRQ_4

#define	MALTA_IRQ_NOT_USED MALTA_SB_IRQ_5

#define	MALTA_IRQ_FLOPPY_SUPERIO MALTA_SB_IRQ_6

#define	MALTA_IRQ_PARALLEL_PORT_SUPERIO MALTA_SB_IRQ_7

#define	MALTA_IRQ_REALTIME_CLOCK_SOUTH_BRIDGE MALTA_SB_IRQ_8

#define	MALTA_IRQ_I2C_SOUTH_BRIDGE MALTA_SB_IRQ_9

#define	MALTA_IRQ_PCI_A_B MALTA_SB_IRQ_10

#define	MALTA_IRQ_PCI_C_D MALTA_SB_IRQ_11

#define	MALTA_IRQ_MOUSE_SUPERIO MALTA_SB_IRQ_12

#define	MALTA_IRQ_RESERVED2_SOUTH_BRIDGE MALTA_SB_IRQ_13

#define	MALTA_IRQ_PRIMARY_IDE MALTA_SB_IRQ_14

#define	MALTA_IRQ_SECONDARY_IDE MALTA_SB_IRQ_15

#define	MALTA_IRQ_SOUTH_BRIDGE MALTA_PCI_ADP20

#define	MALTA_IRQ_ETHERNET MALTA_IRQ_PCI_A_B

#define	MALTA_IRQ_AUDIO MALTA_PCI_ADP22

#define	MALTA_IRQ_CORE_CARD MALTA_PCI_ADP27

#define	MALTA_IRQ_PCI_CONNECTOR_1 MALTA_PCI_ADP28

#define	MALTA_IRQ_PCI_CONNECTOR_2 MALTA_PCI_ADP29

#define	MALTA_IRQ_PCI_CONNECTOR_3 MALTA_PCI_ADP30

#define	MALTA_IRQ_PCI_CONNECTOR_4 MALTA_PCI_ADP31

#define	BSP_INTERRUPT_VECTOR_MIN 0

#define	TX4925_IRQ_RSV1 MIPS_INTERRUPT_BASE+0

#define	TX4925_IRQ_WTE MIPS_INTERRUPT_BASE+1

#define	TX4925_IRQ_INT0 MIPS_INTERRUPT_BASE+2

#define	TX4925_IRQ_INT1 MIPS_INTERRUPT_BASE+3

#define	TX4925_IRQ_INT2 MIPS_INTERRUPT_BASE+4

#define	TX4925_IRQ_INT3 MIPS_INTERRUPT_BASE+5

#define	TX4925_IRQ_INT4 MIPS_INTERRUPT_BASE+6

#define	TX4925_IRQ_INT5 MIPS_INTERRUPT_BASE+7

#define	TX4925_IRQ_INT6 MIPS_INTERRUPT_BASE+8

#define	TX4925_IRQ_INT7 MIPS_INTERRUPT_BASE+9

#define	TX4925_IRQ_RSV2 MIPS_INTERRUPT_BASE+10

#define	TX4925_IRQ_NAND MIPS_INTERRUPT_BASE+11

#define	TX4925_IRQ_SIO0 MIPS_INTERRUPT_BASE+12

#define	TX4925_IRQ_SIO1 MIPS_INTERRUPT_BASE+13

#define	TX4925_IRQ_DMAC0 MIPS_INTERRUPT_BASE+14

#define	TX4925_IRQ_DMAC1 MIPS_INTERRUPT_BASE+15

#define	TX4925_IRQ_DMAC2 MIPS_INTERRUPT_BASE+16

#define	TX4925_IRQ_DMAC3 MIPS_INTERRUPT_BASE+17

#define	TX4925_IRQ_IRC MIPS_INTERRUPT_BASE+18

#define	TX4925_IRQ_PDMAC MIPS_INTERRUPT_BASE+19

#define	TX4925_IRQ_PCIC MIPS_INTERRUPT_BASE+20

#define	TX4925_IRQ_TMR0 MIPS_INTERRUPT_BASE+21

#define	TX4925_IRQ_TMR1 MIPS_INTERRUPT_BASE+22

#define	TX4925_IRQ_TMR2 MIPS_INTERRUPT_BASE+23

#define	TX4925_IRQ_SPI MIPS_INTERRUPT_BASE+24

#define	TX4925_IRQ_RTC MIPS_INTERRUPT_BASE+25

#define	TX4925_IRQ_ACLC MIPS_INTERRUPT_BASE+26

#define	TX4925_IRQ_ACLCPME MIPS_INTERRUPT_BASE+27

#define	TX4925_IRQ_CHI MIPS_INTERRUPT_BASE+28

#define	TX4925_IRQ_PCIERR MIPS_INTERRUPT_BASE+29

#define	TX4925_IRQ_PCIPME MIPS_INTERRUPT_BASE+30

#define	TX4925_IRQ_RSV3 MIPS_INTERRUPT_BASE+31

#define	TX4925_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+32

#define	TX4925_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+33

#define	TX4925_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34

#define	BSP_INTERRUPT_VECTOR_MAX TX4925_MAXIMUM_VECTORS

#define	BSP_INTERRUPT_VECTOR_MIN 0

#define	TX4938_IRQ_ECC MIPS_INTERRUPT_BASE+0

#define	TX4938_IRQ_WTE MIPS_INTERRUPT_BASE+1

#define	TX4938_IRQ_INT0 MIPS_INTERRUPT_BASE+2

#define	TX4938_IRQ_INT1 MIPS_INTERRUPT_BASE+3

#define	TX4938_IRQ_INT2 MIPS_INTERRUPT_BASE+4

#define	TX4938_IRQ_INT3 MIPS_INTERRUPT_BASE+5

#define	TX4938_IRQ_INT4 MIPS_INTERRUPT_BASE+6

#define	TX4938_IRQ_INT5 MIPS_INTERRUPT_BASE+7

#define	TX4938_IRQ_SIO0 MIPS_INTERRUPT_BASE+8

#define	TX4938_IRQ_SIO1 MIPS_INTERRUPT_BASE+9

#define	TX4938_IRQ_DMAC00 MIPS_INTERRUPT_BASE+10

#define	TX4938_IRQ_DMAC01 MIPS_INTERRUPT_BASE+11

#define	TX4938_IRQ_DMAC02 MIPS_INTERRUPT_BASE+12

#define	TX4938_IRQ_DMAC03 MIPS_INTERRUPT_BASE+13

#define	TX4938_IRQ_IRC MIPS_INTERRUPT_BASE+14

#define	TX4938_IRQ_PDMAC MIPS_INTERRUPT_BASE+15

#define	TX4938_IRQ_PCIC MIPS_INTERRUPT_BASE+16

#define	TX4938_IRQ_TMR0 MIPS_INTERRUPT_BASE+17

#define	TX4938_IRQ_TMR1 MIPS_INTERRUPT_BASE+18

#define	TX4938_IRQ_TMR2 MIPS_INTERRUPT_BASE+19

#define	TX4938_IRQ_RSV1 MIPS_INTERRUPT_BASE+20

#define	TX4938_IRQ_NDFMC MIPS_INTERRUPT_BASE+21

#define	TX4938_IRQ_PCIERR MIPS_INTERRUPT_BASE+22

#define	TX4938_IRQ_PCIPMC MIPS_INTERRUPT_BASE+23

#define	TX4938_IRQ_ACLC MIPS_INTERRUPT_BASE+24

#define	TX4938_IRQ_ACLCPME MIPS_INTERRUPT_BASE+25

#define	TX4938_IRQ_ACLCPME MIPS_INTERRUPT_BASE+27

#define	TX4938_IRQ_PCIC1NT MIPS_INTERRUPT_BASE+26

#define	TX4938_IRQ_DMAC10 MIPS_INTERRUPT_BASE+28

#define	TX4938_IRQ_DMAC11 MIPS_INTERRUPT_BASE+29

#define	TX4938_IRQ_DMAC12 MIPS_INTERRUPT_BASE+30

#define	TX4938_IRQ_DMAC13 MIPS_INTERRUPT_BASE+31

#define	TX4938_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+32

#define	TX4938_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+33

#define	TX4938_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34

#define	BSP_INTERRUPT_VECTOR_MAX TX4938_MAXIMUM_VECTORS

#define	BSP_INTERRUPT_VECTOR_MIN MPC55XX_IRQ_MIN

#define	BSP_INTERRUPT_VECTOR_MAX MPC55XX_IRQ_MAX

Functions
void	bsp_interrupt_dispatch (void)
	Interrupt dispatch. More...

void	lpc176x_irq_set_priority (rtems_vector_number vector, unsigned priority)
	Sets the priority according to the current interruption. More...

unsigned	lpc176x_irq_get_priority (rtems_vector_number vector)
	Gets the priority number according to the current interruption. More...

void	lpc24xx_irq_set_priority (rtems_vector_number vector, unsigned priority)

unsigned	lpc24xx_irq_get_priority (rtems_vector_number vector)

void	bsp_interrupt_handler_default (rtems_vector_number vector)
	Default interrupt handler. More...

void	bsp_interrupt_initialize (void)
	Initialize BSP interrupt support. More...

rtems_status_code	bsp_interrupt_facility_initialize (void)
	BSP specific initialization. More...

void	bsp_interrupt_vector_enable (rtems_vector_number vector)
	Enables the interrupt vector with number vector. More...

void	bsp_interrupt_vector_disable (rtems_vector_number vector)
	Disables the interrupt vector with number vector. More...

bool	bsp_interrupt_handler_is_empty (rtems_vector_number vector)
	Is interrupt handler empty. More...

Detailed Description

Generic BSP Interrupt Support.

The BSP interrupt support manages a sequence of interrupt vector numbers ranging from BSP_INTERRUPT_VECTOR_MIN to BSP_INTERRUPT_VECTOR_MAX including the end points. It provides methods to install, remove and dispatch interrupt handlers for each vector number. It implements parts of the RTEMS interrupt manager.

The entry points to a list of interrupt handlers are stored in a table (= handler table).

You have to configure the BSP interrupt support in the <bsp/irq.h> file for each BSP. For a minimum configuration you have to provide BSP_INTERRUPT_VECTOR_MIN and BSP_INTERRUPT_VECTOR_MAX.

For boards with small memory requirements you can define BSP_INTERRUPT_USE_INDEX_TABLE. With an enabled index table the handler table will be accessed via a small index table. You can define the size of the handler table with BSP_INTERRUPT_HANDLER_TABLE_SIZE.

Normally new list entries are allocated from the heap. You may define BSP_INTERRUPT_NO_HEAP_USAGE, if you do not want to use the heap. For this option you have to define BSP_INTERRUPT_USE_INDEX_TABLE as well.

You have to provide some special routines in your BSP (follow the links for the details):

The following now deprecated functions are provided for backward compatibility:

Function Documentation

◆ bsp_interrupt_dispatch()

void bsp_interrupt_dispatch ( void )

Interrupt dispatch.

Called by OS to determine which interrupt occured. Function passes control to interrupt handler.

Returns: Void

◆ bsp_interrupt_facility_initialize()

rtems_status_code bsp_interrupt_facility_initialize ( void )

BSP specific initialization.

This routine will be called form bsp_interrupt_initialize() and shall do the following:

Initialize the facilities that call bsp_interrupt_handler_dispatch(). For example on PowerPC the external exception handler.
Initialize the interrupt controller. You shall set the interrupt controller in a state such that interrupts are disabled for all vectors. The vectors will be enabled with your bsp_interrupt_vector_enable() function and disabled via your bsp_interrupt_vector_disable() function. These functions have to work afterwards.

Returns: On success RTEMS_SUCCESSFUL shall be returned.

BSP specific initialization.

Resets vectored interrupt interface to default state. Disables all interrupts. Set all sources as IRQ (not FIR).

Return values

RTEMS_SUCCESSFUL All is set

◆ bsp_interrupt_handler_default()

void bsp_interrupt_handler_default ( rtems_vector_number vector )

Default interrupt handler.

This routine will be called from bsp_interrupt_handler_dispatch() with the current vector number vector when the handler list for this vector is empty or the vector number is out of range.

Note: This function must cope with arbitrary vector numbers vector.

◆ bsp_interrupt_handler_is_empty()

bool bsp_interrupt_handler_is_empty ( rtems_vector_number vector )

Is interrupt handler empty.

This routine returns true if the handler is empty and has not been initialised else false is returned. The interrupt lock is not used so this call can be used from within interrupts.

Returns: If empty true shall be returned else false is returned.

◆ bsp_interrupt_initialize()

void bsp_interrupt_initialize ( void )

Initialize BSP interrupt support.

You must call this function before you can install, remove and dispatch interrupt handlers. There is no protection against concurrent initialization. This function must be called at most once. The BSP specific bsp_interrupt_facility_initialize() function will be called after all internals are initialized. If the BSP specific initialization fails, then this is a fatal error. The fatal error source is RTEMS_FATAL_SOURCE_BSP and the fatal error code is BSP_FATAL_INTERRUPT_INITIALIZATION.

◆ bsp_interrupt_vector_disable()

void bsp_interrupt_vector_disable ( rtems_vector_number vector )

Disables the interrupt vector with number vector.

This function shall disable the vector at the corresponding facility (in most cases the interrupt controller). It will be called then the last handler is removed for the vector in bsp_interrupt_handler_remove() for example.

Note: The implementation should use bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)) to valdiate the vector number.; You must not install or remove an interrupt handler in this function. This may result in a deadlock.

Disables the interrupt vector with number vector.

Disables HW interrupt for specified vector

Parameters

[in] vector vector of the isr which needs to be disabled.

Return values

RTEMS_INVALID_ID	vector is invalid.
RTEMS_SUCCESSFUL	interrupt source disabled.

◆ bsp_interrupt_vector_enable()

void bsp_interrupt_vector_enable ( rtems_vector_number vector )

Enables the interrupt vector with number vector.

This function shall enable the vector at the corresponding facility (in most cases the interrupt controller). It will be called then the first handler is installed for the vector in bsp_interrupt_handler_install() for example.

Note: The implementation should use bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector)) to valdiate the vector number.; You must not install or remove an interrupt handler in this function. This may result in a deadlock.

Enables the interrupt vector with number vector.

Enables HW interrupt for specified vector

Parameters

[in] vector vector of the isr which needs to be enabled.

Return values

RTEMS_INVALID_ID	vector is invalid.
RTEMS_SUCCESSFUL	interrupt source enabled.

◆ lpc176x_irq_get_priority()

unsigned lpc176x_irq_get_priority ( rtems_vector_number vector )

Gets the priority number according to the current interruption.

Parameters

vector Interrupts to be attended.

Returns: The priority number according to the current interruption.

◆ lpc176x_irq_set_priority()

void lpc176x_irq_set_priority	(	rtems_vector_number	vector,
		unsigned	priority
	)

Sets the priority according to the current interruption.

Parameters

vector	Interrupt to be attended.
priority	Interrupts priority.

Modules

Files

Macros

Functions

Detailed Description

Function Documentation

◆ bsp_interrupt_dispatch()

◆ bsp_interrupt_facility_initialize()

◆ bsp_interrupt_handler_default()

◆ bsp_interrupt_handler_is_empty()

◆ bsp_interrupt_initialize()

◆ bsp_interrupt_vector_disable()

◆ bsp_interrupt_vector_enable()

◆ lpc176x_irq_get_priority()

◆ lpc176x_irq_set_priority()