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#define | BSP_INTERRUPT_VECTOR_MIN 0 |
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#define | MALTA_CPU_INT_START MIPS_INTERRUPT_BASE+0 |
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#define | MALTA_CPU_INT_SW0 MALTA_CPU_INT_START+0 |
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#define | MALTA_CPU_INT_SW2 MALTA_CPU_INT_START+1 |
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#define | MALTA_CPU_INT0 MALTA_CPU_INT_START+2 |
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#define | MALTA_CPU_INT1 MALTA_CPU_INT_START+3 |
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#define | MALTA_CPU_INT2 MALTA_CPU_INT_START+4 |
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#define | MALTA_CPU_INT3 MALTA_CPU_INT_START+5 |
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#define | MALTA_CPU_INT4 MALTA_CPU_INT_START+6 |
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#define | MALTA_CPU_INT5 MALTA_CPU_INT_START+7 |
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#define | MALTA_CPU_INT_LAST MALTA_CPU_INT5 |
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#define | MALTA_SB_IRQ_START MALTA_CPU_INT_LAST+1 |
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#define | MALTA_SB_IRQ_0 MALTA_SB_IRQ_START+0 |
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#define | MALTA_SB_IRQ_1 MALTA_SB_IRQ_START+1 |
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#define | MALTA_SB_IRQ_2 MALTA_SB_IRQ_START+2 |
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#define | MALTA_SB_IRQ_3 MALTA_SB_IRQ_START+3 |
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#define | MALTA_SB_IRQ_4 MALTA_SB_IRQ_START+4 |
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#define | MALTA_SB_IRQ_5 MALTA_SB_IRQ_START+5 |
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#define | MALTA_SB_IRQ_6 MALTA_SB_IRQ_START+6 |
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#define | MALTA_SB_IRQ_7 MALTA_SB_IRQ_START+7 |
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#define | MALTA_SB_IRQ_8 MALTA_SB_IRQ_START+8 |
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#define | MALTA_SB_IRQ_9 MALTA_SB_IRQ_START+9 |
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#define | MALTA_SB_IRQ_10 MALTA_SB_IRQ_START+10 |
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#define | MALTA_SB_IRQ_11 MALTA_SB_IRQ_START+11 |
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#define | MALTA_SB_IRQ_12 MALTA_SB_IRQ_START+12 |
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#define | MALTA_SB_IRQ_13 MALTA_SB_IRQ_START+13 |
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#define | MALTA_SB_IRQ_14 MALTA_SB_IRQ_START+14 |
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#define | MALTA_SB_IRQ_15 MALTA_SB_IRQ_START+15 |
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#define | MALTA_SB_IRQ_LAST MALTA_SB_IRQ_15 |
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#define | MALTA_PCI_ADP_START MALTA_SB_IRQ_LAST+1 |
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#define | MALTA_PCI_ADP20 MALTA_PCI_ADP_START+0 |
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#define | MALTA_PCI_ADP21 MALTA_PCI_ADP_START+1 |
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#define | MALTA_PCI_ADP22 MALTA_PCI_ADP_START+2 |
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#define | MALTA_PCI_ADP27 MALTA_PCI_ADP_START+3 |
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#define | MALTA_PCI_ADP28 MALTA_PCI_ADP_START+4 |
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#define | MALTA_PCI_ADP29 MALTA_PCI_ADP_START+5 |
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#define | MALTA_PCI_ADP30 MALTA_PCI_ADP_START+6 |
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#define | MALTA_PCI_ADP31 MALTA_PCI_ADP_START+7 |
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#define | MALTA_PCI_ADP_LAST MALTA_PCI_ADP31 |
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#define | BSP_INTERRUPT_VECTOR_MAX MALTA_PCI_ADP_LAST |
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#define | MALTA_INT_SOUTHBRIDGE_INTR MALTA_CPU_INT0 |
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#define | MALTA_INT_SOUTHBRIDGE_SMI MALTA_CPU_INT1 |
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#define | MALTA_INT_TTY2 MALTA_CPU_INT2 |
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#define | MALTA_INT_COREHI MALTA_CPU_INT3 |
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#define | MALTA_INT_CORELO MALTA_CPU_INT4 |
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#define | MALTA_INT_TICKER MALTA_CPU_INT5 |
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#define | MALTA_IRQ_TIMER_SOUTH_BRIDGE MALTA_SB_IRQ_0 |
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#define | MALTA_IRQ_KEYBOARD_SUPERIO MALTA_SB_IRQ_1 |
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#define | MALTA_IRQ_RESERVED1_SOUTH_BRIDGE MALTA_SB_IRQ_2 |
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#define | MALTA_IRQ_TTY1 MALTA_SB_IRQ_3 |
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#define | MALTA_IRQ_TTY0 MALTA_SB_IRQ_4 |
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#define | MALTA_IRQ_NOT_USED MALTA_SB_IRQ_5 |
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#define | MALTA_IRQ_FLOPPY_SUPERIO MALTA_SB_IRQ_6 |
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#define | MALTA_IRQ_PARALLEL_PORT_SUPERIO MALTA_SB_IRQ_7 |
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#define | MALTA_IRQ_REALTIME_CLOCK_SOUTH_BRIDGE MALTA_SB_IRQ_8 |
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#define | MALTA_IRQ_I2C_SOUTH_BRIDGE MALTA_SB_IRQ_9 |
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#define | MALTA_IRQ_PCI_A_B MALTA_SB_IRQ_10 |
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#define | MALTA_IRQ_PCI_C_D MALTA_SB_IRQ_11 |
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#define | MALTA_IRQ_MOUSE_SUPERIO MALTA_SB_IRQ_12 |
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#define | MALTA_IRQ_RESERVED2_SOUTH_BRIDGE MALTA_SB_IRQ_13 |
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#define | MALTA_IRQ_PRIMARY_IDE MALTA_SB_IRQ_14 |
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#define | MALTA_IRQ_SECONDARY_IDE MALTA_SB_IRQ_15 |
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#define | MALTA_IRQ_SOUTH_BRIDGE MALTA_PCI_ADP20 |
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#define | MALTA_IRQ_ETHERNET MALTA_IRQ_PCI_A_B |
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#define | MALTA_IRQ_AUDIO MALTA_PCI_ADP22 |
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#define | MALTA_IRQ_CORE_CARD MALTA_PCI_ADP27 |
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#define | MALTA_IRQ_PCI_CONNECTOR_1 MALTA_PCI_ADP28 |
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#define | MALTA_IRQ_PCI_CONNECTOR_2 MALTA_PCI_ADP29 |
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#define | MALTA_IRQ_PCI_CONNECTOR_3 MALTA_PCI_ADP30 |
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#define | MALTA_IRQ_PCI_CONNECTOR_4 MALTA_PCI_ADP31 |
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Malta Interrupt Definitions.