RTEMS  5.0.0
fsl-mpc567x.h
1 /*
2  * Modifications of the original file provided by Freescale are:
3  *
4  * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
5  *
6  * embedded brains GmbH
7  * Obere Lagerstr. 30
8  * 82178 Puchheim
9  * Germany
10  * <info@embedded-brains.de>
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  * notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  * notice, this list of conditions and the following disclaimer in the
19  * documentation and/or other materials provided with the distribution.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 /**************************************************************************/
35 /* FILE NAME: mpc5674f.h COPYRIGHT (c) Freescale 2009 */
36 /* VERSION: 1.04 All Rights Reserved */
37 /* */
38 /* DESCRIPTION: */
39 /* This file contains all of the register and bit field definitions for */
40 /* MPC5674F. */
41 /*========================================================================*/
42 /* UPDATE HISTORY */
43 /* REV AUTHOR DATE DESCRIPTION OF CHANGE */
44 /* --- ----------- --------- --------------------- */
45 /* NOTE: Branch pulled at version 0.87 for mpc5674_c.h version 1.00 */
46 /* 1.00 B. Terry Corrected DECFILT addresses and added */
47 /* 4 additional filters for Rev. 2 */
48 /* 1.01 B. Terry 16/Nov/09 Corrected bit definitions in SIUDIV */
49 /* register. */
50 /* 1.02 B. Terry 19/Nov/09 Added ISEL8, ISEL9, ISEL10, and ISEL11 */
51 /* regs to SIU tag. (Mamba 2 features) */
52 /* 1.03 B. Terry 19/Nov/09 Renamed ISEL10 and ISEL11 to DECFIL1 */
53 /* and DECFIL2 to match RM. */
54 /* 1.04 B. Terry 22/Jan/10 Updated bitfields of MPU RGDx Word2 */
55 /* register to reflect Mamba 2. Added */
56 /* MXCR and MXSR registers to DecFilt. */
57 /* Removed pre-release rev history. */
58 /**************************************************************************/
59 
60 #ifndef _MPC5674F_H_
61 #define _MPC5674F_H_
62 
63 #ifndef ASM
64 
65 #include <stdint.h>
66 
67 #include <mpc55xx/regs-edma.h>
68 
69 #ifdef __cplusplus
70 extern "C" {
71 #endif
72 
73 #ifdef __MWERKS__
74 #pragma push
75 #pragma ANSI_strict off
76 #endif
77 
78 /****************************************************************************/
79 /* MODULE : PBRIDGE_A Peripheral Bridge */
80 /****************************************************************************/
81 
82  struct PBRIDGE_A_tag {
83 
84  union { /* Master Privilege Control Register 0*/
85  uint32_t R;
86  struct {
87  uint32_t MBW0:1; /* z7 Core */
88  uint32_t MTR0:1;
89  uint32_t MTW0:1;
90  uint32_t MPL0:1;
91  uint32_t MBW1:1; /* Nexus */
92  uint32_t MTR1:1;
93  uint32_t MTW1:1;
94  uint32_t MPL1:1;
95  uint32_t MBW2:1; /* Reserved */
96  uint32_t MTR2:1;
97  uint32_t MTW2:1;
98  uint32_t MPL2:1;
99  uint32_t MBW3:1; /* Reserved */
100  uint32_t MTR3:1;
101  uint32_t MTW3:1;
102  uint32_t MPL3:1;
103  uint32_t MBW4:1; /* eDMA A */
104  uint32_t MTR4:1;
105  uint32_t MTW4:1;
106  uint32_t MPL4:1;
107  uint32_t MBW5:1; /* eDMA B */
108  uint32_t MTR5:1;
109  uint32_t MTW5:1;
110  uint32_t MPL5:1;
111  uint32_t MBW6:1; /* FLEXRAY */
112  uint32_t MTR6:1;
113  uint32_t MTW6:1;
114  uint32_t MPL6:1;
115  uint32_t MBW7:1; /* EBI */
116  uint32_t MTR7:1;
117  uint32_t MTW7:1;
118  uint32_t MPL7:1;
119  } B;
120  } MPCR;
121 
122  union { /* Master Privilege Control Register 1 */
123  uint32_t R;
124  struct {
125  uint32_t:32; /* reserved */
126  } B;
127  } MPCR1;
128 
129  uint32_t PBRIDGE_A_reserved0008[6]; /* 0x0008-0x001F */
130 
131  union { /* Peripheral Access Control Register 0 */
132  uint32_t R;
133  struct {
134  uint32_t BW0:1; /* PBRIDGE_A */
135  uint32_t SP0:1;
136  uint32_t WP0:1;
137  uint32_t TP0:1;
138  uint32_t:4; /* Reserved */
139  uint32_t:4; /* Reserved */
140  uint32_t:4; /* Reserved */
141  uint32_t:4; /* Reserved */
142  uint32_t:4; /* Reserved */
143  uint32_t:4; /* Reserved */
144  uint32_t:4; /* Reserved */
145  } B;
146  } PACR0;
147 
148  uint32_t PBRIDGE_A_reserved0024[7]; /* 0x0024-0x003F */
149 
150  union { /* Off-Platform Peripheral Access Control Register 0 */
151  uint32_t R;
152  struct {
153  uint32_t BW0:1; /* FMPLL */
154  uint32_t SP0:1;
155  uint32_t WP0:1;
156  uint32_t TP0:1;
157  uint32_t BW1:1; /* EBI control */
158  uint32_t SP1:1;
159  uint32_t WP1:1;
160  uint32_t TP1:1;
161  uint32_t BW2:1; /* Flash A control */
162  uint32_t SP2:1;
163  uint32_t WP2:1;
164  uint32_t TP2:1;
165  uint32_t BW3:1; /* Flash B control */
166  uint32_t SP3:1;
167  uint32_t WP3:1;
168  uint32_t TP3:1;
169  uint32_t BW4:1; /* SIU */
170  uint32_t SP4:1;
171  uint32_t WP4:1;
172  uint32_t TP4:1;
173  uint32_t:4; /* Reserved */
174  uint32_t:4; /* Reserved */
175  uint32_t:4; /* Reserved */
176  } B;
177  } OPACR0;
178 
179  union { /* Off-Platform Peripheral Access Control Register 1 */
180  uint32_t R;
181  struct {
182  uint32_t BW0:1; /* EMIOS */
183  uint32_t SP0:1;
184  uint32_t WP0:1;
185  uint32_t TP0:1;
186  uint32_t:4; /* Reserved */
187  uint32_t:4; /* Reserved */
188  uint32_t:4; /* Reserved */
189  uint32_t:4; /* Reserved */
190  uint32_t:4; /* Reserved */
191  uint32_t:4; /* Reserved */
192  uint32_t BW7:1; /* PMC */
193  uint32_t SP7:1;
194  uint32_t WP7:1;
195  uint32_t TP7:1;
196  } B;
197  } OPACR1;
198 
199  union { /* Off-Platform Peripheral Access Control Register 2 */
200  uint32_t R;
201  struct {
202  uint32_t BW0:1; /* eTPU */
203  uint32_t SP0:1;
204  uint32_t WP0:1;
205  uint32_t TP0:1;
206  uint32_t:4; /* Reserved */
207  uint32_t BW2:1; /* eTPU PRAM */
208  uint32_t SP2:1;
209  uint32_t WP2:1;
210  uint32_t TP2:1;
211  uint32_t BW3:1; /* eTPU PRAM mirror */
212  uint32_t SP3:1;
213  uint32_t WP3:1;
214  uint32_t TP3:1;
215  uint32_t BW4:1; /* eTPU SCM */
216  uint32_t SP4:1;
217  uint32_t WP4:1;
218  uint32_t TP4:1;
219  uint32_t BW5:1; /* eTPU SCM */
220  uint32_t SP5:1;
221  uint32_t WP5:1;
222  uint32_t TP5:1;
223  uint32_t:4; /* Reserved */
224  uint32_t:4; /* Reserved */
225  } B;
226  } OPACR2;
227 
228  union { /* Off-Platform Peripheral Access Control Register 3 */
229  uint32_t R;
230  struct {
231  uint32_t:4; /* Reserved */
232  uint32_t:4; /* Reserved */
233  uint32_t:4; /* Reserved */
234  uint32_t:4; /* Reserved */
235  uint32_t BW4:1; /* PIT/RTI */
236  uint32_t SP4:1;
237  uint32_t WP4:1;
238  uint32_t TP4:1;
239  uint32_t:4; /* Reserved */
240  uint32_t:4; /* Reserved */
241  uint32_t:4; /* Reserved */
242  } B;
243  } OPACR3;
244 
245  uint32_t PBRIDGE_A_reserved0050[4076]; /* 0x0050-0x3FFF */
246 
247  };
248 
249 /****************************************************************************/
250 /* MODULE : PBRIDGE_B Peripheral Bridge */
251 /****************************************************************************/
252 
253  struct PBRIDGE_B_tag {
254 
255  union { /* Master Privilege Control Register 0 */
256  uint32_t R;
257  struct {
258  uint32_t MBW0:1; /* z7 Core */
259  uint32_t MTR0:1;
260  uint32_t MTW0:1;
261  uint32_t MPL0:1;
262  uint32_t MBW1:1; /* Nexus */
263  uint32_t MTR1:1;
264  uint32_t MTW1:1;
265  uint32_t MPL1:1;
266  uint32_t MBW2:1; /* Reserved */
267  uint32_t MTR2:1;
268  uint32_t MTW2:1;
269  uint32_t MPL2:1;
270  uint32_t MBW3:1; /* Reserved */
271  uint32_t MTR3:1;
272  uint32_t MTW3:1;
273  uint32_t MPL3:1;
274  uint32_t MBW4:1; /* eDMA A */
275  uint32_t MTR4:1;
276  uint32_t MTW4:1;
277  uint32_t MPL4:1;
278  uint32_t MBW5:1; /* eDMA B */
279  uint32_t MTR5:1;
280  uint32_t MTW5:1;
281  uint32_t MPL5:1;
282  uint32_t MBW6:1; /* FLEXRAY */
283  uint32_t MTR6:1;
284  uint32_t MTW6:1;
285  uint32_t MPL6:1;
286  uint32_t MBW7:1; /* EBI */
287  uint32_t MTR7:1;
288  uint32_t MTW7:1;
289  uint32_t MPL7:1;
290  } B;
291  } MPCR;
292 
293  union { /* Master Privilege Control Register 1 */
294  uint32_t R;
295  struct {
296  uint32_t:32; /* Reserved */
297 
298  } B;
299  } MPCR1;
300 
301  uint32_t PBRIDGE_B_reserved0008[6]; /* 0x0008-0x001F */
302 
303  union { /* Peripheral Access Control Register 0 */
304  uint32_t R;
305  struct {
306  uint32_t BW0:1; /* PBRIDGE B */
307  uint32_t SP0:1;
308  uint32_t WP0:1;
309  uint32_t TP0:1;
310  uint32_t BW1:1; /* XBAR */
311  uint32_t SP1:1;
312  uint32_t WP1:1;
313  uint32_t TP1:1;
314  uint32_t:4; /* Reserved */
315  uint32_t:4; /* Reserved */
316  uint32_t BW4:1; /* MPU */
317  uint32_t SP4:1;
318  uint32_t WP4:1;
319  uint32_t TP4:1;
320  uint32_t:4; /* Reserved */
321  uint32_t:4; /* Reserved */
322  uint32_t:4; /* Reserved */
323  } B;
324  } PACR0;
325 
326  union { /* Peripheral Access Control Register 1 */
327  uint32_t R;
328  struct {
329  uint32_t:4; /* Reserved */
330  uint32_t:4; /* Reserved */
331  uint32_t:4; /* Reserved */
332  uint32_t:4; /* Reserved */
333  uint32_t:4; /* Reserved */
334  uint32_t:4; /* Reserved */
335  uint32_t BW6:1; /* SWT */
336  uint32_t SP6:1;
337  uint32_t WP6:1;
338  uint32_t TP6:1;
339  uint32_t BW7:1; /* STM */
340  uint32_t SP7:1;
341  uint32_t WP7:1;
342  uint32_t TP7:1;
343  } B;
344  } PACR1;
345 
346  union { /* Peripheral Access Control Register 2 */
347  uint32_t R;
348  struct {
349  uint32_t BW0:1; /* ECSM */
350  uint32_t SP0:1;
351  uint32_t WP0:1;
352  uint32_t TP0:1;
353  uint32_t BW1:1; /* eDMA A */
354  uint32_t SP1:1;
355  uint32_t WP1:1;
356  uint32_t TP1:1;
357  uint32_t BW2:1; /* INTC */
358  uint32_t SP2:1;
359  uint32_t WP2:1;
360  uint32_t TP2:1;
361  uint32_t:4; /* Reserved */
362  uint32_t:4; /* Reserved */
363  uint32_t BW5:1; /* eDMA B */
364  uint32_t SP5:1;
365  uint32_t WP5:1;
366  uint32_t TP5:1;
367  uint32_t:4; /* Reserved */
368  uint32_t:4; /* Reserved */
369  } B;
370  } PACR2;
371 
372  uint32_t PBRIDGE_B_reserved002C[5]; /* 0x002C-0x003F */
373 
374  union { /* Off-Platform Peripheral Access Control Register 0 */
375  uint32_t R;
376  struct {
377  uint32_t BW0:1; /* eQADC A */
378  uint32_t SP0:1;
379  uint32_t WP0:1;
380  uint32_t TP0:1;
381  uint32_t BW1:1; /* eQADC B */
382  uint32_t SP1:1;
383  uint32_t WP1:1;
384  uint32_t TP1:1;
385  uint32_t BW2:1; /* Decimation Filters A, B, C, D */
386  uint32_t SP2:1;
387  uint32_t WP2:1;
388  uint32_t TP2:1;
389  uint32_t:4; /* Reserved */
390  uint32_t BW4:1; /* DSPI_A */
391  uint32_t SP4:1;
392  uint32_t WP4:1;
393  uint32_t TP4:1;
394  uint32_t BW5:1; /* DSPI_B */
395  uint32_t SP5:1;
396  uint32_t WP5:1;
397  uint32_t TP5:1;
398  uint32_t BW6:1; /* DSPI_C */
399  uint32_t SP6:1;
400  uint32_t WP6:1;
401  uint32_t TP6:1;
402  uint32_t BW7:1; /* DSPI_D */
403  uint32_t SP7:1;
404  uint32_t WP7:1;
405  uint32_t TP7:1;
406  } B;
407  } OPACR0;
408 
409  union { /* Off-Platform Peripheral Access Control Register 1 */
410  uint32_t R;
411  struct {
412  uint32_t:4; /* Reserved */
413  uint32_t:4; /* Reserved */
414  uint32_t:4; /* Reserved */
415  uint32_t:4; /* Reserved */
416  uint32_t BW4:1; /* ESCI_A */
417  uint32_t SP4:1;
418  uint32_t WP4:1;
419  uint32_t TP4:1;
420  uint32_t BW5:1; /* ESCI_B */
421  uint32_t SP5:1;
422  uint32_t WP5:1;
423  uint32_t TP5:1;
424  uint32_t BW6:1; /* ESCI_C */
425  uint32_t SP6:1;
426  uint32_t WP6:1;
427  uint32_t TP6:1;
428  uint32_t:4; /* Reserved */
429  } B;
430  } OPACR1;
431 
432  union { /* Off-Platform Peripheral Access Control Register 2 */
433  uint32_t R;
434  struct {
435  uint32_t BW0:1; /* FlexCAN_A */
436  uint32_t SP0:1;
437  uint32_t WP0:1;
438  uint32_t TP0:1;
439  uint32_t BW1:1; /* FlexCAN_B */
440  uint32_t SP1:1;
441  uint32_t WP1:1;
442  uint32_t TP1:1;
443  uint32_t BW2:1; /* FlexCAN_C */
444  uint32_t SP2:1;
445  uint32_t WP2:1;
446  uint32_t TP2:1;
447  uint32_t BW3:1; /* FlexCAN_D */
448  uint32_t SP3:1;
449  uint32_t WP3:1;
450  uint32_t TP3:1;
451  uint32_t:4; /* Reserved */
452  uint32_t:4; /* Reserved */
453  uint32_t:4; /* Reserved */
454  uint32_t:4; /* Reserved */
455  } B;
456  } OPACR2;
457 
458  union { /* Off-Platform Peripheral Access Control Register 3 */
459  uint32_t R;
460  struct {
461  uint32_t BW0:1; /* FlexRAY */
462  uint32_t SP0:1;
463  uint32_t WP0:1;
464  uint32_t TP0:1;
465  uint32_t:4; /* Reserved */
466  uint32_t:4; /* Reserved */
467  uint32_t BW3:1; /* Temp Sensor */
468  uint32_t SP3:1;
469  uint32_t WP3:1;
470  uint32_t TP3:1;
471  uint32_t:4; /* Reserved */
472  uint32_t:4; /* Reserved */
473  uint32_t:4; /* Reserved */
474  uint32_t BW7:1; /* BAM */
475  uint32_t SP7:1;
476  uint32_t WP7:1;
477  uint32_t TP7:1;
478  } B;
479  } OPACR3;
480 
481  uint32_t PBRIDGE_B_reserved0050[4076]; /* 0x0050-0x3FFF */
482 
483  };
484 
485 /****************************************************************************/
486 /* MODULE : FMPLL */
487 /****************************************************************************/
488 
489  struct FMPLL_tag {
490 
491  uint32_t FMPLL_reserved0000; /* 0x0000-0x0003 */
492 
493  union FMPLL_SYNSR_tag { /* FMPLL Synthesizer Status Register */
494  uint32_t R;
495  struct {
496  uint32_t:22;
497  uint32_t LOLF:1;
498  uint32_t LOC:1;
499  uint32_t MODE:1;
500  uint32_t PLLSEL:1;
501  uint32_t PLLREF:1;
502  uint32_t LOCKS:1;
503  uint32_t LOCK:1;
504  uint32_t LOCF:1;
505  uint32_t CALDONE:1;
506  uint32_t CALPASS:1;
507  } B;
508  } SYNSR;
509 
510  union FMPLL_ESYNCR1_tag {/* FMPLL Enhanced Synthesizer Control Register 1 */
511  uint32_t R;
512  struct {
513  uint32_t:1;
514  uint32_t CLKCFG:3;
515  uint32_t:8;
516  uint32_t EPREDIV:4;
517  uint32_t :8;
518  uint32_t EMFD:8;
519  } B;
520  } ESYNCR1;
521 
522  union FMPLL_ESYNCR2_tag {/* FMPLL Enhanced Synthesizer Control Register 2 */
523  uint32_t R;
524  struct {
525  uint32_t:8;
526  uint32_t LOCEN:1;
527  uint32_t LOLRE:1;
528  uint32_t LOCRE:1;
529  uint32_t LOLIRQ:1;
530  uint32_t LOCIRQ:1;
531  uint32_t:1;
532  uint32_t ERATE:2;
533  uint32_t CLKCFG_DIS:1;
534  uint32_t:4;
535  uint32_t EDEPTH:3;
536  uint32_t:2;
537  uint32_t ERFD:6;
538  } B;
539  } ESYNCR2;
540 
541  uint32_t FMPLL_reserved0010[4092]; /* 0x0010-0x3FFF */
542 
543  };
544 
545 /****************************************************************************/
546 /* MODULE : External Bus Interface (EBI) */
547 /****************************************************************************/
548 
549  struct EBI_CS_tag {
550  uint32_t ebi_cs_reserved [2];
551  };
552 
553  struct EBI_CAL_CS_tag {
554  union { /* Calibration Base Register Bank */
555  uint32_t R;
556  struct {
557  uint32_t BA:17;
558  uint32_t:3;
559  uint32_t PS:1;
560  uint32_t:3;
561  uint32_t AD_MUX:1;
562  uint32_t BL:1;
563  uint32_t WEBS:1;
564  uint32_t TBDIP:1;
565  uint32_t:1;
566  uint32_t SETA:1;
567  uint32_t BI:1;
568  uint32_t V:1;
569  } B;
570  } BR;
571 
572  union { /* Calibration Option Register Bank */
573  uint32_t R;
574  struct {
575  uint32_t AM:17;
576  uint32_t:7;
577  uint32_t SCY:4;
578  uint32_t:1;
579  uint32_t BSCY:2;
580  uint32_t:1;
581  } B;
582  } OR;
583  };
584 
585  struct EBI_tag {
586 
587  union EBI_MCR_tag { /* Module Configuration Register */
588  uint32_t R;
589  struct {
590  uint32_t:16;
591  uint32_t ACGE:1;
592  uint32_t:8;
593  uint32_t MDIS:1;
594  uint32_t:3;
595  uint32_t D16_31:1;
596  uint32_t AD_MUX:1;
597  uint32_t DBM:1;
598  } B;
599  } MCR;
600 
601  uint32_t EBI_reserved0004; /* 0x0004-0x0007 */
602 
603  union { /* Transfer Error Status Register */
604  uint32_t R;
605  struct {
606  uint32_t:30;
607  uint32_t TEAF:1;
608  uint32_t BMTF:1;
609  } B;
610  } TESR;
611 
612  union { /* Bus Monitor Control Register */
613  uint32_t R;
614  struct {
615  uint32_t:16;
616  uint32_t BMT:8;
617  uint32_t BME:1;
618  uint32_t:7;
619  } B;
620  } BMCR;
621 
622  /* Base/Option registers */
623  struct EBI_CS_tag CS[4];
624 
625  uint32_t EBI_reserved0030[4]; /* 0x0030-0x003F */
626 
627  /* Calibration registers */
628  struct EBI_CAL_CS_tag CAL_CS[4];
629 
630  uint32_t EBI_reserved0060[4000]; /* 0x0060-0x3FFF */
631 
632  };
633 
634 /****************************************************************************/
635 /* MODULE : FLASH */
636 /****************************************************************************/
637 
638  struct FLASH_tag {
639 
640  union { /* Module Configuration Register */
641  uint32_t R;
642  struct {
643  uint32_t:5;
644  uint32_t SIZE:3;
645  uint32_t:1;
646  uint32_t LAS:3;
647  uint32_t:3;
648  uint32_t MAS:1;
649  uint32_t EER:1;
650  uint32_t RWE:1;
651  uint32_t SBC:1;
652  uint32_t:1;
653  uint32_t PEAS:1;
654  uint32_t DONE:1;
655  uint32_t PEG:1;
656  uint32_t:4;
657  uint32_t PGM:1;
658  uint32_t PSUS:1;
659  uint32_t ERS:1;
660  uint32_t ESUS:1;
661  uint32_t EHV:1;
662  } B;
663  } MCR;
664 
665  union LMLR_tag { /* Low/Mid Address Space Block Locking Register */
666  uint32_t R;
667  struct {
668  uint32_t LME:1;
669  uint32_t:10;
670  uint32_t SLOCK:1;
671  uint32_t:2;
672  uint32_t MLOCK:2;
673  uint32_t:6;
674  uint32_t LLOCK:10;
675  } B;
676  } LMLR; /* Legacy naming - refer to LML in Reference Manual */
677 
678  union HLR_tag { /* High Address Space Block Locking Register */
679  uint32_t R;
680  struct {
681  uint32_t HBE:1;
682  uint32_t:25;
683  uint32_t HBLOCK:6; /* Legacy naming - refer to HLOCK in Reference Manual */
684  } B;
685  } HLR; /* Legacy naming - refer to HBL in Reference Manual */
686 
687  union SLMLR_tag { /* Secondary Low/Mid Block Locking Register */
688  uint32_t R;
689  struct {
690  uint32_t SLE:1;
691  uint32_t:10;
692  uint32_t SSLOCK:1;
693  uint32_t:2;
694  uint32_t SMLOCK:2;
695  uint32_t:6;
696  uint32_t SLLOCK:10;
697  } B;
698  } SLMLR; /* Legacy naming - refer to SLL in Reference Manual */
699 
700  union { /* Low/Mid Address Space Block Select Register */
701  uint32_t R;
702  struct {
703  uint32_t:14;
704  uint32_t MSEL:2;
705  uint32_t:6;
706  uint32_t LSEL:10;
707  } B;
708  } LMSR; /* Legacy naming - refer to LMS in Reference Manual */
709 
710  union { /* High Address Space Block Select Register */
711  uint32_t R;
712  struct {
713  uint32_t:26;
714  uint32_t HBSEL:6; /* Legacy naming - refer to HSEL in Reference Manual */
715  } B;
716  } HSR; /* Legacy naming - refer to HBS in Reference Manual */
717 
718  union { /* Address Register */
719  uint32_t R;
720  struct {
721  uint32_t SAD:1;
722  uint32_t:13;
723  uint32_t ADDR:15;
724  uint32_t:3;
725  } B;
726  } AR; /* Legacy naming - refer to ADR in Reference Manual */
727 
728  union { /* Platform Flash Configuration Register 1 */
729  uint32_t R;
730  struct {
731  uint32_t:7;
732  uint32_t M8PFE:1; /* z7 Nexus */
733  uint32_t:1; /* EBI Testing - Reserved */
734  uint32_t M6PFE:1; /* FlexRay */
735  uint32_t M5PFE:1; /* eDMA_B */
736  uint32_t M4PFE:1; /* eDMA_A */
737  uint32_t:1; /* Reserved */
738  uint32_t:1; /* Reserved */
739  uint32_t:1; /* Reserved */
740  uint32_t M0PFE:1; /* z7 Core */
741  uint32_t APC:3;
742  uint32_t WWSC:2;
743  uint32_t RWSC:3;
744  uint32_t:1;
745  uint32_t DPFEN:1;
746  uint32_t:1;
747  uint32_t IPFEN:1;
748  uint32_t:1;
749  uint32_t PFLIM:2;
750  uint32_t BFEN:1;
751  } B;
752  } BIUCR; /* Legacy naming - PFCR1 */
753 
754  union { /*Platform Flash Access Protection Register */
755  uint32_t R;
756  struct {
757  uint32_t:14;
758  uint32_t M8AP:2; /* z7 Nexus */
759  uint32_t:2; /* EBI Testing - Reserved */
760  uint32_t M6AP:2; /* FlexRay */
761  uint32_t M5AP:2; /* eDMA_B */
762  uint32_t M4AP:2; /* eDMA_A */
763  uint32_t:2; /* Reserved */
764  uint32_t:2; /* Reserved */
765  uint32_t:2; /* Reserved */
766  uint32_t M0AP:2; /* z7 Core */
767  } B;
768  } BIUAPR; /* Legacy naming - refer to PFAPR in Reference Manual */
769 
770  union { /* Platform Flash Configuration Register 2 */
771  uint32_t R;
772  struct {
773  uint32_t LBCFG:2;
774  uint32_t:30;
775  } B;
776  } BIUCR2;
777 
778  uint32_t FLASH_reserved0028[4086]; /* 0x0028-0x3FFF */
779  };
780 
781 /****************************************************************************/
782 /* MODULE : SIU */
783 /****************************************************************************/
784  struct SIU_tag {
785  int32_t SIU_reserved0000 /* 0x0000-0x0003 */;
786 
787  union { /* MCU ID Register */
788  uint32_t R;
789  struct {
790  uint32_t PARTNUM:16;
791  uint32_t PKG:4;
792  uint32_t:4;
793  uint32_t MAJOR_REV:4;
794  uint32_t MINOR_REV:4;
795  } B;
796  } MIDR;
797 
798  int32_t SIU_reserved0008; /* 0x0008-0x000B */
799 
800  union { /* Reset Status Register */
801  uint32_t R;
802  struct {
803  uint32_t PORS:1;
804  uint32_t ERS:1;
805  uint32_t LLRS:1;
806  uint32_t LCRS:1;
807  uint32_t WDRS:1;
808  uint32_t CRS:1;
809  uint32_t SWTRS:1;
810  uint32_t:7;
811  uint32_t SSRS:1;
812  uint32_t SERF:1;
813  uint32_t WKPCFG:1;
814  uint32_t:11;
815  uint32_t ABR:1;
816  uint32_t BOOTCFG:2;
817  uint32_t RGF:1;
818  } B;
819  } RSR;
820 
821  union { /* System Reset Control Register */
822  uint32_t R;
823  struct {
824  uint32_t SSR:1;
825  uint32_t SER:1;
826  uint32_t:30; // Removed CRE bit
827  } B;
828  } SRCR;
829 
830  union SIU_EISR_tag { /* External Interrupt Status Register */
831  uint32_t R;
832  struct {
833  uint32_t NMI:1;
834  uint32_t:15;
835  uint32_t EIF15:1;
836  uint32_t EIF14:1;
837  uint32_t EIF13:1;
838  uint32_t EIF12:1;
839  uint32_t EIF11:1;
840  uint32_t EIF10:1;
841  uint32_t EIF9:1;
842  uint32_t EIF8:1;
843  uint32_t EIF7:1;
844  uint32_t EIF6:1;
845  uint32_t EIF5:1;
846  uint32_t EIF4:1;
847  uint32_t EIF3:1;
848  uint32_t EIF2:1;
849  uint32_t EIF1:1;
850  uint32_t EIF0:1;
851  } B;
852  } EISR;
853 
854  union SIU_DIRER_tag { /* DMA/Interrupt Request Enable Register */
855  uint32_t R;
856  struct {
857  uint32_t NMISEL8:1;
858  uint32_t:7;
859  uint32_t NMISEL0:1;
860  uint32_t:7;
861  uint32_t EIRE15:1;
862  uint32_t EIRE14:1;
863  uint32_t EIRE13:1;
864  uint32_t EIRE12:1;
865  uint32_t EIRE11:1;
866  uint32_t EIRE10:1;
867  uint32_t EIRE9:1;
868  uint32_t EIRE8:1;
869  uint32_t EIRE7:1;
870  uint32_t EIRE6:1;
871  uint32_t EIRE5:1;
872  uint32_t EIRE4:1;
873  uint32_t EIRE3:1;
874  uint32_t EIRE2:1;
875  uint32_t EIRE1:1;
876  uint32_t EIRE0:1;
877  } B;
878  } DIRER;
879 
880  union SIU_DIRSR_tag { /* DMA/Interrupt Request Select Register */
881  uint32_t R;
882  struct {
883  uint32_t:28;
884  uint32_t DIRS3:1;
885  uint32_t DIRS2:1;
886  uint32_t DIRS1:1;
887  uint32_t DIRS0:1;
888  } B;
889  } DIRSR;
890 
891  union { /* Overrun Status Register */
892  uint32_t R;
893  struct {
894  uint32_t:16;
895  uint32_t OVF15:1;
896  uint32_t OVF14:1;
897  uint32_t OVF13:1;
898  uint32_t OVF12:1;
899  uint32_t OVF11:1;
900  uint32_t OVF10:1;
901  uint32_t OVF9:1;
902  uint32_t OVF8:1;
903  uint32_t OVF7:1;
904  uint32_t OVF6:1;
905  uint32_t OVF5:1;
906  uint32_t OVF4:1;
907  uint32_t OVF3:1;
908  uint32_t OVF2:1;
909  uint32_t OVF1:1;
910  uint32_t OVF0:1;
911  } B;
912  } OSR;
913 
914  union SIU_ORER_tag { /* Overrun Request Enable Register */
915  uint32_t R;
916  struct {
917  uint32_t:16;
918  uint32_t ORE15:1;
919  uint32_t ORE14:1;
920  uint32_t ORE13:1;
921  uint32_t ORE12:1;
922  uint32_t ORE11:1;
923  uint32_t ORE10:1;
924  uint32_t ORE9:1;
925  uint32_t ORE8:1;
926  uint32_t ORE7:1;
927  uint32_t ORE6:1;
928  uint32_t ORE5:1;
929  uint32_t ORE4:1;
930  uint32_t ORE3:1;
931  uint32_t ORE2:1;
932  uint32_t ORE1:1;
933  uint32_t ORE0:1;
934  } B;
935  } ORER;
936 
937  union SIU_IREER_tag { /* External IRQ Rising-Edge Event Enable Register */
938  uint32_t R;
939  struct {
940  uint32_t IREE_NMI8:1;
941  uint32_t:7;
942  uint32_t IREE_NMI0:1;
943  uint32_t:7;
944  uint32_t IREE15:1;
945  uint32_t IREE14:1;
946  uint32_t IREE13:1;
947  uint32_t IREE12:1;
948  uint32_t IREE11:1;
949  uint32_t IREE10:1;
950  uint32_t IREE9:1;
951  uint32_t IREE8:1;
952  uint32_t IREE7:1;
953  uint32_t IREE6:1;
954  uint32_t IREE5:1;
955  uint32_t IREE4:1;
956  uint32_t IREE3:1;
957  uint32_t IREE2:1;
958  uint32_t IREE1:1;
959  uint32_t IREE0:1;
960  } B;
961  } IREER;
962 
963  union SIU_IFEER_tag { /* External IRQ Falling-Edge Event Enable Register */
964  uint32_t R;
965  struct {
966  uint32_t IFEE_NMI8:1;
967  uint32_t:7;
968  uint32_t IFEE_NMI0:1;
969  uint32_t:7;
970  uint32_t IFEE15:1;
971  uint32_t IFEE14:1;
972  uint32_t IFEE13:1;
973  uint32_t IFEE12:1;
974  uint32_t IFEE11:1;
975  uint32_t IFEE10:1;
976  uint32_t IFEE9:1;
977  uint32_t IFEE8:1;
978  uint32_t IFEE7:1;
979  uint32_t IFEE6:1;
980  uint32_t IFEE5:1;
981  uint32_t IFEE4:1;
982  uint32_t IFEE3:1;
983  uint32_t IFEE2:1;
984  uint32_t IFEE1:1;
985  uint32_t IFEE0:1;
986  } B;
987  } IFEER;
988 
989  union SIU_IDFR_tag { /* External IRQ Digital Filter Register */
990  uint32_t R;
991  struct {
992  uint32_t:28;
993  uint32_t DFL:4;
994  } B;
995  } IDFR;
996 
997  union { /* External IRQ Filtered Input Register */
998  uint32_t R;
999  struct {
1000  uint32_t FI31:1;
1001  uint32_t FI30:1;
1002  uint32_t FI29:1;
1003  uint32_t FI28:1;
1004  uint32_t FI27:1;
1005  uint32_t FI26:1;
1006  uint32_t FI25:1;
1007  uint32_t FI24:1;
1008  uint32_t FI23:1;
1009  uint32_t FI22:1;
1010  uint32_t FI21:1;
1011  uint32_t FI20:1;
1012  uint32_t FI19:1;
1013  uint32_t FI18:1;
1014  uint32_t FI17:1;
1015  uint32_t FI16:1;
1016  uint32_t FI15:1;
1017  uint32_t FI14:1;
1018  uint32_t FI13:1;
1019  uint32_t FI12:1;
1020  uint32_t FI11:1;
1021  uint32_t FI10:1;
1022  uint32_t FI9:1;
1023  uint32_t FI8:1;
1024  uint32_t FI7:1;
1025  uint32_t FI6:1;
1026  uint32_t FI5:1;
1027  uint32_t FI4:1;
1028  uint32_t FI3:1;
1029  uint32_t FI2:1;
1030  uint32_t FI1:1;
1031  uint32_t FI0:1;
1032  } B;
1033  } IFIR;
1034 
1035  int32_t SIU_reserved0038[2]; /* 0x0038-0x003F */
1036 
1037  union SIU_PCR_tag { /* Pad Configuration Registers */
1038  uint16_t R;
1039  struct {
1040  uint16_t:3;
1041  uint16_t PA:3;
1042  uint16_t OBE:1;
1043  uint16_t IBE:1;
1044  uint16_t DSC:2;
1045  uint16_t ODE:1;
1046  uint16_t HYS:1;
1047  uint16_t SRC:2;
1048  uint16_t WPE:1;
1049  uint16_t WPS:1;
1050  } B;
1051  } PCR[512];
1052 
1053  int16_t SIU_reserved0440[224]; /* 0x0440-0x05FF */
1054 
1055  union { /* GPIO Pin Data Output Registers */
1056  uint8_t R;
1057  struct {
1058  uint8_t:7;
1059  uint8_t PDO:1;
1060  } B;
1061  } GPDO[512];
1062 
1063  union { /* GPIO Pin Data Input Registers */
1064  uint8_t R;
1065  struct {
1066  uint8_t:7;
1067  uint8_t PDI:1;
1068  } B;
1069  } GPDI[256];
1070 
1071  uint32_t SIU_reserved0900; /* 0x0900-0x0903 */
1072 
1073  union { /* External IRQ Input Select Register */
1074  uint32_t R;
1075  struct {
1076  uint32_t ESEL15:2;
1077  uint32_t ESEL14:2;
1078  uint32_t ESEL13:2;
1079  uint32_t ESEL12:2;
1080  uint32_t ESEL11:2;
1081  uint32_t ESEL10:2;
1082  uint32_t ESEL9:2;
1083  uint32_t ESEL8:2;
1084  uint32_t ESEL7:2;
1085  uint32_t ESEL6:2;
1086  uint32_t ESEL5:2;
1087  uint32_t ESEL4:2;
1088  uint32_t ESEL3:2;
1089  uint32_t ESEL2:2;
1090  uint32_t ESEL1:2;
1091  uint32_t ESEL0:2;
1092  } B;
1093  } EIISR;
1094 
1095  union { /* DSPI Input Select Register */
1096  uint32_t R;
1097  struct {
1098  uint32_t SINSELA:2;
1099  uint32_t SSSELA:2;
1100  uint32_t SCKSELA:2;
1101  uint32_t TRIGSELA:2;
1102  uint32_t SINSELB:2;
1103  uint32_t SSSELB:2;
1104  uint32_t SCKSELB:2;
1105  uint32_t TRIGSELB:2;
1106  uint32_t SINSELC:2;
1107  uint32_t SSSELC:2;
1108  uint32_t SCKSELC:2;
1109  uint32_t TRIGSELC:2;
1110  uint32_t SINSELD:2;
1111  uint32_t SSSELD:2;
1112  uint32_t SCKSELD:2;
1113  uint32_t TRIGSELD:2;
1114  } B;
1115  } DISR;
1116 
1117  int32_t SIU_reserved090C; /* 0x090C-0x090F */
1118 
1119  union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */
1120  uint32_t R;
1121  struct {
1122  uint32_t:1;
1123  uint32_t CTSEL5_0:7;
1124  uint32_t:1;
1125  uint32_t CTSEL4_0:7;
1126  uint32_t:1;
1127  uint32_t CTSEL3_0:7;
1128  uint32_t:1;
1129  uint32_t CTSEL2_0:7;
1130  } B;
1131  } ISEL4;
1132 
1133  union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */
1134  uint32_t R;
1135  struct {
1136  uint32_t:1;
1137  uint32_t CTSEL1_0:7;
1138  uint32_t:1;
1139  uint32_t CTSEL0_0:7;
1140  uint32_t:16;
1141  } B;
1142  } ISEL5;
1143 
1144  union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */
1145  uint32_t R;
1146  struct {
1147  uint32_t:1;
1148  uint32_t CTSEL5_1:7;
1149  uint32_t:1;
1150  uint32_t CTSEL4_1:7;
1151  uint32_t:1;
1152  uint32_t CTSEL3_1:7;
1153  uint32_t:1;
1154  uint32_t CTSEL2_1:7;
1155  } B;
1156  } ISEL6;
1157 
1158  union { /* eQADC Command FIFO Trigger Source Select - IMUX Select Registers */
1159  uint32_t R;
1160  struct {
1161  uint32_t:1;
1162  uint32_t CTSEL1_1:7;
1163  uint32_t:1;
1164  uint32_t CTSEL0_1:7;
1165  uint32_t:16;
1166  } B;
1167  } ISEL7;
1168 
1169  union { /* eTPU Input Select Register */
1170  uint32_t R;
1171  struct {
1172  uint32_t:11;
1173  uint32_t ETPU29:1;
1174  uint32_t:3;
1175  uint32_t ETPU28:1;
1176  uint32_t:3;
1177  uint32_t ETPU27:1;
1178  uint32_t:3;
1179  uint32_t ETPU26:1;
1180  uint32_t:3;
1181  uint32_t ETPU25:1;
1182  uint32_t:3;
1183  uint32_t ETPU24:1;
1184  } B;
1185  } ISEL8;
1186 
1187  union { /* eQADC Advanced Trigger Select */
1188  uint32_t R;
1189  struct {
1190  uint32_t:27;
1191  uint32_t ETSEL0A:5;
1192  } B;
1193  } ISEL9;
1194 
1195  union { /* DecFilter Integrator Control */
1196  uint32_t R;
1197  struct {
1198  uint32_t ZSELA:4;
1199  uint32_t HSELA:4;
1200  uint32_t ZSELB:4;
1201  uint32_t HSELB:4;
1202  uint32_t ZSELC:4;
1203  uint32_t HSELC:4;
1204  uint32_t ZSELD:4;
1205  uint32_t HSELD:4;
1206  } B;
1207  } DECFIL1;
1208 
1209  union { /* DecFilter Integrator Control */
1210  uint32_t R;
1211  struct {
1212  uint32_t ZSELE:4;
1213  uint32_t HSELE:4;
1214  uint32_t ZSELF:4;
1215  uint32_t HSELF:4;
1216  uint32_t ZSELG:4;
1217  uint32_t HSELG:4;
1218  uint32_t ZSELH:4;
1219  uint32_t HSELH:4;
1220  } B;
1221  } DECFIL2;
1222 
1223 
1224  int32_t SIU_reserved0920[20]; /* 0x0930-0x097F */
1225 
1226  union { /* Chip Configuration Register Register */
1227  uint32_t R;
1228  struct {
1229  uint32_t:14;
1230  uint32_t MATCH:1;
1231  uint32_t DISNEX:1;
1232  uint32_t:16;
1233  } B;
1234  } CCR;
1235 
1236  union { /* External Clock Configuration Register Register */
1237  uint32_t R;
1238  struct {
1239  uint32_t:16;
1240  uint32_t ENGDIV:8;
1241  uint32_t ECSS:1;
1242  uint32_t:3;
1243  uint32_t EBTS:1;
1244  uint32_t:1;
1245  uint32_t EBDF:2;
1246  } B;
1247  } ECCR;
1248 
1249  union { /* Compare A Register High */
1250  uint32_t R;
1251  struct {
1252  uint32_t CMPAH:32;
1253  } B;
1254  } CARH;
1255 
1256  union { /* Compare A Register Low */
1257  uint32_t R;
1258  struct {
1259  uint32_t CMPAL:32;
1260  } B;
1261  } CARL;
1262 
1263  union { /* Compare B Register High */
1264  uint32_t R;
1265  struct {
1266  uint32_t CMPBH:32;
1267  } B;
1268  } CBRH;
1269 
1270  union { /* Compare B Register Low */
1271  uint32_t R;
1272  struct {
1273  uint32_t CMPBL:32;
1274  } B;
1275  } CBRL;
1276 
1277  int32_t SIU_reserved0998[2]; /* 0x0998-0x099F */
1278 
1279  union { /* System Clock Register */
1280  uint32_t R;
1281  struct {
1282  uint32_t:22;
1283  uint32_t IPCLKDIV:2;
1284  uint32_t:3;
1285  uint32_t BYPASS:1;
1286  uint32_t SYSCLKDIV:2;
1287  uint32_t:2;
1288  } B;
1289  } SYSDIV;
1290 
1291  union { /* Halt Register */
1292  uint32_t R;
1293  struct {
1294  uint32_t CPUSTP:1; /* CPU and Platform stop request */
1295  uint32_t:4; /* Reserved */
1296  uint32_t TPUSTP:1; /* eTPU_A stop request */
1297  uint32_t NPCSTP:1; /* Nexus stop request */
1298  uint32_t EBISTP:1; /* EBI stop request*/
1299  uint32_t ADCSTP:1; /* eQADC stop request */
1300  uint32_t:1; /* Reserved */
1301  uint32_t MIOSSTP:1; /* eMIOS stop request */
1302  uint32_t DFILSTP:1; /* Decimation filter stop request */
1303  uint32_t:1; /* Reserved */
1304  uint32_t PITSTP:1; /* PIT stop request */
1305  uint32_t:2; /* Reserved */
1306  uint32_t CNDSTP:1; /* FlexCAN D stop request */
1307  uint32_t CNCSTP:1; /* FlexCAN C stop request */
1308  uint32_t CNBSTP:1; /* FlexCAN B stop request */
1309  uint32_t CNASTP:1; /* FlexCAN A stop request */
1310  uint32_t SPIDSTP:1; /* DSPI D stop request */
1311  uint32_t SPICSTP:1; /* DSPI C stop request */
1312  uint32_t SPIBSTP:1; /* DSPI B stop request */
1313  uint32_t SPIASTP:1; /* DSPI C stop request */
1314  uint32_t:5; /* Reserved */
1315  uint32_t SCICSTP:1; /* eSCI C stop request */
1316  uint32_t SCIBSTP:1; /* eSCI B stop request */
1317  uint32_t SCIASTP:1; /* eSCI A stop request */
1318  } B;
1319  } HLT;
1320 
1321  union { /* Halt Acknowledge Register */
1322  uint32_t R;
1323  struct {
1324  uint32_t CPUACK:1; /* CPU and Platform stop acknowledge */
1325  uint32_t:4; /* Reserved */
1326  uint32_t TPUACK:1; /* eTPU_A stop acknowledge */
1327  uint32_t NPCACK:1; /* Nexus stop acknowledge */
1328  uint32_t EBIACK:1; /* EBI stop acknowledge*/
1329  uint32_t ADCACK:1; /* eQADC stop acknowledge */
1330  uint32_t:1; /* Reserved */
1331  uint32_t MIOSACK:1; /* eMIOS stop acknowledge */
1332  uint32_t DFILACK:1; /* Decimation filter stop acknowledge */
1333  uint32_t:1; /* Reserved */
1334  uint32_t PITACK:1; /* PIT stop acknowledge */
1335  uint32_t:2; /* Reserved */
1336  uint32_t CNDACK:1; /* FlexCAN D stop acknowledge */
1337  uint32_t CNCACK:1; /* FlexCAN C stop acknowledge */
1338  uint32_t CNBACK:1; /* FlexCAN B stop acknowledge */
1339  uint32_t CNAACK:1; /* FlexCAN A stop acknowledge */
1340  uint32_t SPIDACK:1; /* DSPI D stop acknowledge */
1341  uint32_t SPICACK:1; /* DSPI C stop acknowledge */
1342  uint32_t SPIBACK:1; /* DSPI B stop acknowledge */
1343  uint32_t SPIAACK:1; /* DSPI C stop acknowledge */
1344  uint32_t:5; /* Reserved */
1345  uint32_t SCICACK:1; /* eSCI C stop acknowledge */
1346  uint32_t SCIBACK:1; /* eSCI B stop acknowledge */
1347  uint32_t SCIAACK:1; /* eSCI A stop acknowledge */
1348  } B;
1349  } HLTACK;
1350 
1351  int32_t SIU_reserved09AC[21]; /* 0x09AC-0x09FF */
1352 
1353  int32_t SIU_reserved0A00[128]; /* 0x0A00-0x0BFF */
1354 
1355  union { /* Parallel GPIO Pin Data Output Register */
1356  uint32_t R;
1357  struct {
1358  uint32_t PGPDO0:1;
1359  uint32_t PGPDO1:1;
1360  uint32_t PGPDO2:1;
1361  uint32_t PGPDO3:1;
1362  uint32_t PGPDO4:1;
1363  uint32_t PGPDO5:1;
1364  uint32_t PGPDO6:1;
1365  uint32_t PGPDO7:1;
1366  uint32_t PGPDO8:1;
1367  uint32_t PGPDO9:1;
1368  uint32_t PGPDO10:1;
1369  uint32_t PGPDO11:1;
1370  uint32_t PGPDO12:1;
1371  uint32_t PGPDO13:1;
1372  uint32_t PGPDO14:1;
1373  uint32_t PGPDO15:1;
1374  uint32_t PGPDO16:1;
1375  uint32_t PGPDO17:1;
1376  uint32_t PGPDO18:1;
1377  uint32_t PGPDO19:1;
1378  uint32_t PGPDO20:1;
1379  uint32_t PGPDO21:1;
1380  uint32_t PGPDO22:1;
1381  uint32_t PGPDO23:1;
1382  uint32_t PGPDO24:1;
1383  uint32_t PGPDO25:1;
1384  uint32_t PGPDO26:1;
1385  uint32_t PGPDO27:1;
1386  uint32_t PGPDO28:1;
1387  uint32_t PGPDO29:1;
1388  uint32_t PGPDO30:1;
1389  uint32_t PGPDO31:1;
1390  } B;
1391  } PGPDO[16];
1392 
1393  union { /* Parallel GPIO Pin Data Input Register */
1394  uint32_t R;
1395  struct {
1396  uint32_t PGPDI0:1;
1397  uint32_t PGPDI1:1;
1398  uint32_t PGPDI2:1;
1399  uint32_t PGPDI3:1;
1400  uint32_t PGPDI4:1;
1401  uint32_t PGPDI5:1;
1402  uint32_t PGPDI6:1;
1403  uint32_t PGPDI7:1;
1404  uint32_t PGPDI8:1;
1405  uint32_t PGPDI9:1;
1406  uint32_t PGPDI10:1;
1407  uint32_t PGPDI11:1;
1408  uint32_t PGPDI12:1;
1409  uint32_t PGPDI13:1;
1410  uint32_t PGPDI14:1;
1411  uint32_t PGPDI15:1;
1412  uint32_t PGPDI16:1;
1413  uint32_t PGPDI17:1;
1414  uint32_t PGPDI18:1;
1415  uint32_t PGPDI19:1;
1416  uint32_t PGPDI20:1;
1417  uint32_t PGPDI21:1;
1418  uint32_t PGPDI22:1;
1419  uint32_t PGPDI23:1;
1420  uint32_t PGPDI24:1;
1421  uint32_t PGPDI25:1;
1422  uint32_t PGPDI26:1;
1423  uint32_t PGPDI27:1;
1424  uint32_t PGPDI28:1;
1425  uint32_t PGPDI29:1;
1426  uint32_t PGPDI30:1;
1427  uint32_t PGPDI31:1;
1428  } B;
1429  } PGPDI[16];
1430 
1431  union { /* Masked Parallel GPIO Pin Data Input Register */
1432  uint32_t R;
1433  struct {
1434  uint32_t MASK0:1;
1435  uint32_t MASK1:1;
1436  uint32_t MASK2:1;
1437  uint32_t MASK3:1;
1438  uint32_t MASK4:1;
1439  uint32_t MASK5:1;
1440  uint32_t MASK6:1;
1441  uint32_t MASK7:1;
1442  uint32_t MASK8:1;
1443  uint32_t MASK9:1;
1444  uint32_t MASK10:1;
1445  uint32_t MASK11:1;
1446  uint32_t MASK12:1;
1447  uint32_t MASK13:1;
1448  uint32_t MASK14:1;
1449  uint32_t MASK15:1;
1450  uint32_t DATA0:1;
1451  uint32_t DATA1:1;
1452  uint32_t DATA2:1;
1453  uint32_t DATA3:1;
1454  uint32_t DATA4:1;
1455  uint32_t DATA5:1;
1456  uint32_t DATA6:1;
1457  uint32_t DATA7:1;
1458  uint32_t DATA8:1;
1459  uint32_t DATA9:1;
1460  uint32_t DATA10:1;
1461  uint32_t DATA11:1;
1462  uint32_t DATA12:1;
1463  uint32_t DATA13:1;
1464  uint32_t DATA14:1;
1465  uint32_t DATA15:1;
1466  } B;
1467  } MPGPDO[32];
1468 
1469  union { /* DSPI_A Mask Output High Register */
1470  uint32_t R;
1471  struct {
1472  uint32_t MASK0:1;
1473  uint32_t MASK1:1;
1474  uint32_t MASK2:1;
1475  uint32_t MASK3:1;
1476  uint32_t MASK4:1;
1477  uint32_t MASK5:1;
1478  uint32_t MASK6:1;
1479  uint32_t MASK7:1;
1480  uint32_t MASK8:1;
1481  uint32_t MASK9:1;
1482  uint32_t MASK10:1;
1483  uint32_t MASK11:1;
1484  uint32_t MASK12:1;
1485  uint32_t MASK13:1;
1486  uint32_t MASK14:1;
1487  uint32_t MASK15:1;
1488  uint32_t DATA0:1;
1489  uint32_t DATA1:1;
1490  uint32_t DATA2:1;
1491  uint32_t DATA3:1;
1492  uint32_t DATA4:1;
1493  uint32_t DATA5:1;
1494  uint32_t DATA6:1;
1495  uint32_t DATA7:1;
1496  uint32_t DATA8:1;
1497  uint32_t DATA9:1;
1498  uint32_t DATA10:1;
1499  uint32_t DATA11:1;
1500  uint32_t DATA12:1;
1501  uint32_t DATA13:1;
1502  uint32_t DATA14:1;
1503  uint32_t DATA15:1;
1504  } B;
1505  } DSPIAH;
1506 
1507  union { /* DSPI_A Mask Output Low Register */
1508  uint32_t R;
1509  struct {
1510  uint32_t MASK16:1;
1511  uint32_t MASK17:1;
1512  uint32_t MASK18:1;
1513  uint32_t MASK19:1;
1514  uint32_t MASK20:1;
1515  uint32_t MASK21:1;
1516  uint32_t MASK22:1;
1517  uint32_t MASK23:1;
1518  uint32_t MASK24:1;
1519  uint32_t MASK25:1;
1520  uint32_t MASK26:1;
1521  uint32_t MASK27:1;
1522  uint32_t MASK28:1;
1523  uint32_t MASK29:1;
1524  uint32_t MASK30:1;
1525  uint32_t MASK31:1;
1526  uint32_t DATA16:1;
1527  uint32_t DATA17:1;
1528  uint32_t DATA18:1;
1529  uint32_t DATA19:1;
1530  uint32_t DATA20:1;
1531  uint32_t DATA21:1;
1532  uint32_t DATA22:1;
1533  uint32_t DATA23:1;
1534  uint32_t DATA24:1;
1535  uint32_t DATA25:1;
1536  uint32_t DATA26:1;
1537  uint32_t DATA27:1;
1538  uint32_t DATA28:1;
1539  uint32_t DATA29:1;
1540  uint32_t DATA30:1;
1541  uint32_t DATA31:1;
1542  } B;
1543  } DSPIAL;
1544 
1545  union { /* DSPI_B Mask Output High Register */
1546  uint32_t R;
1547  struct {
1548  uint32_t MASK0:1;
1549  uint32_t MASK1:1;
1550  uint32_t MASK2:1;
1551  uint32_t MASK3:1;
1552  uint32_t MASK4:1;
1553  uint32_t MASK5:1;
1554  uint32_t MASK6:1;
1555  uint32_t MASK7:1;
1556  uint32_t MASK8:1;
1557  uint32_t MASK9:1;
1558  uint32_t MASK10:1;
1559  uint32_t MASK11:1;
1560  uint32_t MASK12:1;
1561  uint32_t MASK13:1;
1562  uint32_t MASK14:1;
1563  uint32_t MASK15:1;
1564  uint32_t DATA0:1;
1565  uint32_t DATA1:1;
1566  uint32_t DATA2:1;
1567  uint32_t DATA3:1;
1568  uint32_t DATA4:1;
1569  uint32_t DATA5:1;
1570  uint32_t DATA6:1;
1571  uint32_t DATA7:1;
1572  uint32_t DATA8:1;
1573  uint32_t DATA9:1;
1574  uint32_t DATA10:1;
1575  uint32_t DATA11:1;
1576  uint32_t DATA12:1;
1577  uint32_t DATA13:1;
1578  uint32_t DATA14:1;
1579  uint32_t DATA15:1;
1580  } B;
1581  } DSPIBH;
1582 
1583  union { /* DSPI_B Mask Output Low Register */
1584  uint32_t R;
1585  struct {
1586  uint32_t MASK16:1;
1587  uint32_t MASK17:1;
1588  uint32_t MASK18:1;
1589  uint32_t MASK19:1;
1590  uint32_t MASK20:1;
1591  uint32_t MASK21:1;
1592  uint32_t MASK22:1;
1593  uint32_t MASK23:1;
1594  uint32_t MASK24:1;
1595  uint32_t MASK25:1;
1596  uint32_t MASK26:1;
1597  uint32_t MASK27:1;
1598  uint32_t MASK28:1;
1599  uint32_t MASK29:1;
1600  uint32_t MASK30:1;
1601  uint32_t MASK31:1;
1602  uint32_t DATA16:1;
1603  uint32_t DATA17:1;
1604  uint32_t DATA18:1;
1605  uint32_t DATA19:1;
1606  uint32_t DATA20:1;
1607  uint32_t DATA21:1;
1608  uint32_t DATA22:1;
1609  uint32_t DATA23:1;
1610  uint32_t DATA24:1;
1611  uint32_t DATA25:1;
1612  uint32_t DATA26:1;
1613  uint32_t DATA27:1;
1614  uint32_t DATA28:1;
1615  uint32_t DATA29:1;
1616  uint32_t DATA30:1;
1617  uint32_t DATA31:1;
1618  } B;
1619  } DSPIBL;
1620 
1621  union { /* DSPI_C Mask Output High Register */
1622  uint32_t R;
1623  struct {
1624  uint32_t MASK0:1;
1625  uint32_t MASK1:1;
1626  uint32_t MASK2:1;
1627  uint32_t MASK3:1;
1628  uint32_t MASK4:1;
1629  uint32_t MASK5:1;
1630  uint32_t MASK6:1;
1631  uint32_t MASK7:1;
1632  uint32_t MASK8:1;
1633  uint32_t MASK9:1;
1634  uint32_t MASK10:1;
1635  uint32_t MASK11:1;
1636  uint32_t MASK12:1;
1637  uint32_t MASK13:1;
1638  uint32_t MASK14:1;
1639  uint32_t MASK15:1;
1640  uint32_t DATA0:1;
1641  uint32_t DATA1:1;
1642  uint32_t DATA2:1;
1643  uint32_t DATA3:1;
1644  uint32_t DATA4:1;
1645  uint32_t DATA5:1;
1646  uint32_t DATA6:1;
1647  uint32_t DATA7:1;
1648  uint32_t DATA8:1;
1649  uint32_t DATA9:1;
1650  uint32_t DATA10:1;
1651  uint32_t DATA11:1;
1652  uint32_t DATA12:1;
1653  uint32_t DATA13:1;
1654  uint32_t DATA14:1;
1655  uint32_t DATA15:1;
1656  } B;
1657  } DSPICH;
1658 
1659  union { /* DSPI_C Mask Output Low Register */
1660  uint32_t R;
1661  struct {
1662  uint32_t MASK16:1;
1663  uint32_t MASK17:1;
1664  uint32_t MASK18:1;
1665  uint32_t MASK19:1;
1666  uint32_t MASK20:1;
1667  uint32_t MASK21:1;
1668  uint32_t MASK22:1;
1669  uint32_t MASK23:1;
1670  uint32_t MASK24:1;
1671  uint32_t MASK25:1;
1672  uint32_t MASK26:1;
1673  uint32_t MASK27:1;
1674  uint32_t MASK28:1;
1675  uint32_t MASK29:1;
1676  uint32_t MASK30:1;
1677  uint32_t MASK31:1;
1678  uint32_t DATA16:1;
1679  uint32_t DATA17:1;
1680  uint32_t DATA18:1;
1681  uint32_t DATA19:1;
1682  uint32_t DATA20:1;
1683  uint32_t DATA21:1;
1684  uint32_t DATA22:1;
1685  uint32_t DATA23:1;
1686  uint32_t DATA24:1;
1687  uint32_t DATA25:1;
1688  uint32_t DATA26:1;
1689  uint32_t DATA27:1;
1690  uint32_t DATA28:1;
1691  uint32_t DATA29:1;
1692  uint32_t DATA30:1;
1693  uint32_t DATA31:1;
1694  } B;
1695  } DSPICL;
1696 
1697  union { /* DSPI_D Mask Output High Register */
1698  uint32_t R;
1699  struct {
1700  uint32_t MASK0:1;
1701  uint32_t MASK1:1;
1702  uint32_t MASK2:1;
1703  uint32_t MASK3:1;
1704  uint32_t MASK4:1;
1705  uint32_t MASK5:1;
1706  uint32_t MASK6:1;
1707  uint32_t MASK7:1;
1708  uint32_t MASK8:1;
1709  uint32_t MASK9:1;
1710  uint32_t MASK10:1;
1711  uint32_t MASK11:1;
1712  uint32_t MASK12:1;
1713  uint32_t MASK13:1;
1714  uint32_t MASK14:1;
1715  uint32_t MASK15:1;
1716  uint32_t DATA0:1;
1717  uint32_t DATA1:1;
1718  uint32_t DATA2:1;
1719  uint32_t DATA3:1;
1720  uint32_t DATA4:1;
1721  uint32_t DATA5:1;
1722  uint32_t DATA6:1;
1723  uint32_t DATA7:1;
1724  uint32_t DATA8:1;
1725  uint32_t DATA9:1;
1726  uint32_t DATA10:1;
1727  uint32_t DATA11:1;
1728  uint32_t DATA12:1;
1729  uint32_t DATA13:1;
1730  uint32_t DATA14:1;
1731  uint32_t DATA15:1;
1732  } B;
1733  } DSPIDH;
1734 
1735  union { /* DSPI_D Mask Output Low Register */
1736  uint32_t R;
1737  struct {
1738  uint32_t MASK16:1;
1739  uint32_t MASK17:1;
1740  uint32_t MASK18:1;
1741  uint32_t MASK19:1;
1742  uint32_t MASK20:1;
1743  uint32_t MASK21:1;
1744  uint32_t MASK22:1;
1745  uint32_t MASK23:1;
1746  uint32_t MASK24:1;
1747  uint32_t MASK25:1;
1748  uint32_t MASK26:1;
1749  uint32_t MASK27:1;
1750  uint32_t MASK28:1;
1751  uint32_t MASK29:1;
1752  uint32_t MASK30:1;
1753  uint32_t MASK31:1;
1754  uint32_t DATA16:1;
1755  uint32_t DATA17:1;
1756  uint32_t DATA18:1;
1757  uint32_t DATA19:1;
1758  uint32_t DATA20:1;
1759  uint32_t DATA21:1;
1760  uint32_t DATA22:1;
1761  uint32_t DATA23:1;
1762  uint32_t DATA24:1;
1763  uint32_t DATA25:1;
1764  uint32_t DATA26:1;
1765  uint32_t DATA27:1;
1766  uint32_t DATA28:1;
1767  uint32_t DATA29:1;
1768  uint32_t DATA30:1;
1769  uint32_t DATA31:1;
1770  } B;
1771  } DSPIDL;
1772 
1773  int32_t SIU_reserved0D20[8]; /* 0x0D20-0x0D3F */
1774 
1775  union { /* ETPU B Select Register */
1776  uint32_t R;
1777  struct {
1778  uint32_t ETPUB15:1;
1779  uint32_t ETPUB14:1;
1780  uint32_t ETPUB13:1;
1781  uint32_t ETPUB12:1;
1782  uint32_t ETPUB11:1;
1783  uint32_t ETPUB10:1;
1784  uint32_t ETPUB9:1;
1785  uint32_t ETPUB8:1;
1786  uint32_t ETPUB7:1;
1787  uint32_t ETPUB6:1;
1788  uint32_t ETPUB5:1;
1789  uint32_t ETPUB4:1;
1790  uint32_t ETPUB3:1;
1791  uint32_t ETPUB2:1;
1792  uint32_t ETPUB1:1;
1793  uint32_t ETPUB0:1;
1794  uint32_t ETPUB31:1;
1795  uint32_t ETPUB30:1;
1796  uint32_t ETPUB29:1;
1797  uint32_t ETPUB28:1;
1798  uint32_t ETPUB27:1;
1799  uint32_t ETPUB26:1;
1800  uint32_t ETPUB25:1;
1801  uint32_t ETPUB24:1;
1802  uint32_t ETPUB23:1;
1803  uint32_t ETPUB22:1;
1804  uint32_t ETPUB21:1;
1805  uint32_t ETPUB20:1;
1806  uint32_t ETPUB19:1;
1807  uint32_t ETPUB18:1;
1808  uint32_t ETPUB17:1;
1809  uint32_t ETPUB16:1;
1810  } B ;
1811  } ETPUBA;
1812 
1813  union { /* EMIOS A Select Register */
1814  uint32_t R;
1815  struct {
1816  uint32_t EMIOS7:1;
1817  uint32_t EMIOS6:1;
1818  uint32_t EMIOS5:1;
1819  uint32_t EMIOS4:1;
1820  uint32_t EMIOS3:1;
1821  uint32_t EMIOS2:1;
1822  uint32_t EMIOS1:1;
1823  uint32_t EMIOS0:1;
1824  uint32_t EMIOS8:1;
1825  uint32_t EMIOS9:1;
1826  uint32_t EMIOS10:1;
1827  uint32_t EMIOS11:1;
1828  uint32_t EMIOS12:1;
1829  uint32_t EMIOS13:1;
1830  uint32_t EMIOS14:1;
1831  uint32_t EMIOS15:1;
1832  uint32_t EMIOS16:1;
1833  uint32_t EMIOS17:1;
1834  uint32_t EMIOS18:1;
1835  uint32_t EMIOS19:1;
1836  uint32_t EMIOS20:1;
1837  uint32_t EMIOS21:1;
1838  uint32_t EMIOS22:1;
1839  uint32_t EMIOS23:1;
1840  uint32_t EMIOS0_0:1;
1841  uint32_t EMIOS1_1:1;
1842  uint32_t EMIOS2_2:1;
1843  uint32_t EMIOS3_3:1;
1844  uint32_t EMIOS4_4:1;
1845  uint32_t EMIOS5_5:1;
1846  uint32_t EMIOS6_6:1;
1847  uint32_t EMIOS7_7:1;
1848  } B;
1849  } EMIOSA;
1850 
1851  union { /* DSPIAH/L Select Register for DSPI A */
1852  uint32_t R;
1853  struct {
1854  uint32_t DSPIAH0:1;
1855  uint32_t DSPIAH1:1;
1856  uint32_t DSPIAH2:1;
1857  uint32_t DSPIAH3:1;
1858  uint32_t DSPIAH4:1;
1859  uint32_t DSPIAH5:1;
1860  uint32_t DSPIAH6:1;
1861  uint32_t DSPIAH7:1;
1862  uint32_t DSPIAH8:1;
1863  uint32_t DSPIAH9:1;
1864  uint32_t DSPIAH10:1;
1865  uint32_t DSPIAH11:1;
1866  uint32_t DSPIAH12:1;
1867  uint32_t DSPIAH13:1;
1868  uint32_t DSPIAH14:1;
1869  uint32_t DSPIAH15:1;
1870  uint32_t DSPIAL16:1;
1871  uint32_t DSPIAL17:1;
1872  uint32_t DSPIAL18:1;
1873  uint32_t DSPIAL19:1;
1874  uint32_t DSPIAL20:1;
1875  uint32_t DSPIAL21:1;
1876  uint32_t DSPIAL22:1;
1877  uint32_t DSPIAL23:1;
1878  uint32_t DSPIAL24:1;
1879  uint32_t DSPIAL25:1;
1880  uint32_t DSPIAL26:1;
1881  uint32_t DSPIAL27:1;
1882  uint32_t DSPIAL28:1;
1883  uint32_t DSPIAL29:1;
1884  uint32_t DSPIAL30:1;
1885  uint32_t DSPIAL31:1;
1886  } B;
1887  } DSPIAHLA;
1888 
1889  int32_t SIU_reserved0D4C; /* 0x0D4C-0x0D4F */
1890 
1891  union { /* ETPU A Select Register */
1892  uint32_t R;
1893  struct {
1894  uint32_t ETPUA23:1;
1895  uint32_t ETPUA22:1;
1896  uint32_t ETPUA21:1;
1897  uint32_t ETPUA20:1;
1898  uint32_t ETPUA19:1;
1899  uint32_t ETPUA18:1;
1900  uint32_t ETPUA17:1;
1901  uint32_t ETPUA16:1;
1902  uint32_t ETPUA29:1;
1903  uint32_t ETPUA28:1;
1904  uint32_t ETPUA27:1;
1905  uint32_t ETPUA26:1;
1906  uint32_t ETPUA25:1;
1907  uint32_t ETPUA24:1;
1908  uint32_t ETPUA31:1;
1909  uint32_t ETPUA30:1;
1910  uint32_t ETPUA12:1;
1911  uint32_t ETPUA13:1;
1912  uint32_t ETPUA14:1;
1913  uint32_t ETPUA15:1;
1914  uint32_t ETPUA0:1;
1915  uint32_t ETPUA1:1;
1916  uint32_t ETPUA2:1;
1917  uint32_t ETPUA3:1;
1918  uint32_t ETPUA4:1;
1919  uint32_t ETPUA5:1;
1920  uint32_t ETPUA6:1;
1921  uint32_t ETPUA7:1;
1922  uint32_t ETPUA8:1;
1923  uint32_t ETPUA9:1;
1924  uint32_t ETPUA10:1;
1925  uint32_t ETPUA11:1;
1926  } B ;
1927  } ETPUAB;
1928 
1929  union { /* EMIOS B Select Register */
1930  uint32_t R;
1931  struct {
1932  uint32_t EMIOS11:1;
1933  uint32_t EMIOS10:1;
1934  uint32_t EMIOS9:1;
1935  uint32_t EMIOS8:1;
1936  uint32_t EMIOS6:1;
1937  uint32_t EMIOS5:1;
1938  uint32_t EMIOS4:1;
1939  uint32_t EMIOS3:1;
1940  uint32_t EMIOS2:1;
1941  uint32_t EMIOS1:1;
1942  uint32_t EMIOS0:1;
1943  uint32_t EMIOS23:1;
1944  uint32_t EMIOS15:1;
1945  uint32_t EMIOS14:1;
1946  uint32_t EMIOS13:1;
1947  uint32_t EMIOS12:1;
1948  uint32_t EMIOS23_23:1;
1949  uint32_t EMIOS15_15:1;
1950  uint32_t EMIOS14_14:1;
1951  uint32_t EMIOS13_13:1;
1952  uint32_t EMIOS12_12:1;
1953  uint32_t EMIOS11_11:1;
1954  uint32_t EMIOS10_10:1;
1955  uint32_t EMIOS9_9:1;
1956  uint32_t EMIOS8_8:1;
1957  uint32_t EMIOS6_6:1;
1958  uint32_t EMIOS5_5:1;
1959  uint32_t EMIOS4_4:1;
1960  uint32_t EMIOS3_3:1;
1961  uint32_t EMIOS2_2:1;
1962  uint32_t EMIOS1_1:1;
1963  uint32_t EMIOS0_0:1;
1964  } B;
1965  } EMIOSB;
1966 
1967  union { /* DSPIBH/L Select Register for DSPI B */
1968  uint32_t R;
1969  struct {
1970  uint32_t DSPIBH0:1;
1971  uint32_t DSPIBH1:1;
1972  uint32_t DSPIBH2:1;
1973  uint32_t DSPIBH3:1;
1974  uint32_t DSPIBH4:1;
1975  uint32_t DSPIBH5:1;
1976  uint32_t DSPIBH6:1;
1977  uint32_t DSPIBH7:1;
1978  uint32_t DSPIBH8:1;
1979  uint32_t DSPIBH9:1;
1980  uint32_t DSPIBH10:1;
1981  uint32_t DSPIBH11:1;
1982  uint32_t DSPIBH12:1;
1983  uint32_t DSPIBH13:1;
1984  uint32_t DSPIBH14:1;
1985  uint32_t DSPIBH15:1;
1986  uint32_t DSPIBL16:1;
1987  uint32_t DSPIBL17:1;
1988  uint32_t DSPIBL18:1;
1989  uint32_t DSPIBL19:1;
1990  uint32_t DSPIBL20:1;
1991  uint32_t DSPIBL21:1;
1992  uint32_t DSPIBL22:1;
1993  uint32_t DSPIBL23:1;
1994  uint32_t DSPIBL24:1;
1995  uint32_t DSPIBL25:1;
1996  uint32_t DSPIBL26:1;
1997  uint32_t DSPIBL27:1;
1998  uint32_t DSPIBL28:1;
1999  uint32_t DSPIBL29:1;
2000  uint32_t DSPIBL30:1;
2001  uint32_t DSPIBL31:1;
2002  } B;
2003  } DSPIBHLB;
2004 
2005  int32_t SIU_reserved0D5C; /* 0x0D5C-0x0D5F */
2006 
2007  union { /* ETPU A Select Register */
2008  uint32_t R;
2009  struct {
2010  uint32_t ETPUA12:1;
2011  uint32_t ETPUA13:1;
2012  uint32_t ETPUA14:1;
2013  uint32_t ETPUA15:1;
2014  uint32_t ETPUA0:1;
2015  uint32_t ETPUA1:1;
2016  uint32_t ETPUA2:1;
2017  uint32_t ETPUA3:1;
2018  uint32_t ETPUA4:1;
2019  uint32_t ETPUA5:1;
2020  uint32_t ETPUA6:1;
2021  uint32_t ETPUA7:1;
2022  uint32_t ETPUA8:1;
2023  uint32_t ETPUA9:1;
2024  uint32_t ETPUA10:1;
2025  uint32_t ETPUA11:1;
2026  uint32_t ETPUA23:1;
2027  uint32_t ETPUA22:1;
2028  uint32_t ETPUA21:1;
2029  uint32_t ETPUA20:1;
2030  uint32_t ETPUA19:1;
2031  uint32_t ETPUA18:1;
2032  uint32_t ETPUA17:1;
2033  uint32_t ETPUA16:1;
2034  uint32_t ETPUA29:1;
2035  uint32_t ETPUA28:1;
2036  uint32_t ETPUA27:1;
2037  uint32_t ETPUA26:1;
2038  uint32_t ETPUA25:1;
2039  uint32_t ETPUA24:1;
2040  uint32_t ETPUA31:1;
2041  uint32_t ETPUA30:1;
2042  } B ;
2043  } ETPUAC;
2044 
2045  union { /* EMIOS C Select Register */
2046  uint32_t R;
2047  struct {
2048  uint32_t EMIOS12:1;
2049  uint32_t EMIOS13:1;
2050  uint32_t EMIOS14:1;
2051  uint32_t EMIOS15:1;
2052  uint32_t EMIOS23:1;
2053  uint32_t EMIOS0:1;
2054  uint32_t EMIOS1:1;
2055  uint32_t EMIOS2:1;
2056  uint32_t EMIOS3:1;
2057  uint32_t EMIOS4:1;
2058  uint32_t EMIOS5:1;
2059  uint32_t EMIOS6:1;
2060  uint32_t EMIOS8:1;
2061  uint32_t EMIOS9:1;
2062  uint32_t EMIOS10:1;
2063  uint32_t EMIOS11:1;
2064  uint32_t EMIOS23_23:1;
2065  uint32_t EMIOS22:1;
2066  uint32_t EMIOS21:1;
2067  uint32_t EMIOS20:1;
2068  uint32_t EMIOS19:1;
2069  uint32_t EMIOS18:1;
2070  uint32_t EMIOS17:1;
2071  uint32_t EMIOS16:1;
2072  uint32_t EMIOS29:1;
2073  uint32_t EMIOS28:1;
2074  uint32_t EMIOS27:1;
2075  uint32_t EMIOS26:1;
2076  uint32_t EMIOS25:1;
2077  uint32_t EMIOS24:1;
2078  uint32_t EMIOS31:1;
2079  uint32_t EMIOS30:1;
2080  } B;
2081  } EMIOSC;
2082 
2083  union { /* DSPICH/L Select Register for DSPI C */
2084  uint32_t R;
2085  struct {
2086  uint32_t DSPICH0:1;
2087  uint32_t DSPICH1:1;
2088  uint32_t DSPICH2:1;
2089  uint32_t DSPICH3:1;
2090  uint32_t DSPICH4:1;
2091  uint32_t DSPICH5:1;
2092  uint32_t DSPICH6:1;
2093  uint32_t DSPICH7:1;
2094  uint32_t DSPICH8:1;
2095  uint32_t DSPICH9:1;
2096  uint32_t DSPICH10:1;
2097  uint32_t DSPICH11:1;
2098  uint32_t DSPICH12:1;
2099  uint32_t DSPICH13:1;
2100  uint32_t DSPICH14:1;
2101  uint32_t DSPICH15:1;
2102  uint32_t DSPICL16:1;
2103  uint32_t DSPICL17:1;
2104  uint32_t DSPICL18:1;
2105  uint32_t DSPICL19:1;
2106  uint32_t DSPICL20:1;
2107  uint32_t DSPICL21:1;
2108  uint32_t DSPICL22:1;
2109  uint32_t DSPICL23:1;
2110  uint32_t DSPICL24:1;
2111  uint32_t DSPICL25:1;
2112  uint32_t DSPICL26:1;
2113  uint32_t DSPICL27:1;
2114  uint32_t DSPICL28:1;
2115  uint32_t DSPICL29:1;
2116  uint32_t DSPICL30:1;
2117  uint32_t DSPICL31:1;
2118  } B;
2119  } DSPICHLC;
2120 
2121  int32_t SIU_reserved0D6C; /* 0x0D6C-0x0D6F */
2122 
2123  union { /* ETPU B Select Register */
2124  uint32_t R;
2125  struct {
2126  uint32_t ETPUB21:1;
2127  uint32_t ETPUB20:1;
2128  uint32_t ETPUB19:1;
2129  uint32_t ETPUB18:1;
2130  uint32_t ETPUB17:1;
2131  uint32_t ETPUB16:1;
2132  uint32_t:4;
2133  uint32_t ETPUB29:1;
2134  uint32_t ETPUB28:1;
2135  uint32_t ETPUB27:1;
2136  uint32_t ETPUB26:1;
2137  uint32_t ETPUB25:1;
2138  uint32_t ETPUB24:1;
2139  uint32_t:16;
2140  } B ;
2141  } ETPUBD;
2142 
2143  union { /* EMIOS D Select Register */
2144  uint32_t R;
2145  struct {
2146  uint32_t:6;
2147  uint32_t EMIOS11:1;
2148  uint32_t EMIOS10:1;
2149  uint32_t EMIOS13:1;
2150  uint32_t EMIOS12:1;
2151  uint32_t:22;
2152  } B;
2153  } EMIOSD;
2154 
2155  union { /* DSPIDH/L Select Register for DSPI D */
2156  uint32_t R;
2157  struct {
2158  uint32_t:32;
2159  } B;
2160  } DSPIDHLD;
2161 
2162  int32_t SIU_reserved0D7C; /* 0x0D7C-0x0D7F */
2163 
2164  int32_t SIU_reserved0D80[32]; /* 0x0D80-0x0DFF */
2165 
2166  union { /* GPIO Pin Data Input Registers */
2167  uint8_t R;
2168  struct {
2169  uint8_t:7;
2170  uint8_t PDI:1;
2171  } B;
2172  } GPDI0_511[512];
2173 
2174  uint32_t SIU_reserved1000[3072]; /* 0x1000-0x3FFF */
2175  };
2176 
2177 /****************************************************************************/
2178 /* MODULE : EMIOS */
2179 /****************************************************************************/
2180 
2181  struct EMIOS_tag {
2182 
2183  union EMIOS_MCR_tag { /* Module Configuration Register */
2184  uint32_t R;
2185  struct {
2186  uint32_t:1;
2187  uint32_t MDIS:1;
2188  uint32_t FRZ:1;
2189  uint32_t GTBE:1;
2190  uint32_t ETB:1;
2191  uint32_t GPREN:1;
2192  uint32_t:6;
2193  uint32_t SRV:4;
2194  uint32_t GPRE:8;
2195  uint32_t:8;
2196  } B;
2197  } MCR;
2198 
2199  union { /* Global FLAG Register */
2200  uint32_t R;
2201  struct {
2202  uint32_t F31:1;
2203  uint32_t F30:1;
2204  uint32_t F29:1;
2205  uint32_t F28:1;
2206  uint32_t F27:1;
2207  uint32_t F26:1;
2208  uint32_t F25:1;
2209  uint32_t F24:1;
2210  uint32_t F23:1;
2211  uint32_t F22:1;
2212  uint32_t F21:1;
2213  uint32_t F20:1;
2214  uint32_t F19:1;
2215  uint32_t F18:1;
2216  uint32_t F17:1;
2217  uint32_t F16:1;
2218  uint32_t F15:1;
2219  uint32_t F14:1;
2220  uint32_t F13:1;
2221  uint32_t F12:1;
2222  uint32_t F11:1;
2223  uint32_t F10:1;
2224  uint32_t F9:1;
2225  uint32_t F8:1;
2226  uint32_t F7:1;
2227  uint32_t F6:1;
2228  uint32_t F5:1;
2229  uint32_t F4:1;
2230  uint32_t F3:1;
2231  uint32_t F2:1;
2232  uint32_t F1:1;
2233  uint32_t F0:1;
2234  } B;
2235  } GFR;
2236 
2237  union { /* Output Update Disable Register */
2238  uint32_t R;
2239  struct {
2240  uint32_t OU31:1;
2241  uint32_t OU30:1;
2242  uint32_t OU29:1;
2243  uint32_t OU28:1;
2244  uint32_t OU27:1;
2245  uint32_t OU26:1;
2246  uint32_t OU25:1;
2247  uint32_t OU24:1;
2248  uint32_t OU23:1;
2249  uint32_t OU22:1;
2250  uint32_t OU21:1;
2251  uint32_t OU20:1;
2252  uint32_t OU19:1;
2253  uint32_t OU18:1;
2254  uint32_t OU17:1;
2255  uint32_t OU16:1;
2256  uint32_t OU15:1;
2257  uint32_t OU14:1;
2258  uint32_t OU13:1;
2259  uint32_t OU12:1;
2260  uint32_t OU11:1;
2261  uint32_t OU10:1;
2262  uint32_t OU9:1;
2263  uint32_t OU8:1;
2264  uint32_t OU7:1;
2265  uint32_t OU6:1;
2266  uint32_t OU5:1;
2267  uint32_t OU4:1;
2268  uint32_t OU3:1;
2269  uint32_t OU2:1;
2270  uint32_t OU1:1;
2271  uint32_t OU0:1;
2272  } B;
2273  } OUDR;
2274 
2275  uint32_t eMIOS_reserved000C[5]; /* 0x000C-0x001F */
2276 
2277  struct EMIOS_CH_tag {
2278  union { /* Channel A Data Register */
2279  uint32_t R;
2280  } CADR;
2281 
2282  union { /* Channel B Data Register */
2283  uint32_t R;
2284  } CBDR;
2285 
2286  union { /* Channel Counter Register */
2287  uint32_t R;
2288  } CCNTR;
2289 
2290  union EMIOS_CCR_tag {/* Channel Control Register */
2291  uint32_t R;
2292  struct {
2293  uint32_t FREN:1;
2294  uint32_t ODIS:1;
2295  uint32_t ODISSL:2;
2296  uint32_t UCPRE:2;
2297  uint32_t UCPREN:1;
2298  uint32_t DMA:1;
2299  uint32_t:1;
2300  uint32_t IF:4;
2301  uint32_t FCK:1;
2302  uint32_t FEN:1;
2303  uint32_t:3;
2304  uint32_t FORCMA:1;
2305  uint32_t FORCMB:1;
2306  uint32_t:1;
2307  uint32_t BSL:2;
2308  uint32_t EDSEL:1;
2309  uint32_t EDPOL:1;
2310  uint32_t MODE:7;
2311  } B;
2312  } CCR;
2313 
2314  union EMIOS_CSR_tag {/* Channel Status Register */
2315  uint32_t R;
2316  struct {
2317  uint32_t OVR:1;
2318  uint32_t:15;
2319  uint32_t OVFL:1;
2320  uint32_t:12;
2321  uint32_t UCIN:1;
2322  uint32_t UCOUT:1;
2323  uint32_t FLAG:1;
2324  } B;
2325  } CSR;
2326 
2327  union { /* Alternate Channel A Data Register */
2328  uint32_t R;
2329  } ALTA;
2330 
2331  uint32_t eMIOS_channel_reserved0018[2]; /* 0x0018-0x001F */
2332 
2333  } CH[32];
2334 
2335  uint32_t eMIOS_reserved0420[3832]; /* 0x0420-0x3FFF */
2336 
2337  };
2338 
2339 /****************************************************************************/
2340 /* MODULE : PMC */
2341 /****************************************************************************/
2342 
2343  struct PMC_tag {
2344 
2345  union {
2346  uint32_t R;
2347  struct {
2348  uint32_t LVRER:1;
2349  uint32_t LVREH:1;
2350  uint32_t LVRE50:1;
2351  uint32_t LVRE33:1;
2352  uint32_t LVREC:1;
2353  uint32_t LVREA:1;
2354  uint32_t:1;
2355  uint32_t:1;
2356  uint32_t LVIER:1;
2357  uint32_t LVIEH:1;
2358  uint32_t LVIE50:1;
2359  uint32_t LVIE33:1;
2360  uint32_t LVIEC:1;
2361  uint32_t LVIEA:1;
2362  uint32_t:1;
2363  uint32_t TLK:1;
2364  uint32_t:16;
2365  } B;
2366  } MCR; /* Module Configuration Register */
2367 
2368  union {
2369  uint32_t R;
2370  struct {
2371  uint32_t :8;
2372  uint32_t LVDATRIM:4;
2373  uint32_t LVDREGTRIM:4;
2374  uint32_t VDD33TRIM:4;
2375  uint32_t LVD33TRIM:4;
2376  uint32_t VDDCTRIM:4;
2377  uint32_t LVDCTRIM:4;
2378  } B;
2379  } TRIMR; /* Trimming register */
2380 
2381  union {
2382  uint32_t R;
2383  struct {
2384  uint32_t :5;
2385  uint32_t LVFSTBY:1;
2386  uint32_t BGRDY:1;
2387  uint32_t BGTS:1;
2388  uint32_t :5;
2389  uint32_t LVFCSTBY:1;
2390  uint32_t :2;
2391  uint32_t LVFCR:1;
2392  uint32_t LVFCH:1;
2393  uint32_t LVFC50:1;
2394  uint32_t LVFC33:1;
2395  uint32_t LVFCC:1;
2396  uint32_t LVFCA:1;
2397  uint32_t :2;
2398  uint32_t LVFR:1;
2399  uint32_t LVFH:1;
2400  uint32_t LVF50:1;
2401  uint32_t LVF33:1;
2402  uint32_t LVFC:1;
2403  uint32_t LVFA:1;
2404  uint32_t :2;
2405  } B;
2406  } SR; /* status register */
2407 
2408  uint32_t PMC_reserved000C[4093]; /* 0x000C-0x3FFF */
2409  };
2410 
2411 /****************************************************************************/
2412 /* MODULE :ETPU */
2413 /****************************************************************************/
2414 
2415 /***************************Configuration Registers**************************/
2416 
2417  struct ETPU_tag {
2418  union { /* MODULE CONFIGURATION REGISTER */
2419  uint32_t R;
2420  struct {
2421  uint32_t GEC:1; /* Global Exception Clear */
2422  uint32_t SDMERR:1; /* SDM Read Error */
2423  uint32_t WDTOA:1; /* Watchdog Timeout-eTPU_A */
2424  uint32_t WDTOB:1; /* Watchdog Timeout-eTPU_B */
2425  uint32_t MGE1:1; /* Microcode Global Exception-ETPU_A */
2426  uint32_t MGE2:1; /* Microcode Global Exception-ETPU_B */
2427  uint32_t ILF1:1; /* Illegal Instruction Flag-ETPU_A */
2428  uint32_t ILF2:1; /* Illegal Instruction Flag-ETPU_B */
2429  uint32_t:3;
2430  uint32_t SCMSIZE:5; /* Shared Code Memory size */
2431  uint32_t:4;
2432  uint32_t SCMMISC:1; /* SCM MISC Complete/Clear */
2433  uint32_t SCMMISF:1; /* SCM MISC Flag */
2434  uint32_t SCMMISEN:1; /* SCM MISC Enable */
2435  uint32_t:2;
2436  uint32_t VIS:1; /* SCM Visability */
2437  uint32_t:5;
2438  uint32_t GTBE:1; /* Global Time Base Enable */
2439  } B;
2440  } MCR;
2441 
2442  union { /* COHERENT DUAL-PARAMETER CONTROL */
2443  uint32_t R;
2444  struct {
2445  uint32_t STS:1; /* Start Status bit */
2446  uint32_t CTBASE:5; /* Channel Transfer Base */
2447  uint32_t PBASE:10; /* Parameter Buffer Base Address */
2448  uint32_t PWIDTH:1; /* Parameter Width */
2449  uint32_t PARAM0:7; /* Channel Parameter 0 */
2450  uint32_t WR:1; /* Read/Write selection */
2451  uint32_t PARAM1:7; /* Channel Parameter 1 */
2452  } B;
2453  } CDCR;
2454 
2455  uint32_t eTPU_reserved0008; /* 0x0008-0x000B */
2456 
2457  union { /* MISC Compare Register */
2458  uint32_t R;
2459  struct {
2460  uint32_t ETPUMISCCMP:32;
2461  } B;
2462  } MISCCMPR;
2463 
2464  union { /* SCM off-range Date Register */
2465  uint32_t R;
2466  struct {
2467  uint32_t ETPUSCMOFFDATA:32;
2468  } B;
2469  } SCMOFFDATAR;
2470 
2471  union { /* ETPU_A Configuration Register */
2472  uint32_t R;
2473  struct {
2474  uint32_t FEND:1; /* Force END */
2475  uint32_t MDIS:1; /* Low power Stop */
2476  uint32_t:1;
2477  uint32_t STF:1; /* Stop Flag */
2478  uint32_t:4;
2479  uint32_t HLTF:1; /* Halt Mode Flag */
2480  uint32_t:3;
2481  uint32_t FCSS:1; /* Filter Clock Source Select */
2482  uint32_t FPSCK:3; /* Filter Prescaler Clock Control */
2483  uint32_t CDFC:2;
2484  uint32_t:1;
2485  uint32_t ERBA:5; /* Engine Relative Base Address */
2486  uint32_t SPPDIS:1; /* Schedule Priority Passing Disable */
2487  uint32_t:2;
2488  uint32_t ETB:5; /* Entry Table Base */
2489  } B;
2490  } ECR_A;
2491 
2492  union { /* ETPU_B Configuration Register */
2493  uint32_t R;
2494  struct {
2495  uint32_t FEND:1; /* Force END */
2496  uint32_t MDIS:1; /* Low power Stop */
2497  uint32_t:1;
2498  uint32_t STF:1; /* Stop Flag */
2499  uint32_t:4;
2500  uint32_t HLTF:1; /* Halt Mode Flag */
2501  uint32_t:3;
2502  uint32_t FCSS:1; /* Filter Clock Source Select */
2503  uint32_t FPSCK:3; /* Filter Prescaler Clock Control */
2504  uint32_t CDFC:2;
2505  uint32_t:1;
2506  uint32_t ERBA:5; /* Engine Relative Base Address */
2507  uint32_t SPPDIS:1; /* Schedule Priority Passing Disable */
2508  uint32_t:2;
2509  uint32_t ETB:5; /* Entry Table Base */
2510  } B;
2511  } ECR_B;
2512 
2513  uint32_t eTPU_reserved001C; /* 0x001C-0x001F */
2514 
2515  union { /* ETPU_A Timebase Configuration Register */
2516  uint32_t R;
2517  struct {
2518  uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
2519  uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
2520  uint32_t AM:2; /* Angle Mode */
2521  uint32_t:3;
2522  uint32_t TCR2P:6; /* TCR2 Prescaler Control */
2523  uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
2524  uint32_t TCR1CS:1; /* TCR1 Clock Source */
2525  uint32_t:5;
2526  uint32_t TCR1P:8; /* TCR1 Prescaler Control */
2527  } B;
2528  } TBCR_A;
2529 
2530  union { /* ETPU_A TCR1 Visibility Register */
2531  uint32_t R;
2532  struct {
2533  uint32_t:8;
2534  uint32_t TCR1:24;
2535  } B;
2536  } TB1R_A;
2537 
2538  union { /* ETPU_A TCR2 Visibility Register */
2539  uint32_t R;
2540  struct {
2541  uint32_t:8;
2542  uint32_t TCR2:24;
2543  } B;
2544  } TB2R_A;
2545 
2546  union { /* ETPU_A STAC Configuration Register */
2547  uint32_t R;
2548  struct {
2549  uint32_t REN1:1; /* Resource Enable TCR1 */
2550  uint32_t RSC1:1; /* Resource Control TCR1 */
2551  uint32_t:2;
2552  uint32_t SERVER_ID1:4; /* TCR1 Server ID */
2553  uint32_t:4;
2554  uint32_t SRV1:4; /* Resource Server Slot */
2555  uint32_t REN2:1; /* Resource Enable TCR2 */
2556  uint32_t RSC2:1; /* Resource Control TCR2 */
2557  uint32_t:2;
2558  uint32_t SERVER_ID2:4; /* TCR2 Server ID */
2559  uint32_t:4;
2560  uint32_t SRV2:4; /* Resource Server Slot */
2561  } B;
2562  } REDCR_A;
2563 
2564  uint32_t eTPU_reserved0030[4]; /* 0x0030-0x003F */
2565 
2566  union { /* ETPU_B Timebase Configuration Register */
2567  uint32_t R;
2568  struct {
2569  uint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */
2570  uint32_t TCRCF:2; /* TCRCLK Signal Filter Control */
2571  uint32_t AM:2; /* Angle Mode */
2572  uint32_t:3;
2573  uint32_t TCR2P:6; /* TCR2 Prescaler Control */
2574  uint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */
2575  uint32_t TCR1CS:1; /* TCR1 Clock Source */
2576  uint32_t:5;
2577  uint32_t TCR1P:8; /* TCR1 Prescaler Control */
2578  } B;
2579  } TBCR_B;
2580 
2581  union { /* ETPU_B TCR1 Visibility Register */
2582  uint32_t R;
2583  struct {
2584  uint32_t:8;
2585  uint32_t TCR1:24;
2586  } B;
2587  } TB1R_B;
2588 
2589  union { /* ETPU_B TCR2 Visibility Register */
2590  uint32_t R;
2591  struct {
2592  uint32_t:8;
2593  uint32_t TCR2:24;
2594  } B;
2595  } TB2R_B;
2596 
2597  union { /* ETPU_B STAC Configuration Register */
2598  uint32_t R;
2599  struct {
2600  uint32_t REN1:1; /* Resource Enable TCR1 */
2601  uint32_t RSC1:1; /* Resource Control TCR1 */
2602  uint32_t:2;
2603  uint32_t SERVER_ID1:4; /* TCR1 Server ID */
2604  uint32_t:4;
2605  uint32_t SRV1:4; /* Resource Server Slot */
2606  uint32_t REN2:1; /* Resource Enable TCR2 */
2607  uint32_t RSC2:1; /* Resource Control TCR2 */
2608  uint32_t:2;
2609  uint32_t SERVER_ID2:4; /* TCR2 Server ID */
2610  uint32_t:4;
2611  uint32_t SRV2:4; /* Resource Server Slot */
2612  } B;
2613  } REDCR_B;
2614 
2615  uint32_t eTPU_reserved0050[4]; /* 0x0050-0x005F */
2616 
2617  union { /* Watchdog Timer Register A */
2618  uint32_t R;
2619  struct {
2620  uint32_t WDM:2; /* Watchdog Mode */
2621  uint32_t:14;
2622  uint32_t WDCNT:16; /* Watchdog Count */
2623  } B;
2624  } WDTR_A;
2625 
2626  uint32_t eTPU_reserved0064; /* 0x0064-0x0067 */
2627 
2628  union { /* Idle Counter Register A*/
2629  uint32_t R;
2630  struct {
2631  uint32_t IDLE_CNT:31;
2632  uint32_t ICLR:1; /* Idle Clear */
2633  } B;
2634 
2635  } IDLE_A;
2636 
2637  uint32_t eTPU_reserved006C; /* 0x006C-0x006F */
2638 
2639  union { /* Watchdog Timer Register B */
2640  uint32_t R;
2641  struct {
2642  uint32_t WDM:2; /* Watchdog Mode */
2643  uint32_t:14;
2644  uint32_t WDCNT:16; /* Watchdog Count */
2645  } B;
2646  } WDTR_B;
2647 
2648  uint32_t eTPU_reserved0074; /* 0x0074-0x0077 */
2649 
2650  union { /* Idle Counter Register B*/
2651  uint32_t R;
2652  struct {
2653  uint32_t IDLE_CNT:31;
2654  uint32_t ICLR:1; /* Idle Clear */
2655  } B;
2656  } IDLE_B;
2657 
2658  uint32_t eTPU_reserved007C; /* 0x007C-0x007F */
2659 
2660  uint32_t eTPU_reserved0080[96]; /* 0x0080-0x01FF */
2661 
2662 /*****************************Status and Control Registers**************************/
2663 
2664  union { /* ETPU_A Channel Interrut Status */
2665  uint32_t R;
2666  struct {
2667  uint32_t CIS31:1; /* Channel 31 Interrut Status */
2668  uint32_t CIS30:1; /* Channel 30 Interrut Status */
2669  uint32_t CIS29:1; /* Channel 29 Interrut Status */
2670  uint32_t CIS28:1; /* Channel 28 Interrut Status */
2671  uint32_t CIS27:1; /* Channel 27 Interrut Status */
2672  uint32_t CIS26:1; /* Channel 26 Interrut Status */
2673  uint32_t CIS25:1; /* Channel 25 Interrut Status */
2674  uint32_t CIS24:1; /* Channel 24 Interrut Status */
2675  uint32_t CIS23:1; /* Channel 23 Interrut Status */
2676  uint32_t CIS22:1; /* Channel 22 Interrut Status */
2677  uint32_t CIS21:1; /* Channel 21 Interrut Status */
2678  uint32_t CIS20:1; /* Channel 20 Interrut Status */
2679  uint32_t CIS19:1; /* Channel 19 Interrut Status */
2680  uint32_t CIS18:1; /* Channel 18 Interrut Status */
2681  uint32_t CIS17:1; /* Channel 17 Interrut Status */
2682  uint32_t CIS16:1; /* Channel 16 Interrut Status */
2683  uint32_t CIS15:1; /* Channel 15 Interrut Status */
2684  uint32_t CIS14:1; /* Channel 14 Interrut Status */
2685  uint32_t CIS13:1; /* Channel 13 Interrut Status */
2686  uint32_t CIS12:1; /* Channel 12 Interrut Status */
2687  uint32_t CIS11:1; /* Channel 11 Interrut Status */
2688  uint32_t CIS10:1; /* Channel 10 Interrut Status */
2689  uint32_t CIS9:1; /* Channel 9 Interrut Status */
2690  uint32_t CIS8:1; /* Channel 8 Interrut Status */
2691  uint32_t CIS7:1; /* Channel 7 Interrut Status */
2692  uint32_t CIS6:1; /* Channel 6 Interrut Status */
2693  uint32_t CIS5:1; /* Channel 5 Interrut Status */
2694  uint32_t CIS4:1; /* Channel 4 Interrut Status */
2695  uint32_t CIS3:1; /* Channel 3 Interrut Status */
2696  uint32_t CIS2:1; /* Channel 2 Interrut Status */
2697  uint32_t CIS1:1; /* Channel 1 Interrut Status */
2698  uint32_t CIS0:1; /* Channel 0 Interrut Status */
2699  } B;
2700  } CISR_A;
2701 
2702  union { /* ETPU_B Channel Interruput Status */
2703  uint32_t R;
2704  struct {
2705  uint32_t CIS31:1; /* Channel 31 Interrut Status */
2706  uint32_t CIS30:1; /* Channel 30 Interrut Status */
2707  uint32_t CIS29:1; /* Channel 29 Interrut Status */
2708  uint32_t CIS28:1; /* Channel 28 Interrut Status */
2709  uint32_t CIS27:1; /* Channel 27 Interrut Status */
2710  uint32_t CIS26:1; /* Channel 26 Interrut Status */
2711  uint32_t CIS25:1; /* Channel 25 Interrut Status */
2712  uint32_t CIS24:1; /* Channel 24 Interrut Status */
2713  uint32_t CIS23:1; /* Channel 23 Interrut Status */
2714  uint32_t CIS22:1; /* Channel 22 Interrut Status */
2715  uint32_t CIS21:1; /* Channel 21 Interrut Status */
2716  uint32_t CIS20:1; /* Channel 20 Interrut Status */
2717  uint32_t CIS19:1; /* Channel 19 Interrut Status */
2718  uint32_t CIS18:1; /* Channel 18 Interrut Status */
2719  uint32_t CIS17:1; /* Channel 17 Interrut Status */
2720  uint32_t CIS16:1; /* Channel 16 Interrut Status */
2721  uint32_t CIS15:1; /* Channel 15 Interrut Status */
2722  uint32_t CIS14:1; /* Channel 14 Interrut Status */
2723  uint32_t CIS13:1; /* Channel 13 Interrut Status */
2724  uint32_t CIS12:1; /* Channel 12 Interrut Status */
2725  uint32_t CIS11:1; /* Channel 11 Interrut Status */
2726  uint32_t CIS10:1; /* Channel 10 Interrut Status */
2727  uint32_t CIS9:1; /* Channel 9 Interrut Status */
2728  uint32_t CIS8:1; /* Channel 8 Interrut Status */
2729  uint32_t CIS7:1; /* Channel 7 Interrut Status */
2730  uint32_t CIS6:1; /* Channel 6 Interrut Status */
2731  uint32_t CIS5:1; /* Channel 5 Interrut Status */
2732  uint32_t CIS4:1; /* Channel 4 Interrut Status */
2733  uint32_t CIS3:1; /* Channel 3 Interrut Status */
2734  uint32_t CIS2:1; /* Channel 2 Interrut Status */
2735  uint32_t CIS1:1; /* Channel 1 Interrupt Status */
2736  uint32_t CIS0:1; /* Channel 0 Interrupt Status */
2737  } B;
2738  } CISR_B;
2739 
2740  uint32_t eTPU_reserved0208[2]; /* 0x0208-0x020F */
2741 
2742  union { /* ETPU_A Data Transfer Request Status */
2743  uint32_t R;
2744  struct {
2745  uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
2746  uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
2747  uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
2748  uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
2749  uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
2750  uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
2751  uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
2752  uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
2753  uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
2754  uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
2755  uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
2756  uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
2757  uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
2758  uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
2759  uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
2760  uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
2761  uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
2762  uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
2763  uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
2764  uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
2765  uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
2766  uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
2767  uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
2768  uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
2769  uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
2770  uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
2771  uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
2772  uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
2773  uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
2774  uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
2775  uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
2776  uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
2777  } B;
2778  } CDTRSR_A;
2779 
2780  union { /* ETPU_B Data Transfer Request Status */
2781  uint32_t R;
2782  struct {
2783  uint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */
2784  uint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */
2785  uint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */
2786  uint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */
2787  uint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */
2788  uint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */
2789  uint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */
2790  uint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */
2791  uint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */
2792  uint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */
2793  uint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */
2794  uint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */
2795  uint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */
2796  uint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */
2797  uint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */
2798  uint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */
2799  uint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */
2800  uint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */
2801  uint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */
2802  uint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */
2803  uint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */
2804  uint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */
2805  uint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */
2806  uint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */
2807  uint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */
2808  uint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */
2809  uint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */
2810  uint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */
2811  uint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */
2812  uint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */
2813  uint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */
2814  uint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */
2815  } B;
2816  } CDTRSR_B;
2817 
2818  uint32_t eTPU_reserved0218[2]; /* 0x0218-0x021F */
2819 
2820  union { /* ETPU_A Interruput Overflow Status */
2821  uint32_t R;
2822  struct {
2823  uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
2824  uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
2825  uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
2826  uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
2827  uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
2828  uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
2829  uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
2830  uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
2831  uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
2832  uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
2833  uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
2834  uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
2835  uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
2836  uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
2837  uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
2838  uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
2839  uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
2840  uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
2841  uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
2842  uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
2843  uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
2844  uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
2845  uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
2846  uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
2847  uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
2848  uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
2849  uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
2850  uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
2851  uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
2852  uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
2853  uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
2854  uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
2855  } B;
2856  } CIOSR_A;
2857 
2858  union { /* ETPU_B Interruput Overflow Status */
2859  uint32_t R;
2860  struct {
2861  uint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */
2862  uint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */
2863  uint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */
2864  uint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */
2865  uint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */
2866  uint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */
2867  uint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */
2868  uint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */
2869  uint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */
2870  uint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */
2871  uint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */
2872  uint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */
2873  uint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */
2874  uint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */
2875  uint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */
2876  uint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */
2877  uint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */
2878  uint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */
2879  uint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */
2880  uint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */
2881  uint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */
2882  uint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */
2883  uint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */
2884  uint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */
2885  uint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */
2886  uint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */
2887  uint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */
2888  uint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */
2889  uint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */
2890  uint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */
2891  uint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */
2892  uint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */
2893  } B;
2894  } CIOSR_B;
2895 
2896  uint32_t eTPU_reserved0228[2]; /* 0x0228-0x022F */
2897 
2898  union { /* ETPU_A Data Transfer Overflow Status */
2899  uint32_t R;
2900  struct {
2901  uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
2902  uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
2903  uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
2904  uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
2905  uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
2906  uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
2907  uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
2908  uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
2909  uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
2910  uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
2911  uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
2912  uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
2913  uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
2914  uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
2915  uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
2916  uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
2917  uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
2918  uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
2919  uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
2920  uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
2921  uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
2922  uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
2923  uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
2924  uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
2925  uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
2926  uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
2927  uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
2928  uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
2929  uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
2930  uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
2931  uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
2932  uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
2933  } B;
2934  } CDTROSR_A;
2935 
2936  union { /* ETPU_B Data Transfer Overflow Status */
2937  uint32_t R;
2938  struct {
2939  uint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */
2940  uint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */
2941  uint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */
2942  uint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */
2943  uint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */
2944  uint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */
2945  uint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */
2946  uint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */
2947  uint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */
2948  uint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */
2949  uint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */
2950  uint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */
2951  uint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */
2952  uint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */
2953  uint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */
2954  uint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */
2955  uint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */
2956  uint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */
2957  uint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */
2958  uint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */
2959  uint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */
2960  uint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */
2961  uint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */
2962  uint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */
2963  uint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */
2964  uint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */
2965  uint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */
2966  uint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */
2967  uint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */
2968  uint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */
2969  uint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */
2970  uint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */
2971  } B;
2972  } CDTROSR_B;
2973 
2974  uint32_t eTPU_reserved0238[2]; /* 0x0238-0x023F */
2975 
2976  union { /* ETPU_A Channel Interruput Enable */
2977  uint32_t R;
2978  struct {
2979  uint32_t CIE31:1; /* Channel 31 Interruput Enable */
2980  uint32_t CIE30:1; /* Channel 30 Interruput Enable */
2981  uint32_t CIE29:1; /* Channel 29 Interruput Enable */
2982  uint32_t CIE28:1; /* Channel 28 Interruput Enable */
2983  uint32_t CIE27:1; /* Channel 27 Interruput Enable */
2984  uint32_t CIE26:1; /* Channel 26 Interruput Enable */
2985  uint32_t CIE25:1; /* Channel 25 Interruput Enable */
2986  uint32_t CIE24:1; /* Channel 24 Interruput Enable */
2987  uint32_t CIE23:1; /* Channel 23 Interruput Enable */
2988  uint32_t CIE22:1; /* Channel 22 Interruput Enable */
2989  uint32_t CIE21:1; /* Channel 21 Interruput Enable */
2990  uint32_t CIE20:1; /* Channel 20 Interruput Enable */
2991  uint32_t CIE19:1; /* Channel 19 Interruput Enable */
2992  uint32_t CIE18:1; /* Channel 18 Interruput Enable */
2993  uint32_t CIE17:1; /* Channel 17 Interruput Enable */
2994  uint32_t CIE16:1; /* Channel 16 Interruput Enable */
2995  uint32_t CIE15:1; /* Channel 15 Interruput Enable */
2996  uint32_t CIE14:1; /* Channel 14 Interruput Enable */
2997  uint32_t CIE13:1; /* Channel 13 Interruput Enable */
2998  uint32_t CIE12:1; /* Channel 12 Interruput Enable */
2999  uint32_t CIE11:1; /* Channel 11 Interruput Enable */
3000  uint32_t CIE10:1; /* Channel 10 Interruput Enable */
3001  uint32_t CIE9:1; /* Channel 9 Interruput Enable */
3002  uint32_t CIE8:1; /* Channel 8 Interruput Enable */
3003  uint32_t CIE7:1; /* Channel 7 Interruput Enable */
3004  uint32_t CIE6:1; /* Channel 6 Interruput Enable */
3005  uint32_t CIE5:1; /* Channel 5 Interruput Enable */
3006  uint32_t CIE4:1; /* Channel 4 Interruput Enable */
3007  uint32_t CIE3:1; /* Channel 3 Interruput Enable */
3008  uint32_t CIE2:1; /* Channel 2 Interruput Enable */
3009  uint32_t CIE1:1; /* Channel 1 Interruput Enable */
3010  uint32_t CIE0:1; /* Channel 0 Interruput Enable */
3011  } B;
3012  } CIER_A;
3013 
3014  union { /* ETPU_B Channel Interruput Enable */
3015  uint32_t R;
3016  struct {
3017  uint32_t CIE31:1; /* Channel 31 Interruput Enable */
3018  uint32_t CIE30:1; /* Channel 30 Interruput Enable */
3019  uint32_t CIE29:1; /* Channel 29 Interruput Enable */
3020  uint32_t CIE28:1; /* Channel 28 Interruput Enable */
3021  uint32_t CIE27:1; /* Channel 27 Interruput Enable */
3022  uint32_t CIE26:1; /* Channel 26 Interruput Enable */
3023  uint32_t CIE25:1; /* Channel 25 Interruput Enable */
3024  uint32_t CIE24:1; /* Channel 24 Interruput Enable */
3025  uint32_t CIE23:1; /* Channel 23 Interruput Enable */
3026  uint32_t CIE22:1; /* Channel 22 Interruput Enable */
3027  uint32_t CIE21:1; /* Channel 21 Interruput Enable */
3028  uint32_t CIE20:1; /* Channel 20 Interruput Enable */
3029  uint32_t CIE19:1; /* Channel 19 Interruput Enable */
3030  uint32_t CIE18:1; /* Channel 18 Interruput Enable */
3031  uint32_t CIE17:1; /* Channel 17 Interruput Enable */
3032  uint32_t CIE16:1; /* Channel 16 Interruput Enable */
3033  uint32_t CIE15:1; /* Channel 15 Interruput Enable */
3034  uint32_t CIE14:1; /* Channel 14 Interruput Enable */
3035  uint32_t CIE13:1; /* Channel 13 Interruput Enable */
3036  uint32_t CIE12:1; /* Channel 12 Interruput Enable */
3037  uint32_t CIE11:1; /* Channel 11 Interruput Enable */
3038  uint32_t CIE10:1; /* Channel 10 Interruput Enable */
3039  uint32_t CIE9:1; /* Channel 9 Interruput Enable */
3040  uint32_t CIE8:1; /* Channel 8 Interruput Enable */
3041  uint32_t CIE7:1; /* Channel 7 Interruput Enable */
3042  uint32_t CIE6:1; /* Channel 6 Interruput Enable */
3043  uint32_t CIE5:1; /* Channel 5 Interruput Enable */
3044  uint32_t CIE4:1; /* Channel 4 Interruput Enable */
3045  uint32_t CIE3:1; /* Channel 3 Interruput Enable */
3046  uint32_t CIE2:1; /* Channel 2 Interruput Enable */
3047  uint32_t CIE1:1; /* Channel 1 Interruput Enable */
3048  uint32_t CIE0:1; /* Channel 0 Interruput Enable */
3049  } B;
3050  } CIER_B;
3051 
3052  uint32_t eTPU_reserved0248[2]; /* 0x0248-0x024F */
3053 
3054  union { /* ETPU_A Channel Data Transfer Request Enable */
3055  uint32_t R;
3056  struct {
3057  uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
3058  uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
3059  uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
3060  uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
3061  uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
3062  uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
3063  uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
3064  uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
3065  uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
3066  uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
3067  uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
3068  uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
3069  uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
3070  uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
3071  uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
3072  uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
3073  uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
3074  uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
3075  uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
3076  uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
3077  uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
3078  uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
3079  uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
3080  uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
3081  uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
3082  uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
3083  uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
3084  uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
3085  uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
3086  uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
3087  uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
3088  uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
3089  } B;
3090  } CDTRER_A;
3091 
3092  union { /* ETPU_B Channel Data Transfer Request Enable */
3093  uint32_t R;
3094  struct {
3095  uint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */
3096  uint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */
3097  uint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */
3098  uint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */
3099  uint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */
3100  uint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */
3101  uint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */
3102  uint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */
3103  uint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */
3104  uint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */
3105  uint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */
3106  uint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */
3107  uint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */
3108  uint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */
3109  uint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */
3110  uint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */
3111  uint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */
3112  uint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */
3113  uint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */
3114  uint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */
3115  uint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */
3116  uint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */
3117  uint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */
3118  uint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */
3119  uint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */
3120  uint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */
3121  uint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */
3122  uint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */
3123  uint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */
3124  uint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */
3125  uint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */
3126  uint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */
3127  } B;
3128  } CDTRER_B;
3129 
3130  uint32_t eTPU_reserved0258[2]; /* 0x0258-0x025F */
3131 
3132  union { /* Watchdog Status Register A */
3133  uint32_t R;
3134  struct {
3135  uint32_t WDS31:1;
3136  uint32_t WDS30:1;
3137  uint32_t WDS29:1;
3138  uint32_t WDS28:1;
3139  uint32_t WDS27:1;
3140  uint32_t WDS26:1;
3141  uint32_t WDS25:1;
3142  uint32_t WDS24:1;
3143  uint32_t WDS23:1;
3144  uint32_t WDS22:1;
3145  uint32_t WDS21:1;
3146  uint32_t WDS20:1;
3147  uint32_t WDS19:1;
3148  uint32_t WDS18:1;
3149  uint32_t WDS17:1;
3150  uint32_t WDS16:1;
3151  uint32_t WDS15:1;
3152  uint32_t WDS14:1;
3153  uint32_t WDS13:1;
3154  uint32_t WDS12:1;
3155  uint32_t WDS11:1;
3156  uint32_t WDS10:1;
3157  uint32_t WDS9:1;
3158  uint32_t WDS8:1;
3159  uint32_t WDS7:1;
3160  uint32_t WDS6:1;
3161  uint32_t WDS5:1;
3162  uint32_t WDS4:1;
3163  uint32_t WDS3:1;
3164  uint32_t WDS2:1;
3165  uint32_t WDS1:1;
3166  uint32_t WDS0:1;
3167  } B;
3168  } WDSR_A;
3169 
3170  union { /* Watchdog Status Register B */
3171  uint32_t R;
3172  struct {
3173  uint32_t WDS31:1;
3174  uint32_t WDS30:1;
3175  uint32_t WDS29:1;
3176  uint32_t WDS28:1;
3177  uint32_t WDS27:1;
3178  uint32_t WDS26:1;
3179  uint32_t WDS25:1;
3180  uint32_t WDS24:1;
3181  uint32_t WDS23:1;
3182  uint32_t WDS22:1;
3183  uint32_t WDS21:1;
3184  uint32_t WDS20:1;
3185  uint32_t WDS19:1;
3186  uint32_t WDS18:1;
3187  uint32_t WDS17:1;
3188  uint32_t WDS16:1;
3189  uint32_t WDS15:1;
3190  uint32_t WDS14:1;
3191  uint32_t WDS13:1;
3192  uint32_t WDS12:1;
3193  uint32_t WDS11:1;
3194  uint32_t WDS10:1;
3195  uint32_t WDS9:1;
3196  uint32_t WDS8:1;
3197  uint32_t WDS7:1;
3198  uint32_t WDS6:1;
3199  uint32_t WDS5:1;
3200  uint32_t WDS4:1;
3201  uint32_t WDS3:1;
3202  uint32_t WDS2:1;
3203  uint32_t WDS1:1;
3204  uint32_t WDS0:1;
3205  } B;
3206  } WDSR_B;
3207 
3208  uint32_t eTPU_reserved0268[6]; /* 0x0268-0x027F */
3209 
3210  union { /* ETPU_A Channel Pending Service Status */
3211  uint32_t R;
3212  struct {
3213  uint32_t SR31:1; /* Channel 31 Pending Service Status */
3214  uint32_t SR30:1; /* Channel 30 Pending Service Status */
3215  uint32_t SR29:1; /* Channel 29 Pending Service Status */
3216  uint32_t SR28:1; /* Channel 28 Pending Service Status */
3217  uint32_t SR27:1; /* Channel 27 Pending Service Status */
3218  uint32_t SR26:1; /* Channel 26 Pending Service Status */
3219  uint32_t SR25:1; /* Channel 25 Pending Service Status */
3220  uint32_t SR24:1; /* Channel 24 Pending Service Status */
3221  uint32_t SR23:1; /* Channel 23 Pending Service Status */
3222  uint32_t SR22:1; /* Channel 22 Pending Service Status */
3223  uint32_t SR21:1; /* Channel 21 Pending Service Status */
3224  uint32_t SR20:1; /* Channel 20 Pending Service Status */
3225  uint32_t SR19:1; /* Channel 19 Pending Service Status */
3226  uint32_t SR18:1; /* Channel 18 Pending Service Status */
3227  uint32_t SR17:1; /* Channel 17 Pending Service Status */
3228  uint32_t SR16:1; /* Channel 16 Pending Service Status */
3229  uint32_t SR15:1; /* Channel 15 Pending Service Status */
3230  uint32_t SR14:1; /* Channel 14 Pending Service Status */
3231  uint32_t SR13:1; /* Channel 13 Pending Service Status */
3232  uint32_t SR12:1; /* Channel 12 Pending Service Status */
3233  uint32_t SR11:1; /* Channel 11 Pending Service Status */
3234  uint32_t SR10:1; /* Channel 10 Pending Service Status */
3235  uint32_t SR9:1; /* Channel 9 Pending Service Status */
3236  uint32_t SR8:1; /* Channel 8 Pending Service Status */
3237  uint32_t SR7:1; /* Channel 7 Pending Service Status */
3238  uint32_t SR6:1; /* Channel 6 Pending Service Status */
3239  uint32_t SR5:1; /* Channel 5 Pending Service Status */
3240  uint32_t SR4:1; /* Channel 4 Pending Service Status */
3241  uint32_t SR3:1; /* Channel 3 Pending Service Status */
3242  uint32_t SR2:1; /* Channel 2 Pending Service Status */
3243  uint32_t SR1:1; /* Channel 1 Pending Service Status */
3244  uint32_t SR0:1; /* Channel 0 Pending Service Status */
3245  } B;
3246  } CPSSR_A;
3247 
3248  union { /* ETPU_B Channel Pending Service Status */
3249  uint32_t R;
3250  struct {
3251  uint32_t SR31:1; /* Channel 31 Pending Service Status */
3252  uint32_t SR30:1; /* Channel 30 Pending Service Status */
3253  uint32_t SR29:1; /* Channel 29 Pending Service Status */
3254  uint32_t SR28:1; /* Channel 28 Pending Service Status */
3255  uint32_t SR27:1; /* Channel 27 Pending Service Status */
3256  uint32_t SR26:1; /* Channel 26 Pending Service Status */
3257  uint32_t SR25:1; /* Channel 25 Pending Service Status */
3258  uint32_t SR24:1; /* Channel 24 Pending Service Status */
3259  uint32_t SR23:1; /* Channel 23 Pending Service Status */
3260  uint32_t SR22:1; /* Channel 22 Pending Service Status */
3261  uint32_t SR21:1; /* Channel 21 Pending Service Status */
3262  uint32_t SR20:1; /* Channel 20 Pending Service Status */
3263  uint32_t SR19:1; /* Channel 19 Pending Service Status */
3264  uint32_t SR18:1; /* Channel 18 Pending Service Status */
3265  uint32_t SR17:1; /* Channel 17 Pending Service Status */
3266  uint32_t SR16:1; /* Channel 16 Pending Service Status */
3267  uint32_t SR15:1; /* Channel 15 Pending Service Status */
3268  uint32_t SR14:1; /* Channel 14 Pending Service Status */
3269  uint32_t SR13:1; /* Channel 13 Pending Service Status */
3270  uint32_t SR12:1; /* Channel 12 Pending Service Status */
3271  uint32_t SR11:1; /* Channel 11 Pending Service Status */
3272  uint32_t SR10:1; /* Channel 10 Pending Service Status */
3273  uint32_t SR9:1; /* Channel 9 Pending Service Status */
3274  uint32_t SR8:1; /* Channel 8 Pending Service Status */
3275  uint32_t SR7:1; /* Channel 7 Pending Service Status */
3276  uint32_t SR6:1; /* Channel 6 Pending Service Status */
3277  uint32_t SR5:1; /* Channel 5 Pending Service Status */
3278  uint32_t SR4:1; /* Channel 4 Pending Service Status */
3279  uint32_t SR3:1; /* Channel 3 Pending Service Status */
3280  uint32_t SR2:1; /* Channel 2 Pending Service Status */
3281  uint32_t SR1:1; /* Channel 1 Pending Service Status */
3282  uint32_t SR0:1; /* Channel 0 Pending Service Status */
3283  } B;
3284  } CPSSR_B;
3285 
3286  uint32_t eTPU_reserved0288[2]; /* 0x0288-0x028F */
3287 
3288  union { /* ETPU_A Channel Service Status */
3289  uint32_t R;
3290  struct {
3291  uint32_t SS31:1; /* Channel 31 Service Status */
3292  uint32_t SS30:1; /* Channel 30 Service Status */
3293  uint32_t SS29:1; /* Channel 29 Service Status */
3294  uint32_t SS28:1; /* Channel 28 Service Status */
3295  uint32_t SS27:1; /* Channel 27 Service Status */
3296  uint32_t SS26:1; /* Channel 26 Service Status */
3297  uint32_t SS25:1; /* Channel 25 Service Status */
3298  uint32_t SS24:1; /* Channel 24 Service Status */
3299  uint32_t SS23:1; /* Channel 23 Service Status */
3300  uint32_t SS22:1; /* Channel 22 Service Status */
3301  uint32_t SS21:1; /* Channel 21 Service Status */
3302  uint32_t SS20:1; /* Channel 20 Service Status */
3303  uint32_t SS19:1; /* Channel 19 Service Status */
3304  uint32_t SS18:1; /* Channel 18 Service Status */
3305  uint32_t SS17:1; /* Channel 17 Service Status */
3306  uint32_t SS16:1; /* Channel 16 Service Status */
3307  uint32_t SS15:1; /* Channel 15 Service Status */
3308  uint32_t SS14:1; /* Channel 14 Service Status */
3309  uint32_t SS13:1; /* Channel 13 Service Status */
3310  uint32_t SS12:1; /* Channel 12 Service Status */
3311  uint32_t SS11:1; /* Channel 11 Service Status */
3312  uint32_t SS10:1; /* Channel 10 Service Status */
3313  uint32_t SS9:1; /* Channel 9 Service Status */
3314  uint32_t SS8:1; /* Channel 8 Service Status */
3315  uint32_t SS7:1; /* Channel 7 Service Status */
3316  uint32_t SS6:1; /* Channel 6 Service Status */
3317  uint32_t SS5:1; /* Channel 5 Service Status */
3318  uint32_t SS4:1; /* Channel 4 Service Status */
3319  uint32_t SS3:1; /* Channel 3 Service Status */
3320  uint32_t SS2:1; /* Channel 2 Service Status */
3321  uint32_t SS1:1; /* Channel 1 Service Status */
3322  uint32_t SS0:1; /* Channel 0 Service Status */
3323  } B;
3324  } CSSR_A;
3325 
3326  union { /* ETPU_B Channel Service Status */
3327  uint32_t R;
3328  struct {
3329  uint32_t SS31:1; /* Channel 31 Service Status */
3330  uint32_t SS30:1; /* Channel 30 Service Status */
3331  uint32_t SS29:1; /* Channel 29 Service Status */
3332  uint32_t SS28:1; /* Channel 28 Service Status */
3333  uint32_t SS27:1; /* Channel 27 Service Status */
3334  uint32_t SS26:1; /* Channel 26 Service Status */
3335  uint32_t SS25:1; /* Channel 25 Service Status */
3336  uint32_t SS24:1; /* Channel 24 Service Status */
3337  uint32_t SS23:1; /* Channel 23 Service Status */
3338  uint32_t SS22:1; /* Channel 22 Service Status */
3339  uint32_t SS21:1; /* Channel 21 Service Status */
3340  uint32_t SS20:1; /* Channel 20 Service Status */
3341  uint32_t SS19:1; /* Channel 19 Service Status */
3342  uint32_t SS18:1; /* Channel 18 Service Status */
3343  uint32_t SS17:1; /* Channel 17 Service Status */
3344  uint32_t SS16:1; /* Channel 16 Service Status */
3345  uint32_t SS15:1; /* Channel 15 Service Status */
3346  uint32_t SS14:1; /* Channel 14 Service Status */
3347  uint32_t SS13:1; /* Channel 13 Service Status */
3348  uint32_t SS12:1; /* Channel 12 Service Status */
3349  uint32_t SS11:1; /* Channel 11 Service Status */
3350  uint32_t SS10:1; /* Channel 10 Service Status */
3351  uint32_t SS9:1; /* Channel 9 Service Status */
3352  uint32_t SS8:1; /* Channel 8 Service Status */
3353  uint32_t SS7:1; /* Channel 7 Service Status */
3354  uint32_t SS6:1; /* Channel 6 Service Status */
3355  uint32_t SS5:1; /* Channel 5 Service Status */
3356  uint32_t SS4:1; /* Channel 4 Service Status */
3357  uint32_t SS3:1; /* Channel 3 Service Status */
3358  uint32_t SS2:1; /* Channel 2 Service Status */
3359  uint32_t SS1:1; /* Channel 1 Service Status */
3360  uint32_t SS0:1; /* Channel 0 Service Status */
3361  } B;
3362  } CSSR_B;
3363 
3364  uint32_t eTPU_reserved0298[2]; /* 0x0298-0x029F */
3365 
3366  uint32_t eTPU_reserved02A0[88]; /* 0x02A0-0x03FF */
3367 
3368 /*****************************Channels********************************/
3369 
3370  struct {
3371  union { /* Channel Configuration Register */
3372  uint32_t R;
3373  struct {
3374  uint32_t CIE:1; /* Channel Interruput Enable */
3375  uint32_t DTRE:1; /* Data Transfer Request Enable */
3376  uint32_t CPR:2; /* Channel Priority */
3377  uint32_t:2;
3378  uint32_t ETPD:1;
3379  uint32_t ETCS:1; /* Entry Table Condition Select */
3380  uint32_t:3;
3381  uint32_t CFS:5; /* Channel Function Select */
3382  uint32_t ODIS:1; /* Output disable */
3383  uint32_t OPOL:1; /* output polarity */
3384  uint32_t:3;
3385  uint32_t CPBA:11; /* Channel Parameter Base Address */
3386  } B;
3387  } CR;
3388 
3389  union { /* Channel Status Control Register */
3390  uint32_t R;
3391  struct {
3392  uint32_t CIS:1; /* Channel Interruput Status */
3393  uint32_t CIOS:1; /* Channel Interruput Overflow Status */
3394  uint32_t:6;
3395  uint32_t DTRS:1; /* Data Transfer Status */
3396  uint32_t DTROS:1; /* Data Transfer Overflow Status */
3397  uint32_t:6;
3398  uint32_t IPS:1; /* Input Pin State */
3399  uint32_t OPS:1; /* Output Pin State */
3400  uint32_t OBE:1; /* Output Buffer Enable */
3401  uint32_t:11;
3402  uint32_t FM1:1; /* Function mode */
3403  uint32_t FM0:1; /* Function mode */
3404  } B;
3405  } SCR;
3406 
3407  union { /* Channel Host Service Request Register */
3408  uint32_t R;
3409  struct {
3410  uint32_t:29; /* Host Service Request */
3411  uint32_t HSR:3;
3412  } B;
3413  } HSRR;
3414 
3415  uint32_t eTPU_ch_reserved00C; /* channel offset 0x00C-0x00F */
3416 
3417  } CHAN[127];
3418 
3419  uint32_t eTPU_reserved1000[7168]; /* 0x1000-0x7FFF */
3420 
3421  };
3422 
3423 /****************************************************************************/
3424 /* MODULE : PIT / RTI */
3425 /****************************************************************************/
3426 
3427  struct PIT_tag {
3428  union { /* Module Configuration Register */
3429  uint32_t R;
3430  struct {
3431  uint32_t:29;
3432  uint32_t MDIS_RTI:1;
3433  uint32_t MDIS:1;
3434  uint32_t FRZ:1;
3435  } B;
3436  } MCR;
3437 
3438  uint32_t PIT_reserved0004[59]; /* 0x0004-0x00EF */
3439 
3440  struct {
3441  union {
3442  uint32_t R; /* <URM>TSVn</URM> */
3443  } LDVAL; /* Timer Load Value Register */
3444 
3445  union {
3446  uint32_t R; /* <URM>TVLn</URM> */
3447  } CVAL; /* Current Timer Value Register */
3448 
3449  union {
3450  uint32_t R;
3451  struct {
3452  uint32_t:30;
3453  uint32_t TIE:1;
3454  uint32_t TEN:1;
3455  } B;
3456  } TCTRL; /* Timer Control Register */
3457 
3458  union {
3459  uint32_t R;
3460  struct {
3461  uint32_t:31;
3462  uint32_t TIF:1;
3463  } B;
3464  } TFLG; /* Timer Flag Register */
3465  } RTI; /* RTI Channel */
3466 
3467  struct {
3468  union {
3469  uint32_t R;
3470  struct {
3471  uint32_t TSV:32;
3472  } B;
3473  } LDVAL;
3474 
3475  union {
3476  uint32_t R;
3477  struct {
3478  uint32_t TVL:32;
3479  } B;
3480  } CVAL;
3481 
3482  union {
3483  uint32_t R;
3484  struct {
3485  uint32_t:30;
3486  uint32_t TIE:1;
3487  uint32_t TEN:1;
3488  } B;
3489  } TCTRL;
3490 
3491  union {
3492  uint32_t R;
3493  struct {
3494  uint32_t:31;
3495  uint32_t TIF:1;
3496  } B;
3497  } TFLG;
3498  } CH[4];
3499 
3500  uint32_t PIT_reserved00140[4016]; /* 0x0140-0x3FFF */
3501  };
3502 
3503 /****************************************************************************/
3504 /* MODULE : XBAR CrossBar */
3505 /****************************************************************************/
3506 
3507  struct XBAR_tag {
3508 
3509  union { /* Master Priority Register for Slave Port 0 */
3510  uint32_t R;
3511  struct {
3512  uint32_t:1;
3513  uint32_t MSTR7:3; /* EBI (development bus) */
3514  uint32_t:1;
3515  uint32_t MSTR6:3; /* FlexRay */
3516  uint32_t:1;
3517  uint32_t MSTR5:3; /* eDMA_B */
3518  uint32_t:1;
3519  uint32_t MSTR4:3; /* eDMA_A */
3520  uint32_t:1;
3521  uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */
3522  uint32_t:1;
3523  uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */
3524  uint32_t:1;
3525  uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */
3526  uint32_t:1;
3527  uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */
3528  } B;
3529  } MPR0;
3530 
3531  uint32_t XBAR_reserved0004[3]; /* 0x0004-0x000F */
3532 
3533  union { /* General Purpose Control Register for Slave Port 0 */
3534  uint32_t R;
3535  struct {
3536  uint32_t RO:1;
3537  uint32_t:21;
3538  uint32_t ARB:2;
3539  uint32_t:2;
3540  uint32_t PCTL:2;
3541  uint32_t:1;
3542  uint32_t PARK:3;
3543  } B;
3544  } SGPCR0;
3545 
3546  uint32_t XBAR_reserved0014[59]; /* 0x0014-0x00FF */
3547 
3548  union { /* Master Priority Register for Slave Port 1 */
3549  uint32_t R;
3550  struct {
3551  uint32_t:1;
3552  uint32_t MSTR7:3; /* EBI (development bus) */
3553  uint32_t:1;
3554  uint32_t MSTR6:3; /* FlexRay */
3555  uint32_t:1;
3556  uint32_t MSTR5:3; /* eDMA_B */
3557  uint32_t:1;
3558  uint32_t MSTR4:3; /* eDMA_A */
3559  uint32_t:1;
3560  uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */
3561  uint32_t:1;
3562  uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */
3563  uint32_t:1;
3564  uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */
3565  uint32_t:1;
3566  uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */
3567  } B;
3568  } MPR1;
3569 
3570  uint32_t XBAR_reserved0104[3]; /* 0x0104-0x010F */
3571 
3572  union { /* General Purpose Control Register for Slave Port 1 */
3573  uint32_t R;
3574  struct {
3575  uint32_t RO:1;
3576  uint32_t:21;
3577  uint32_t ARB:2;
3578  uint32_t:2;
3579  uint32_t PCTL:2;
3580  uint32_t:1;
3581  uint32_t PARK:3;
3582  } B;
3583  } SGPCR1;
3584 
3585  uint32_t XBAR_reserved0114[59]; /* 0x0114-0x01FF */
3586 
3587  union { /* Master Priority Register for Slave Port 2 */
3588  uint32_t R;
3589  struct {
3590  uint32_t:1;
3591  uint32_t MSTR7:3; /* EBI (development bus) */
3592  uint32_t:1;
3593  uint32_t MSTR6:3; /* FlexRay */
3594  uint32_t:1;
3595  uint32_t MSTR5:3; /* eDMA_B */
3596  uint32_t:1;
3597  uint32_t MSTR4:3; /* eDMA_A */
3598  uint32_t:1;
3599  uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */
3600  uint32_t:1;
3601  uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */
3602  uint32_t:1;
3603  uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */
3604  uint32_t:1;
3605  uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */
3606  } B;
3607  } MPR2;
3608 
3609  uint32_t XBAR_reserved0204[3]; /* 0x0204-0x020F */
3610 
3611  union { /* General Purpose Control Register for Slave Port 2 */
3612  uint32_t R;
3613  struct {
3614  uint32_t RO:1;
3615  uint32_t:21;
3616  uint32_t ARB:2;
3617  uint32_t:2;
3618  uint32_t PCTL:2;
3619  uint32_t:1;
3620  uint32_t PARK:3;
3621  } B;
3622  } SGPCR2;
3623 
3624  uint32_t XBAR_reserved0214[59]; /* 0x0214-0x02FF */
3625 
3626  uint32_t XBAR_reserved0300[64]; /* 0x0300-0x03FF */
3627 
3628  uint32_t XBAR_reserved0400[64]; /* 0x0400-0x04FF */
3629 
3630  uint32_t XBAR_reserved0500[64]; /* 0x0500-0x05FF */
3631 
3632  union { /* Master Priority Register for Slave Port 6 */
3633  uint32_t R;
3634  struct {
3635  uint32_t:1;
3636  uint32_t MSTR7:3; /* EBI (development bus) */
3637  uint32_t:1;
3638  uint32_t MSTR6:3; /* FlexRay */
3639  uint32_t:1;
3640  uint32_t MSTR5:3; /* eDMA_B */
3641  uint32_t:1;
3642  uint32_t MSTR4:3; /* eDMA_A */
3643  uint32_t:1;
3644  uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */
3645  uint32_t:1;
3646  uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */
3647  uint32_t:1;
3648  uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */
3649  uint32_t:1;
3650  uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */
3651  } B;
3652  } MPR6;
3653 
3654  uint32_t XBAR_reserved604[3]; /* 0x0604-0x060F */
3655 
3656  union { /* General Purpose Control Register for Slave Port 6 */
3657  uint32_t R;
3658  struct {
3659  uint32_t RO:1;
3660  uint32_t:21;
3661  uint32_t ARB:2;
3662  uint32_t:2;
3663  uint32_t PCTL:2;
3664  uint32_t:1;
3665  uint32_t PARK:3;
3666  } B;
3667  } SGPCR6;
3668 
3669  uint32_t XBAR_reserved0614[59]; /* 0x0614-0x06FF */
3670 
3671  union { /* Master Priority Register for Slave Port 7 */
3672  uint32_t R;
3673  struct {
3674  uint32_t:1;
3675  uint32_t MSTR7:3; /* EBI (development bus) */
3676  uint32_t:1;
3677  uint32_t MSTR6:3; /* FlexRay */
3678  uint32_t:1;
3679  uint32_t MSTR5:3; /* eDMA_B */
3680  uint32_t:1;
3681  uint32_t MSTR4:3; /* eDMA_A */
3682  uint32_t:1;
3683  uint32_t MSTR3:3; /* !!! Unsupported in Mamba !!! - Legacy FEC */
3684  uint32_t:1;
3685  uint32_t MSTR2:3; /* !!! Unsupported in Mamba !!! - Legacy EBI */
3686  uint32_t:1;
3687  uint32_t MSTR1:3; /* e200z7 core-Data, and Nexus 3 - Legacy was eDMA_A */
3688  uint32_t:1;
3689  uint32_t MSTR0:3; /* e200z7 core-CPU Instruction - Legacy was z6 core-Instruction/Data & Nexus */
3690  } B;
3691  } MPR7;
3692 
3693  uint32_t XBAR_reserved704[3]; /* 0x0704-0x070F */
3694 
3695  union {
3696  uint32_t R;
3697  struct {
3698  uint32_t RO:1;
3699  uint32_t:21;
3700  uint32_t ARB:2;
3701  uint32_t:2;
3702  uint32_t PCTL:2;
3703  uint32_t:1;
3704  uint32_t PARK:3;
3705  } B;
3706  } SGPCR7; /* General Purpose Control Register for Slave Port 7 */
3707 
3708  uint32_t XBAR_reserved0714[59]; /* 0x0714-0x07FF */
3709 
3710  uint32_t XBAR_reserved0800[3584]; /* 0x0800-0x3FFF */
3711  };
3712 
3713 /****************************************************************************/
3714 /* MODULE : MPU */
3715 /****************************************************************************/
3716 
3717  struct MPU_tag {
3718 
3719  union { /* Module Control/Error Status Register */
3720  uint32_t R;
3721  struct {
3722  uint32_t SPERR:8;
3723  uint32_t:4;
3724  uint32_t HRL:4;
3725  uint32_t NSP:4;
3726  uint32_t NRGD:4;
3727  uint32_t:7;
3728  uint32_t VLD:1;
3729  } B;
3730  } CESR;
3731 
3732  uint32_t MPU_reserved0004[3]; /* 0x0004-0x000F */
3733 
3734  struct {
3735  union { /* MPU Error Address Registers */
3736  uint32_t R;
3737  struct {
3738  uint32_t EADDR:32;
3739  } B;
3740  } EAR;
3741 
3742  union { /* MPU Error Detail Registers */
3743  uint32_t R;
3744  struct {
3745  uint32_t EACD:16;
3746  uint32_t EPID:8;
3747  uint32_t EMN:4;
3748  uint32_t EATTR:3;
3749  uint32_t ERW:1;
3750  } B;
3751  } EDR;
3752  } PORT[3];
3753 
3754  uint32_t MPU_reserved0028[246]; /* 0x0028-0x03FF */
3755 
3756  struct {
3757  union { /* Region Descriptor n Word 0 */
3758  uint32_t R;
3759  struct {
3760  uint32_t SRTADDR:27;
3761  uint32_t:5;
3762  } B;
3763  } WORD0;
3764 
3765  union { /* Region Descriptor n Word 1 */
3766  uint32_t R;
3767  struct {
3768  uint32_t ENDADDR:27;
3769  uint32_t:5;
3770  } B;
3771  } WORD1;
3772 
3773  union { /* Region Descriptor n Word 2 */
3774  uint32_t R;
3775  struct {
3776  uint32_t M7RE:1;
3777  uint32_t M7WE:1;
3778  uint32_t M6RE:1;
3779  uint32_t M6WE:1;
3780  uint32_t M5RE:1;
3781  uint32_t M5WE:1;
3782  uint32_t M4RE:1;
3783  uint32_t M4WE:1;
3784  uint32_t: 18;
3785  uint32_t M0PE:1;
3786  uint32_t M0SM:2;
3787  uint32_t M0UM:3;
3788  } B;
3789  } WORD2;
3790 
3791  union { /* Region Descriptor n Word 3 */
3792  uint32_t R;
3793  struct {
3794  uint32_t PID:8;
3795  uint32_t PIDMASK:8;
3796  uint32_t:15;
3797  uint32_t VLD:1;
3798  } B;
3799  } WORD3;
3800  } RGD[16];
3801 
3802  uint32_t MPU_reserved0500[192]; /* 0x0500-0x07FF */
3803 
3804  union { /* Region Descriptor Alternate Access Control n */
3805  uint32_t R;
3806  struct {
3807  uint32_t:6;
3808  uint32_t M4RE:1;
3809  uint32_t M4WE:1;
3810  uint32_t M3PE:1;
3811  uint32_t M3SM:2;
3812  uint32_t M3UM:3;
3813  uint32_t M2PE:1;
3814  uint32_t M2SM:2;
3815  uint32_t M2UM:3;
3816  uint32_t M1PE:1;
3817  uint32_t M1SM:2;
3818  uint32_t M1UM:3;
3819  uint32_t M0PE:1;
3820  uint32_t M0SM:2;
3821  uint32_t M0UM:3;
3822  } B;
3823  } RGDAAC[16];
3824 
3825  uint32_t MPU_reserved0840[3568]; /* 0x0840-0x3FFF */
3826 
3827  };
3828 
3829 /****************************************************************************/
3830 /* MODULE : SWT */
3831 /****************************************************************************/
3832 
3833  struct SWT_tag {
3834 
3835  union { /* Module Configuration Register */
3836  uint32_t R;
3837  struct {
3838  uint32_t MAP0:1;
3839  uint32_t MAP1:1;
3840  uint32_t:1;
3841  uint32_t:1;
3842  uint32_t MAP4:1;
3843  uint32_t MAP5:1;
3844  uint32_t MAP6:1;
3845  uint32_t MAP7:1;
3846  uint32_t:14;
3847  uint32_t KEY:1;
3848  uint32_t RIA:1;
3849  uint32_t WND:1;
3850  uint32_t ITR:1;
3851  uint32_t HLK:1;
3852  uint32_t SLK:1;
3853  uint32_t CSL:1;
3854  uint32_t STP:1;
3855  uint32_t FRZ:1;
3856  uint32_t WEN:1;
3857  } B;
3858  } MCR;
3859 
3860  union { /* Interrupt register */
3861  uint32_t R;
3862  struct {
3863  uint32_t :31;
3864  uint32_t TIF:1;
3865  } B;
3866  } IR;
3867 
3868  union { /* Timeout register */
3869  uint32_t R;
3870  struct {
3871  uint32_t WTO:32;
3872  } B;
3873  } TO;
3874 
3875  union { /* Window register */
3876  uint32_t R;
3877  struct {
3878  uint32_t WST:32;
3879  } B;
3880  } WN;
3881 
3882  union { /* Service register */
3883  uint32_t R;
3884  struct {
3885  uint32_t :16;
3886  uint32_t WSC:16;
3887  } B;
3888  } SR;
3889 
3890  union { /* Counter output register */
3891  uint32_t R;
3892  struct {
3893  uint32_t CNT:32;
3894  } B;
3895  } CO;
3896 
3897  union { /* Service key register */
3898  uint32_t R;
3899  struct {
3900  uint32_t :16;
3901  uint32_t SK:16;
3902  } B;
3903  } SK;
3904 
3905  uint32_t SWT_reserved001C[4089]; /* 0x001C-0x3FFF */
3906 
3907  };
3908 
3909 /****************************************************************************/
3910 /* MODULE : STM */
3911 /****************************************************************************/
3912 
3913  struct STM_tag {
3914 
3915  union { /* Control Register */
3916  uint32_t R;
3917  struct {
3918  uint32_t :16;
3919  uint32_t CPS:8;
3920  uint32_t :6;
3921  uint32_t FRZ:1;
3922  uint32_t TEN:1;
3923  } B;
3924  } CR;
3925 
3926  union { /* STM Counter */
3927  uint32_t R;
3928  } CNT;
3929 
3930  uint32_t STM_reserved0008[2]; /* 0x0008-0x000F */
3931 
3932  /* channel 0 registers */
3933  union {
3934  uint32_t R;
3935  struct {
3936  uint32_t :31;
3937  uint32_t CEN:1;
3938  } B;
3939  } CCR0; /* Chan 0 Control Register */
3940 
3941  union {
3942  uint32_t R;
3943  struct {
3944  uint32_t :31;
3945  uint32_t CIF:1;
3946  } B;
3947  } CIR0; /* Chan 0 Interrupt Register */
3948 
3949  union {
3950  uint32_t R;
3951  } CMP0; /* Chan 0 Compare Register */
3952 
3953  uint32_t STM_reserved2[1];
3954 
3955 /* channel 1 registers */
3956  union {
3957  uint32_t R;
3958  struct {
3959  uint32_t :31;
3960  uint32_t CEN:1;
3961  } B;
3962  } CCR1; /* Chan 1 Control Register */
3963 
3964  union {
3965  uint32_t R;
3966  struct {
3967  uint32_t :31;
3968  uint32_t CIF:1;
3969  } B;
3970  } CIR1; /* Chan 1 Interrupt Register */
3971 
3972  union {
3973  uint32_t R;
3974  } CMP1; /* Chan 1 Compare Register */
3975 
3976  uint32_t STM_reserved3[1];
3977 
3978 /* channel 2 registers */
3979  union {
3980  uint32_t R;
3981  struct {
3982  uint32_t :31;
3983  uint32_t CEN:1;
3984  } B;
3985  } CCR2; /* Chan 2 Control Register */
3986 
3987  union {
3988  uint32_t R;
3989  struct {
3990  uint32_t :31;
3991  uint32_t CIF:1;
3992  } B;
3993  } CIR2; /* Chan 2 Interrupt Register */
3994 
3995  union {
3996  uint32_t R;
3997  } CMP2; /* Chan 2 Compare Register */
3998 
3999  uint32_t STM_reserved4[1];
4000 
4001 /* channel 3 registers */
4002  union {
4003  uint32_t R;
4004  struct {
4005  uint32_t :31;
4006  uint32_t CEN:1;
4007  } B;
4008  } CCR3; /* Chan 3 Control Register */
4009 
4010  union {
4011  uint32_t R;
4012  struct {
4013  uint32_t :31;
4014  uint32_t CIF:1;
4015  } B;
4016  } CIR3; /* Chan 3 Interrupt Register */
4017 
4018  union {
4019  uint32_t R;
4020  } CMP3; /* Chan 3 Compare Register */
4021 
4022  uint32_t STM_reserved0050[4076]; /* 0x0050-0x3FFF */
4023 
4024  };
4025 
4026 /****************************************************************************/
4027 /* MODULE : ECSM */
4028 /****************************************************************************/
4029 
4030  struct ECSM_tag {
4031 
4032  union { /* Processor core type */
4033  uint16_t R;
4034  } PCT;
4035 
4036  union { /* Platform revision */
4037  uint16_t R;
4038  } REV;
4039 
4040  uint32_t ECSM_reserved0004; /* 0x0004-0x0007 */
4041 
4042  union { /* IPS Module Configuration */
4043  uint32_t R;
4044  } IMC;
4045 
4046  uint8_t ECSM_reserved000C[3]; /* 0x000C-0x000E */
4047 
4048  union { /* Miscellaneous Reset Status Register */
4049  uint8_t R;
4050  struct {
4051  uint8_t POR:1;
4052  uint8_t DIR:1;
4053  uint8_t SWTR:1;
4054  uint8_t:5;
4055  } B;
4056  } MRSR;
4057 
4058  uint8_t ECSM_reserved0010[51]; /* 0x0010-0x0042 */
4059 
4060  union { /* ECC Configuration Register */
4061  uint8_t R;
4062  struct {
4063  uint8_t:2;
4064  uint8_t ER1BR:1;
4065  uint8_t EF1BR:1;
4066  uint8_t:2;
4067  uint8_t ERNCR:1;
4068  uint8_t EFNCR:1;
4069  } B;
4070  } ECR;
4071 
4072  uint8_t ECSM_reserved0044[3]; /* 0x0044-0x0046 */
4073 
4074  union { /* ECC Status Register */
4075  uint8_t R;
4076  struct {
4077  uint8_t:2;
4078  uint8_t R1BC:1;
4079  uint8_t F1BC:1;
4080  uint8_t:2;
4081  uint8_t RNCE:1;
4082  uint8_t FNCE:1;
4083  } B;
4084  } ESR;
4085 
4086  uint16_t ECSM_reserved0048; /* 0x0048-0x0049 */
4087 
4088  union { /* ECC Error Generation Register */
4089  uint16_t R;
4090  struct {
4091  uint16_t:2;
4092  uint16_t FRC1BI:1;
4093  uint16_t FR11BI:1;
4094  uint16_t:2;
4095  uint16_t FRCNCI:1;
4096  uint16_t FR1NCI:1;
4097  uint16_t:1;
4098  uint16_t ERRBIT:7;
4099  } B;
4100  } EEGR;
4101 
4102  uint32_t ECSM_reserved004C; /* 0x004C-0x004F */
4103 
4104  union { /* Flash ECC Address Register */
4105  uint32_t R;
4106  struct {
4107  uint32_t FEAR:32;
4108  } B;
4109  } FEAR;
4110 
4111  uint16_t ECSM_reserved0054; /* 0x0054-0x0055 */
4112 
4113  union { /* Flash ECC Master Number Register */
4114  uint8_t R;
4115  struct {
4116  uint8_t:4;
4117  uint8_t FEMR:4;
4118  } B;
4119  } FEMR;
4120 
4121  union { /* Flash ECC Attributes Register */
4122  uint8_t R;
4123  struct {
4124  uint8_t WRITE:1;
4125  uint8_t SIZE:3;
4126  uint8_t PROT0:1;
4127  uint8_t PROT1:1;
4128  uint8_t PROT2:1;
4129  uint8_t PROT3:1;
4130  } B;
4131  } FEAT;
4132 
4133  union { /* Flash ECC Data Register High */
4134  uint32_t R;
4135  struct {
4136  uint32_t FEDH:32;
4137  } B;
4138  } FEDRH;
4139 
4140  union { /* Flash ECC Data Register Low */
4141  uint32_t R;
4142  struct {
4143  uint32_t FEDL:32;
4144  } B;
4145  } FEDRL;
4146 
4147  union { /* RAM ECC Address Register */
4148  uint32_t R;
4149  struct {
4150  uint32_t REAR:32;
4151  } B;
4152  } REAR;
4153 
4154  uint16_t ECSM_reserved0064; /* 0x0064-0x0065 */
4155 
4156  union { /* RAM ECC Master Number Register */
4157  uint8_t R;
4158  struct {
4159  uint8_t:4;
4160  uint8_t REMR:4;
4161  } B;
4162  } REMR;
4163 
4164  union { /* RAM ECC Attributes Register */
4165  uint8_t R;
4166  struct {
4167  uint8_t WRITE:1;
4168  uint8_t SIZE:3;
4169  uint8_t PROT0:1;
4170  uint8_t PROT1:1;
4171  uint8_t PROT2:1;
4172  uint8_t PROT3:1;
4173  } B;
4174  } REAT;
4175 
4176  union { /* RAM ECC Data Register */
4177  uint32_t R;
4178  struct {
4179  uint32_t REDH:32;
4180  } B;
4181  } REDRH;
4182 
4183  union { /* RAM ECC Data Register */
4184  uint32_t R;
4185  struct {
4186  uint32_t REDL:32;
4187  } B;
4188  } REDRL;
4189 
4190  uint32_t ECSM_reserved0070[4068]; /* 0x0070-0x3FFF */
4191 
4192  };
4193 
4194 /****************************************************************************/
4195 /* MODULE : INTC */
4196 /****************************************************************************/
4197 
4198  struct INTC_tag {
4199 
4200  union { /* Module Configuration Register */
4201  uint32_t R;
4202  struct {
4203  uint32_t:26;
4204  uint32_t VTES:1;
4205  uint32_t:4;
4206  uint32_t HVEN:1;
4207  } B;
4208  } MCR;
4209 
4210  uint32_t INTC_reserved0004; /* 0x0004-0x0007 */
4211 
4212  union { /* Current Priority Register */
4213  uint32_t R;
4214  struct {
4215  uint32_t:28;
4216  uint32_t PRI:4;
4217  } B;
4218  } CPR;
4219 
4220  uint32_t INTC_reserved000C; /* 0x000C-0x000F */
4221 
4222  union { /* Interrupt Acknowledge Register */
4223  uint32_t R;
4224  struct {
4225  uint32_t VTBA:21;
4226  uint32_t INTVEC:9;
4227  uint32_t:2;
4228  } B;
4229  } IACKR;
4230 
4231  uint32_t INTC_reserved0014; /* 0x0014-0x0017 */
4232 
4233  union { /* End of Interrupt Register */
4234  uint32_t R;
4235  struct {
4236  uint32_t EOIR:32;
4237  } B;
4238  } EOIR;
4239 
4240  uint32_t INTC_reserved001C; /* 0x001C-0x001F */
4241 
4242  union { /* Software Set/Clear Interruput Register */
4243  uint8_t R;
4244  struct {
4245  uint8_t:6;
4246  uint8_t SET:1;
4247  uint8_t CLR:1;
4248  } B;
4249  } SSCIR[8];
4250 
4251  uint32_t INTC_reserved0028[6]; /* 0x0028-0x003F */
4252 
4253  union { /* Software Set/Clear Interrupt Register */
4254  uint8_t R;
4255  struct {
4256  uint8_t:4;
4257  uint8_t PRI:4;
4258  } B;
4259  } PSR[480];
4260 
4261  uint16_t INTC_reserved0220[7920]; /* 0x0220-0x3FFF */
4262 
4263  };
4264 
4265 /****************************************************************************/
4266 /* MODULE : EQADC */
4267 /****************************************************************************/
4268 
4269  struct EQADC_tag {
4270 
4271  union EQADC_MCR_tag { /* Module Configuration Register */
4272  uint32_t R;
4273  struct {
4274  uint32_t:24;
4275  uint32_t ICEA0:1;
4276  uint32_t ICEA1:1;
4277  uint32_t:1;
4278  uint32_t ESSIE:2;
4279  uint32_t:1;
4280  uint32_t DBG:2;
4281  } B;
4282  } MCR;
4283 
4284  uint32_t eQADC_reserved0004; /* 0x0004-0x0007 */
4285 
4286  union EQADC_NMSFR_tag { /* Null Message Send Format Register */
4287  uint32_t R;
4288  struct {
4289  uint32_t:6;
4290  uint32_t NMF:26;
4291  } B;
4292  } NMSFR;
4293 
4294  union EQADC_ETDFR_tag { /* External Trigger Digital Filter Register */
4295  uint32_t R;
4296  struct {
4297  uint32_t:28;
4298  uint32_t DFL:4;
4299  } B;
4300  } ETDFR;
4301 
4302  union EQADC_CFPR_tag { /* CFIFO Push Registers */
4303  uint32_t R;
4304  struct {
4305  uint32_t CFPUSH:32;
4306  } B;
4307  } CFPR[6];
4308 
4309  uint32_t eQADC_reserved0028[2]; /* 0x0028-0x002F */
4310 
4311  union EQADC_RFPR_tag { /* Result FIFO Pop Registers */
4312  uint32_t R;
4313  struct {
4314  uint32_t:16;
4315  uint32_t RFPOP:16;
4316  } B;
4317  } RFPR[6];
4318 
4319  uint32_t eQADC_reserved0048[2]; /* 0x0048-0x004F */
4320 
4321  union EQADC_CFCR_tag { /* CFIFO Control Registers */
4322  uint16_t R;
4323  struct {
4324  uint16_t:3;
4325  uint16_t CFEEE0:1;
4326  uint16_t STRME0:1;
4327  uint16_t SSE:1;
4328  uint16_t CFINV:1;
4329  uint16_t:1;
4330  uint16_t MODE:4;
4331  uint16_t AMODE0:4;
4332  } B;
4333  } CFCR[6];
4334 
4335  uint32_t eQADC_reserved005C; /* 0x005C-0x005F */
4336 
4337  union EQADC_IDCR_tag { /* Interrupt and DMA Control Registers */
4338  uint16_t R;
4339  struct {
4340  uint16_t NCIE:1;
4341  uint16_t TORIE:1;
4342  uint16_t PIE:1;
4343  uint16_t EOQIE:1;
4344  uint16_t CFUIE:1;
4345  uint16_t:1;
4346  uint16_t CFFE:1;
4347  uint16_t CFFS:1;
4348  uint16_t:4;
4349  uint16_t RFOIE:1;
4350  uint16_t:1;
4351  uint16_t RFDE:1;
4352  uint16_t RFDS:1;
4353  } B;
4354  } IDCR[6];
4355 
4356  uint32_t eQADC_reserved006C; /* 0x006C-0x006F */
4357 
4358  union { /* FIFO and Interrupt Status Registers */
4359  uint32_t R;
4360  struct {
4361  uint32_t NCF:1;
4362  uint32_t TORF:1;
4363  uint32_t PF:1;
4364  uint32_t EOQF:1;
4365  uint32_t CFUF:1;
4366  uint32_t SSS:1;
4367  uint32_t CFFF:1;
4368  uint32_t:5;
4369  uint32_t RFOF:1;
4370  uint32_t:1;
4371  uint32_t RFDF:1;
4372  uint32_t:1;
4373  uint32_t CFCTR:4;
4374  uint32_t TNXTPTR:4;
4375  uint32_t RFCTR:4;
4376  uint32_t POPNXTPTR:4;
4377  } B;
4378  } FISR[6];
4379 
4380  uint32_t eQADC_reserved0088[2]; /* 0x0088-0x008F */
4381 
4382  union { /* CFIFO Transfer Counter Registers */
4383  uint16_t R;
4384  struct {
4385  uint16_t:5;
4386  uint16_t TCCF:11; /* Legacy naming - refer to TC_CF in Reference Manual */
4387  } B;
4388  } CFTCR[6];
4389 
4390  uint32_t eQADC_reserved009C[1]; /* 0x009F */
4391 
4392  union { /* CFIFO Status Register 0 */
4393  uint32_t R;
4394  struct {
4395  uint32_t CFS0:2; /* Legacy naming - refer to CFS0_TCB0 in Reference Manual */
4396  uint32_t CFS1:2; /* Legacy naming - refer to CFS1_TCB0 in Reference Manual */
4397  uint32_t CFS2:2; /* Legacy naming - refer to CFS2_TCB0 in Reference Manual */
4398  uint32_t CFS3:2; /* Legacy naming - refer to CFS3_TCB0 in Reference Manual */
4399  uint32_t CFS4:2; /* Legacy naming - refer to CFS4_TCB0 in Reference Manual */
4400  uint32_t CFS5:2; /* Legacy naming - refer to CFS5_TCB0 in Reference Manual */
4401  uint32_t:5;
4402  uint32_t LCFTCB0:4;
4403  uint32_t TC_LCFTCB0:11;
4404  } B;
4405  } CFSSR0;
4406 
4407  union { /* CFIFO Status Register 1 */
4408  uint32_t R;
4409  struct {
4410  uint32_t CFS0:2; /* Legacy naming - refer to CFS0_TCB1 in Reference Manual */
4411  uint32_t CFS1:2; /* Legacy naming - refer to CFS1_TCB1 in Reference Manual */
4412  uint32_t CFS2:2; /* Legacy naming - refer to CFS2_TCB1 in Reference Manual */
4413  uint32_t CFS3:2; /* Legacy naming - refer to CFS3_TCB1 in Reference Manual */
4414  uint32_t CFS4:2; /* Legacy naming - refer to CFS4_TCB1 in Reference Manual */
4415  uint32_t CFS5:2; /* Legacy naming - refer to CFS5_TCB1 in Reference Manual */
4416  uint32_t:5;
4417  uint32_t LCFTCB1:4;
4418  uint32_t TC_LCFTCB1:11;
4419  } B;
4420  } CFSSR1;
4421 
4422  union { /* CFIFO Status Register 2 */
4423  uint32_t R;
4424  struct {
4425  uint32_t CFS0:2; /* Legacy naming - refer to CFS0_TSSI in Reference Manual */
4426  uint32_t CFS1:2; /* Legacy naming - refer to CFS1_TSSI in Reference Manual */
4427  uint32_t CFS2:2; /* Legacy naming - refer to CFS2_TSSI in Reference Manual */
4428  uint32_t CFS3:2; /* Legacy naming - refer to CFS3_TSSI in Reference Manual */
4429  uint32_t CFS4:2; /* Legacy naming - refer to CFS4_TSSI in Reference Manual */
4430  uint32_t CFS5:2; /* Legacy naming - refer to CFS5_TSSI in Reference Manual */
4431  uint32_t:4;
4432  uint32_t ECBNI:1;
4433  uint32_t LCFTSSI:4;
4434  uint32_t TC_LCFTSSI:11;
4435  } B;
4436  } CFSSR2;
4437 
4438  union { /* CFIFO Status Register */
4439  uint32_t R;
4440  struct {
4441  uint32_t CFS0:2;
4442  uint32_t CFS1:2;
4443  uint32_t CFS2:2;
4444  uint32_t CFS3:2;
4445  uint32_t CFS4:2;
4446  uint32_t CFS5:2;
4447  uint32_t:20;
4448  } B;
4449  } CFSR;
4450 
4451  uint32_t eQADC_reserved00B0; /* 0x00B0-0x00B3 */
4452 
4453  union EQADC_SSICR_tag { /* SSI Control Register */
4454  uint32_t R;
4455  struct {
4456  uint32_t:21;
4457  uint32_t MDT:3;
4458  uint32_t:4;
4459  uint32_t BR:4;
4460  } B;
4461  } SSICR;
4462 
4463  union { /* SSI Recieve Data Register */
4464  uint32_t R;
4465  struct {
4466  uint32_t RDV:1;
4467  uint32_t:5;
4468  uint32_t RDATA:26;
4469  } B;
4470  } SSIRDR;
4471 
4472  uint32_t eQADC_reserved00BC[17]; /* 0x00BC-0x00FF */
4473 
4474  struct {
4475  union {
4476  uint32_t R;
4477  struct {
4478  uint32_t CFIFO_DATA:32;
4479  } B;
4480  } R[4];
4481 
4482  uint32_t eQADC_cf_reserved010[12]; /* CFIFO offset 0x010-0x03F */
4483 
4484  } CF[6];
4485 
4486  uint32_t eQADC_reserved0280[32]; /* 0x0280-0x02FF */
4487 
4488  struct {
4489  union {
4490  uint32_t R;
4491  struct {
4492  uint32_t RFIFO_DATA:32;
4493  } B;
4494  } R[4];
4495 
4496  uint32_t eQADC_rf_reserved010[12]; /* RFIFO offset 0x010-0x03F */
4497 
4498  } RF[6];
4499 
4500  uint32_t eQADC_reserved0480[3808]; /* 0x0480-0x3FFF */
4501  };
4502 
4503 /****************************************************************************/
4504 /* MODULE : Decimation Filter */
4505 /****************************************************************************/
4506 
4507  struct DECFIL_tag {
4508 
4509  union { /* Module Configuration Register */
4510  uint32_t R;
4511  struct {
4512  uint32_t MDIS:1;
4513  uint32_t FREN:1;
4514  uint32_t :1;
4515  uint32_t FRZ:1;
4516  uint32_t SRES:1;
4517  uint32_t CASCD:2;
4518  uint32_t IDEN:1;
4519  uint32_t ODEN:1;
4520  uint32_t ERREN:1;
4521  uint32_t :1;
4522  uint32_t FTYPE:2;
4523  uint32_t :1;
4524  uint32_t SCAL:2;
4525  uint32_t :1;
4526  uint32_t SAT:1;
4527  uint32_t ISEL:1;
4528  uint32_t :1;
4529  uint32_t DEC_RATE:4;
4530  uint32_t :1;
4531  uint32_t DSEL:1;
4532  uint32_t IBIE:1;
4533  uint32_t OBIE:1;
4534  uint32_t EDME:1;
4535  uint32_t TORE:1;
4536  uint32_t TRFE:1;
4537  uint32_t :1;
4538  } B;
4539  } MCR;
4540 
4541  union { /* Module Status Register */
4542  uint32_t R;
4543  struct {
4544  uint32_t BSY:1;
4545  uint32_t:1;
4546  uint32_t DEC_COUNTER:4;
4547  uint32_t IDFC:1;
4548  uint32_t ODFC:1;
4549  uint32_t:1;
4550  uint32_t IBIC:1;
4551  uint32_t OBIC:1;
4552  uint32_t:1;
4553  uint32_t DIVRC:1;
4554  uint32_t OVFC:1;
4555  uint32_t OVRC:1;
4556  uint32_t IVRC:1;
4557  uint32_t:6;
4558  uint32_t IDF:1;
4559  uint32_t ODF:1;
4560  uint32_t:1;
4561  uint32_t IBIF:1;
4562  uint32_t OBIF:1;
4563  uint32_t:1;
4564  uint32_t DIVR:1;
4565  uint32_t OVF:1;
4566  uint32_t OVR:1;
4567  uint32_t IVR:1;
4568  } B;
4569  } SR;
4570 
4571  union { /* Module Extended Config Register */
4572  uint32_t R;
4573  struct {
4574  uint32_t SDMAE:1;
4575  uint32_t SSIG:1;
4576  uint32_t SSAT:1;
4577  uint32_t SCSAT:1;
4578  uint32_t:10;
4579  uint32_t SRQ:1;
4580  uint32_t SZR0:1;
4581  uint32_t:1;
4582  uint32_t SISEL:1;
4583  uint32_t SZROSEL:2;
4584  uint32_t:2;
4585  uint32_t SHLTSEL:2;
4586  uint32_t:1;
4587  uint32_t SRQSEL:3;
4588  uint32_t:2;
4589  uint32_t SENSEL:2;
4590  } B;
4591  } MXCR;
4592 
4593  union { /* Module Extended Status Register */
4594  uint32_t R;
4595  struct {
4596  uint32_t:7;
4597  uint32_t SDFC:1;
4598  uint32_t:2;
4599  uint32_t SSEC:1;
4600  uint32_t SCEC:1;
4601  uint32_t:1;
4602  uint32_t SSOVFC:1;
4603  uint32_t SCOVFC:1;
4604  uint32_t SVRC:1;
4605  uint32_t:7;
4606  uint32_t SDF:1;
4607  uint32_t:2;
4608  uint32_t SSE:1;
4609  uint32_t SCE:1;
4610  uint32_t:1;
4611  uint32_t SSOVF:1;
4612  uint32_t SCOVF:1;
4613  uint32_t SVR:1;
4614  } B;
4615  } MXSR;
4616 
4617  union { /* Interface Input Buffer Register */
4618  uint32_t R;
4619  struct {
4620  uint32_t:14;
4621  uint32_t PREFILL:1;
4622  uint32_t FLUSH:1;
4623  uint32_t INPBUF:16;
4624  } B;
4625  } IB;
4626 
4627  union { /* Interface Output Buffer Register */
4628  uint32_t R;
4629  struct {
4630  uint32_t:9;
4631  uint32_t TSI:1;
4632  uint32_t:2;
4633  uint32_t OUTTAG:4;
4634  uint32_t OUTBUF:16;
4635  } B;
4636  } OB;
4637 
4638  uint32_t DFILT_reserved0018[2]; /* 0x0018-0x001F */
4639 
4640  union { /* Coefficient n Register */
4641  int32_t R;
4642  struct {
4643  int32_t:8;
4644  int32_t COEF:24;
4645  } B;
4646  } COEF[9];
4647 
4648  uint32_t DFILT_reserved0044[13]; /* 0x0044-0x0077 */
4649 
4650  union { /* TAP n Register */
4651  int32_t R;
4652  struct {
4653  int32_t:8;
4654  int32_t TAP:24;
4655  } B;
4656  } TAP[8];
4657 
4658  uint32_t DFILT_reserved0098[14]; /* 0x0098-0x00CF */
4659 
4660  union { /* EDID Register */
4661  uint32_t R;
4662  struct {
4663  uint32_t:16;
4664  uint32_t SAMP_DATA:16;
4665  } B;
4666  } EDID;
4667 
4668  uint32_t DFILT_reserved00D4[459]; /* 0x00D4-0x07FF */
4669 
4670  };
4671 
4672 /****************************************************************************/
4673 /* MODULE : DSPI */
4674 /****************************************************************************/
4675 
4676  struct DSPI_tag {
4677 
4678  union DSPI_MCR_tag { /* Module Configuration Register */
4679  uint32_t R;
4680  struct {
4681  uint32_t MSTR:1;
4682  uint32_t CONT_SCKE:1;
4683  uint32_t DCONF:2;
4684  uint32_t FRZ:1;
4685  uint32_t MTFE:1;
4686  uint32_t PCSSE:1;
4687  uint32_t ROOE:1;
4688  uint32_t PCSIS7:1;
4689  uint32_t PCSIS6:1;
4690  uint32_t PCSIS5:1;
4691  uint32_t PCSIS4:1;
4692  uint32_t PCSIS3:1;
4693  uint32_t PCSIS2:1;
4694  uint32_t PCSIS1:1;
4695  uint32_t PCSIS0:1;
4696  uint32_t DOZE:1;
4697  uint32_t MDIS:1;
4698  uint32_t DIS_TXF:1;
4699  uint32_t DIS_RXF:1;
4700  uint32_t CLR_TXF:1;
4701  uint32_t CLR_RXF:1;
4702  uint32_t SMPL_PT:2;
4703  uint32_t:7;
4704  uint32_t HALT:1;
4705  } B;
4706  } MCR;
4707 
4708  uint32_t DSPI_reserved0004; /* 0x0004-0x0007 */
4709 
4710  union { /* Transfer Count Register */
4711  uint32_t R;
4712  struct {
4713  uint32_t TCNT:16;
4714  uint32_t:16;
4715  } B;
4716  } TCR;
4717 
4718  union DSPI_CTAR_tag {/* Clock and Transfer Attributes Registers */
4719  uint32_t R;
4720  struct {
4721  uint32_t DBR:1;
4722  uint32_t FMSZ:4;
4723  uint32_t CPOL:1;
4724  uint32_t CPHA:1;
4725  uint32_t LSBFE:1;
4726  uint32_t PCSSCK:2;
4727  uint32_t PASC:2;
4728  uint32_t PDT:2;
4729  uint32_t PBR:2;
4730  uint32_t CSSCK:4;
4731  uint32_t ASC:4;
4732  uint32_t DT:4;
4733  uint32_t BR:4;
4734  } B;
4735  } CTAR[8];
4736 
4737  union DSPI_SR_tag { /* Status Register */
4738  uint32_t R;
4739  struct {
4740  uint32_t TCF:1;
4741  uint32_t TXRXS:1;
4742  uint32_t:1;
4743  uint32_t EOQF:1;
4744  uint32_t TFUF:1;
4745  uint32_t:1;
4746  uint32_t TFFF:1;
4747  uint32_t:5;
4748  uint32_t RFOF:1;
4749  uint32_t:1;
4750  uint32_t RFDF:1;
4751  uint32_t:1;
4752  uint32_t TXCTR:4;
4753  uint32_t TXNXTPTR:4;
4754  uint32_t RXCTR:4;
4755  uint32_t POPNXTPTR:4;
4756  } B;
4757  } SR;
4758 
4759  union DSPI_RSER_tag { /* DMA/Interrupt Request Select and Enable Register */
4760  uint32_t R;
4761  struct {
4762  uint32_t TCFRE:1;
4763  uint32_t:2;
4764  uint32_t EOQFRE:1;
4765  uint32_t TFUFRE:1;
4766  uint32_t:1;
4767  uint32_t TFFFRE:1;
4768  uint32_t TFFFDIRS:1;
4769  uint32_t:4;
4770  uint32_t RFOFRE:1;
4771  uint32_t:1;
4772  uint32_t RFDFRE:1;
4773  uint32_t RFDFDIRS:1;
4774  uint32_t:16;
4775  } B;
4776  } RSER;
4777 
4778  union DSPI_PUSHR_tag { /* PUSH TX FIFO Register */
4779  uint32_t R;
4780  struct {
4781  uint32_t CONT:1;
4782  uint32_t CTAS:3;
4783  uint32_t EOQ:1;
4784  uint32_t CTCNT:1;
4785  uint32_t:2;
4786  uint32_t PCS7:1;
4787  uint32_t PCS6:1;
4788  uint32_t PCS5:1;
4789  uint32_t PCS4:1;
4790  uint32_t PCS3:1;
4791  uint32_t PCS2:1;
4792  uint32_t PCS1:1;
4793  uint32_t PCS0:1;
4794  uint32_t TXDATA:16;
4795  } B;
4796  } PUSHR;
4797 
4798  union DSPI_POPR_tag { /* POP RX FIFO Register */
4799  uint32_t R;
4800  struct {
4801  uint32_t:16;
4802  uint32_t RXDATA:16;
4803  } B;
4804  } POPR;
4805 
4806  union { /* Transmit FIFO Registers */
4807  uint32_t R;
4808  struct {
4809  uint32_t TXCMD:16;
4810  uint32_t TXDATA:16;
4811  } B;
4812  } TXFR[4];
4813 
4814  uint32_t DSPI_reserved004C[12]; /* 0x004C-0x007B */
4815 
4816  union { /* Transmit FIFO Registers */
4817  uint32_t R;
4818  struct {
4819  uint32_t:16;
4820  uint32_t RXDATA:16;
4821  } B;
4822  } RXFR[4];
4823 
4824  uint32_t DSPI_reserved008C[12]; /* 0x008C-0x00BB */
4825 
4826  union { /* DSI Configuration Register */
4827  uint32_t R;
4828  struct {
4829  uint32_t MTOE:1;
4830  uint32_t:1;
4831  uint32_t MTOCNT:6;
4832  uint32_t:3;
4833  uint32_t TSBC:1;
4834  uint32_t TXSS:1;
4835  uint32_t TPOL:1;
4836  uint32_t TRRE:1;
4837  uint32_t CID:1;
4838  uint32_t DCONT:1;
4839  uint32_t DSICTAS:3;
4840  uint32_t:4;
4841  uint32_t DPCS7:1;
4842  uint32_t DPCS6:1;
4843  uint32_t DPCS5:1;
4844  uint32_t DPCS4:1;
4845  uint32_t DPCS3:1;
4846  uint32_t DPCS2:1;
4847  uint32_t DPCS1:1;
4848  uint32_t DPCS0:1;
4849  } B;
4850  } DSICR;
4851 
4852  union { /* DSI Serialization Data Register */
4853  uint32_t R;
4854  struct {
4855  uint32_t SER_DATA:32;
4856  } B;
4857  } SDR;
4858 
4859  union { /* DSI Alternate Serialization Data Register */
4860  uint32_t R;
4861  struct {
4862  uint32_t ASER_DATA:32;
4863  } B;
4864  } ASDR;
4865 
4866  union { /* DSI Transmit Comparison Register */
4867  uint32_t R;
4868  struct {
4869  uint32_t COMP_DATA:32;
4870  } B;
4871  } COMPR;
4872 
4873  union { /* DSI deserialization Data Register */
4874  uint32_t R;
4875  struct {
4876  uint32_t DESER_DATA:32;
4877  } B;
4878  } DDR;
4879 
4880  union {
4881  uint32_t R;
4882  struct {
4883  uint32_t:3;
4884  uint32_t TSBCNT:5;
4885  uint32_t:16;
4886  uint32_t DPCS1_7:1;
4887  uint32_t DPCS1_6:1;
4888  uint32_t DPCS1_5:1;
4889  uint32_t DPCS1_4:1;
4890  uint32_t DPCS1_3:1;
4891  uint32_t DPCS1_2:1;
4892  uint32_t DPCS1_1:1;
4893  uint32_t DPCS1_0:1;
4894  } B;
4895  } DSICR1;
4896  uint32_t DSPI_reserved00D4[4043]; /* 0x00D4-0x3FFF */
4897 
4898  };
4899 
4900 /****************************************************************************/
4901 /* MODULE : eSCI */
4902 /****************************************************************************/
4903 
4904  struct ESCI_tag {
4905  union ESCI_CR1_tag { /* Control Register 1 */
4906  uint32_t R;
4907  struct {
4908  uint32_t:3;
4909  uint32_t SBR:13;
4910  uint32_t LOOPS:1;
4911  uint32_t:1;
4912  uint32_t RSRC:1;
4913  uint32_t M:1;
4914  uint32_t WAKE:1;
4915  uint32_t ILT:1;
4916  uint32_t PE:1;
4917  uint32_t PT:1;
4918  uint32_t TIE:1;
4919  uint32_t TCIE:1;
4920  uint32_t RIE:1;
4921  uint32_t ILIE:1;
4922  uint32_t TE:1;
4923  uint32_t RE:1;
4924  uint32_t RWU:1;
4925  uint32_t SBK:1;
4926  } B;
4927  } CR1;
4928 
4929  union ESCI_CR2_tag { /* Control Register 2 */
4930  uint16_t R;
4931  struct {
4932  uint16_t MDIS:1;
4933  uint16_t FBR:1;
4934  uint16_t BSTP:1;
4935  uint16_t IEBERR:1;
4936  uint16_t RXDMA:1;
4937  uint16_t TXDMA:1;
4938  uint16_t BRK13:1;
4939  uint16_t TXDIR:1;
4940  uint16_t BESM13:1;
4941  uint16_t SBSTP:1;
4942  uint16_t RXPOL:1;
4943  uint16_t PMSK:1;
4944  uint16_t ORIE:1;
4945  uint16_t NFIE:1;
4946  uint16_t FEIE:1;
4947  uint16_t PFIE:1;
4948  } B;
4949  } CR2;
4950 
4951  union ESCI_DR_tag { /* Data Register */
4952  uint16_t R;
4953 
4954  struct {
4955  uint16_t RN:1;
4956  uint16_t TN:1;
4957  uint16_t ERR:1;
4958  uint16_t:1;
4959  uint16_t RD_11:4;
4960  uint16_t D:8;
4961  } B;
4962  } DR; /* Legacy naming - refer to SDR in Reference Manual */
4963 
4964  union ESCI_SR_tag { /* Status Register */
4965  uint32_t R;
4966  struct {
4967  uint32_t TDRE:1;
4968  uint32_t TC:1;
4969  uint32_t RDRF:1;
4970  uint32_t IDLE:1;
4971  uint32_t OR:1;
4972  uint32_t NF:1;
4973  uint32_t FE:1;
4974  uint32_t PF:1;
4975  uint32_t:3;
4976  uint32_t BERR:1;
4977  uint32_t:2;
4978  uint32_t TACT:1;
4979  uint32_t RAF:1;
4980  uint32_t RXRDY:1;
4981  uint32_t TXRDY:1;
4982  uint32_t LWAKE:1;
4983  uint32_t STO:1;
4984  uint32_t PBERR:1;
4985  uint32_t CERR:1;
4986  uint32_t CKERR:1;
4987  uint32_t FRC:1;
4988  uint32_t:6;
4989  uint32_t UREQ:1;
4990  uint32_t OVFL:1;
4991  } B;
4992  } SR;
4993 
4994  union { /* LIN Control Register */
4995  uint32_t R;
4996  struct {
4997  uint32_t LRES:1;
4998  uint32_t WU:1;
4999  uint32_t WUD0:1;
5000  uint32_t WUD1:1;
5001  uint32_t :2;
5002  uint32_t PRTY:1;
5003  uint32_t LIN:1;
5004  uint32_t RXIE:1;
5005  uint32_t TXIE:1;
5006  uint32_t WUIE:1;
5007  uint32_t STIE:1;
5008  uint32_t PBIE:1;
5009  uint32_t CIE:1;
5010  uint32_t CKIE:1;
5011  uint32_t FCIE:1;
5012  uint32_t:6;
5013  uint32_t UQIE:1;
5014  uint32_t OFIE:1;
5015  uint32_t:8;
5016  } B;
5017  } LCR;
5018 
5019  union { /* LIN Transmit Register */
5020  uint8_t R;
5021  } LTR;
5022 
5023  uint8_t eSCI_reserved0011[3]; /* 0x0011-0x0013 */
5024 
5025  union { /* LIN Recieve Register */
5026  uint8_t R;
5027  struct {
5028  uint8_t D:8;
5029  } B;
5030  } LRR;
5031 
5032  uint8_t eSCI_reserved0015[3]; /* 0x0015-0x0017 */
5033 
5034  union { /* LIN CRC Polynom Register */
5035  uint16_t R;
5036  struct {
5037  uint16_t P:16;
5038  } B;
5039  } LPR;
5040 
5041  union { /* Control Register 3 */
5042  uint16_t R;
5043  struct {
5044  uint16_t:3;
5045  uint16_t SYNM:1;
5046  uint16_t EROE:1;
5047  uint16_t ERFE:1;
5048  uint16_t ERPE:1;
5049  uint16_t M2:1;
5050  uint16_t:8;
5051  } B;
5052  } CR3;
5053 
5054  uint32_t eSCI_reserved001C; /* 0x001C-0x001F */
5055 
5056  uint32_t eSCI_reserved0020[4088]; /* 0x0020-0x3FFF */
5057 
5058  };
5059 
5060 /****************************************************************************/
5061 /* MODULE : FlexCAN */
5062 /****************************************************************************/
5063 
5064  struct FLEXCAN2_tag {
5065  union { /* Module Configuration Register */
5066  uint32_t R;
5067  struct {
5068  uint32_t MDIS:1;
5069  uint32_t FRZ:1;
5070  uint32_t FEN:1;
5071  uint32_t HALT:1;
5072  uint32_t NOTRDY:1;
5073  uint32_t WAK_MSK:1;
5074  uint32_t SOFTRST:1;
5075  uint32_t FRZACK:1;
5076  uint32_t SUPV:1;
5077  uint32_t SLF_WAK:1;
5078  uint32_t WRNEN:1;
5079  uint32_t MDISACK:1;
5080  uint32_t WAK_SRC:1;
5081  uint32_t DOZE:1;
5082  uint32_t SRXDIS:1;
5083  uint32_t BCC:1;
5084  uint32_t:2;
5085  uint32_t LPRIO_EN:1;
5086  uint32_t AEN:1;
5087  uint32_t:2;
5088  uint32_t IDAM:2;
5089  uint32_t:2;
5090  uint32_t MAXMB:6;
5091  } B;
5092  } MCR;
5093 
5094  union { /* Control Register */
5095  uint32_t R;
5096  struct {
5097  uint32_t PRESDIV:8;
5098  uint32_t RJW:2;
5099  uint32_t PSEG1:3;
5100  uint32_t PSEG2:3;
5101  uint32_t BOFFMSK:1;
5102  uint32_t ERRMSK:1;
5103  uint32_t CLKSRC:1;
5104  uint32_t LPB:1;
5105  uint32_t TWRNMSK:1;
5106  uint32_t RWRNMSK:1;
5107  uint32_t:2;
5108  uint32_t SMP:1;
5109  uint32_t BOFFREC:1;
5110  uint32_t TSYN:1;
5111  uint32_t LBUF:1;
5112  uint32_t LOM:1;
5113  uint32_t PROPSEG:3;
5114  } B;
5115  } CR; /* Legacy naming - refer to CTRL in Reference Manual */
5116 
5117  union { /* Free Running Timer */
5118  uint32_t R;
5119  } TIMER;
5120 
5121  int32_t FLEXCAN_reserved000C; /* 0x000C-0x000F */
5122 
5123  union { /* RX Global Mask */
5124  uint32_t R;
5125  struct {
5126  uint32_t MI31:1;
5127  uint32_t MI30:1;
5128  uint32_t MI29:1;
5129  uint32_t MI28:1;
5130  uint32_t MI27:1;
5131  uint32_t MI26:1;
5132  uint32_t MI25:1;
5133  uint32_t MI24:1;
5134  uint32_t MI23:1;
5135  uint32_t MI22:1;
5136  uint32_t MI21:1;
5137  uint32_t MI20:1;
5138  uint32_t MI19:1;
5139  uint32_t MI18:1;
5140  uint32_t MI17:1;
5141  uint32_t MI16:1;
5142  uint32_t MI15:1;
5143  uint32_t MI14:1;
5144  uint32_t MI13:1;
5145  uint32_t MI12:1;
5146  uint32_t MI11:1;
5147  uint32_t MI10:1;
5148  uint32_t MI9:1;
5149  uint32_t MI8:1;
5150  uint32_t MI7:1;
5151  uint32_t MI6:1;
5152  uint32_t MI5:1;
5153  uint32_t MI4:1;
5154  uint32_t MI3:1;
5155  uint32_t MI2:1;
5156  uint32_t MI1:1;
5157  uint32_t MI0:1;
5158  } B;
5159  } RXGMASK;
5160 
5161  union { /* RX 14 Mask */
5162  uint32_t R;
5163  struct {
5164  uint32_t MI31:1;
5165  uint32_t MI30:1;
5166  uint32_t MI29:1;
5167  uint32_t MI28:1;
5168  uint32_t MI27:1;
5169  uint32_t MI26:1;
5170  uint32_t MI25:1;
5171  uint32_t MI24:1;
5172  uint32_t MI23:1;
5173  uint32_t MI22:1;
5174  uint32_t MI21:1;
5175  uint32_t MI20:1;
5176  uint32_t MI19:1;
5177  uint32_t MI18:1;
5178  uint32_t MI17:1;
5179  uint32_t MI16:1;
5180  uint32_t MI15:1;
5181  uint32_t MI14:1;
5182  uint32_t MI13:1;
5183  uint32_t MI12:1;
5184  uint32_t MI11:1;
5185  uint32_t MI10:1;
5186  uint32_t MI9:1;
5187  uint32_t MI8:1;
5188  uint32_t MI7:1;
5189  uint32_t MI6:1;
5190  uint32_t MI5:1;
5191  uint32_t MI4:1;
5192  uint32_t MI3:1;
5193  uint32_t MI2:1;
5194  uint32_t MI1:1;
5195  uint32_t MI0:1;
5196  } B;
5197  } RX14MASK;
5198 
5199  union { /* RX 15 Mask */
5200  uint32_t R;
5201  struct {
5202  uint32_t MI31:1;
5203  uint32_t MI30:1;
5204  uint32_t MI29:1;
5205  uint32_t MI28:1;
5206  uint32_t MI27:1;
5207  uint32_t MI26:1;
5208  uint32_t MI25:1;
5209  uint32_t MI24:1;
5210  uint32_t MI23:1;
5211  uint32_t MI22:1;
5212  uint32_t MI21:1;
5213  uint32_t MI20:1;
5214  uint32_t MI19:1;
5215  uint32_t MI18:1;
5216  uint32_t MI17:1;
5217  uint32_t MI16:1;
5218  uint32_t MI15:1;
5219  uint32_t MI14:1;
5220  uint32_t MI13:1;
5221  uint32_t MI12:1;
5222  uint32_t MI11:1;
5223  uint32_t MI10:1;
5224  uint32_t MI9:1;
5225  uint32_t MI8:1;
5226  uint32_t MI7:1;
5227  uint32_t MI6:1;
5228  uint32_t MI5:1;
5229  uint32_t MI4:1;
5230  uint32_t MI3:1;
5231  uint32_t MI2:1;
5232  uint32_t MI1:1;
5233  uint32_t MI0:1;
5234  } B;
5235  } RX15MASK;
5236 
5237  union { /* Error Counter Register */
5238  uint32_t R;
5239  struct {
5240  uint32_t:16;
5241  uint32_t RXECNT:8;
5242  uint32_t TXECNT:8;
5243  } B;
5244  } ECR;
5245 
5246  union { /* Error and Status Register */
5247  uint32_t R;
5248  struct {
5249  uint32_t:14;
5250 
5251  uint32_t TWRNINT:1;
5252  uint32_t RWRNINT:1;
5253  uint32_t BIT1ERR:1;
5254  uint32_t BIT0ERR:1;
5255  uint32_t ACKERR:1;
5256  uint32_t CRCERR:1;
5257  uint32_t FRMERR:1;
5258  uint32_t STFERR:1;
5259  uint32_t TXWRN:1;
5260  uint32_t RXWRN:1;
5261  uint32_t IDLE:1;
5262  uint32_t TXRX:1;
5263  uint32_t FLTCONF:2;
5264  uint32_t:1;
5265  uint32_t BOFFINT:1;
5266  uint32_t ERRINT:1;
5267  uint32_t WAKINT:1;
5268  } B;
5269  } ESR;
5270 
5271  union { /* Interruput Masks Register */
5272  uint32_t R;
5273  struct {
5274  uint32_t BUF63M:1;
5275  uint32_t BUF62M:1;
5276  uint32_t BUF61M:1;
5277  uint32_t BUF60M:1;
5278  uint32_t BUF59M:1;
5279  uint32_t BUF58M:1;
5280  uint32_t BUF57M:1;
5281  uint32_t BUF56M:1;
5282  uint32_t BUF55M:1;
5283  uint32_t BUF54M:1;
5284  uint32_t BUF53M:1;
5285  uint32_t BUF52M:1;
5286  uint32_t BUF51M:1;
5287  uint32_t BUF50M:1;
5288  uint32_t BUF49M:1;
5289  uint32_t BUF48M:1;
5290  uint32_t BUF47M:1;
5291  uint32_t BUF46M:1;
5292  uint32_t BUF45M:1;
5293  uint32_t BUF44M:1;
5294  uint32_t BUF43M:1;
5295  uint32_t BUF42M:1;
5296  uint32_t BUF41M:1;
5297  uint32_t BUF40M:1;
5298  uint32_t BUF39M:1;
5299  uint32_t BUF38M:1;
5300  uint32_t BUF37M:1;
5301  uint32_t BUF36M:1;
5302  uint32_t BUF35M:1;
5303  uint32_t BUF34M:1;
5304  uint32_t BUF33M:1;
5305  uint32_t BUF32M:1;
5306  } B;
5307  } IMRH; /* Legacy naming - refer to IMASK2 in Reference Manual */
5308 
5309  union { /* Interruput Masks Register */
5310  uint32_t R;
5311  struct {
5312  uint32_t BUF31M:1;
5313  uint32_t BUF30M:1;
5314  uint32_t BUF29M:1;
5315  uint32_t BUF28M:1;
5316  uint32_t BUF27M:1;
5317  uint32_t BUF26M:1;
5318  uint32_t BUF25M:1;
5319  uint32_t BUF24M:1;
5320  uint32_t BUF23M:1;
5321  uint32_t BUF22M:1;
5322  uint32_t BUF21M:1;
5323  uint32_t BUF20M:1;
5324  uint32_t BUF19M:1;
5325  uint32_t BUF18M:1;
5326  uint32_t BUF17M:1;
5327  uint32_t BUF16M:1;
5328  uint32_t BUF15M:1;
5329  uint32_t BUF14M:1;
5330  uint32_t BUF13M:1;
5331  uint32_t BUF12M:1;
5332  uint32_t BUF11M:1;
5333  uint32_t BUF10M:1;
5334  uint32_t BUF09M:1;
5335  uint32_t BUF08M:1;
5336  uint32_t BUF07M:1;
5337  uint32_t BUF06M:1;
5338  uint32_t BUF05M:1;
5339  uint32_t BUF04M:1;
5340  uint32_t BUF03M:1;
5341  uint32_t BUF02M:1;
5342  uint32_t BUF01M:1;
5343  uint32_t BUF00M:1;
5344  } B;
5345  } IMRL; /* Legacy naming - refer to IMASK1 in Reference Manual */
5346 
5347  union { /* Interruput Flag Register */
5348  uint32_t R;
5349  struct {
5350  uint32_t BUF63I:1;
5351  uint32_t BUF62I:1;
5352  uint32_t BUF61I:1;
5353  uint32_t BUF60I:1;
5354  uint32_t BUF59I:1;
5355  uint32_t BUF58I:1;
5356  uint32_t BUF57I:1;
5357  uint32_t BUF56I:1;
5358  uint32_t BUF55I:1;
5359  uint32_t BUF54I:1;
5360  uint32_t BUF53I:1;
5361  uint32_t BUF52I:1;
5362  uint32_t BUF51I:1;
5363  uint32_t BUF50I:1;
5364  uint32_t BUF49I:1;
5365  uint32_t BUF48I:1;
5366  uint32_t BUF47I:1;
5367  uint32_t BUF46I:1;
5368  uint32_t BUF45I:1;
5369  uint32_t BUF44I:1;
5370  uint32_t BUF43I:1;
5371  uint32_t BUF42I:1;
5372  uint32_t BUF41I:1;
5373  uint32_t BUF40I:1;
5374  uint32_t BUF39I:1;
5375  uint32_t BUF38I:1;
5376  uint32_t BUF37I:1;
5377  uint32_t BUF36I:1;
5378  uint32_t BUF35I:1;
5379  uint32_t BUF34I:1;
5380  uint32_t BUF33I:1;
5381  uint32_t BUF32I:1;
5382  } B;
5383  } IFRH; /* Legacy naming - refer to IFLAG2 in Reference Manual */
5384 
5385  union { /* Interruput Flag Register */
5386  uint32_t R;
5387  struct {
5388  uint32_t BUF31I:1;
5389  uint32_t BUF30I:1;
5390  uint32_t BUF29I:1;
5391  uint32_t BUF28I:1;
5392  uint32_t BUF27I:1;
5393  uint32_t BUF26I:1;
5394  uint32_t BUF25I:1;
5395  uint32_t BUF24I:1;
5396  uint32_t BUF23I:1;
5397  uint32_t BUF22I:1;
5398  uint32_t BUF21I:1;
5399  uint32_t BUF20I:1;
5400  uint32_t BUF19I:1;
5401  uint32_t BUF18I:1;
5402  uint32_t BUF17I:1;
5403  uint32_t BUF16I:1;
5404  uint32_t BUF15I:1;
5405  uint32_t BUF14I:1;
5406  uint32_t BUF13I:1;
5407  uint32_t BUF12I:1;
5408  uint32_t BUF11I:1;
5409  uint32_t BUF10I:1;
5410  uint32_t BUF09I:1;
5411  uint32_t BUF08I:1;
5412  uint32_t BUF07I:1;
5413  uint32_t BUF06I:1;
5414  uint32_t BUF05I:1;
5415  uint32_t BUF04I:1;
5416  uint32_t BUF03I:1;
5417  uint32_t BUF02I:1;
5418  uint32_t BUF01I:1;
5419  uint32_t BUF00I:1;
5420  } B;
5421  } IFRL; /* Legacy naming - refer to IFLAG1 in Reference Manual */
5422 
5423  uint32_t FLEXCAN_reserved0034[19]; /* 0x0034-0x007F */
5424 
5425  struct canbuf_t {
5426  union {
5427  uint32_t R;
5428  struct {
5429  uint32_t:4;
5430  uint32_t CODE:4;
5431  uint32_t:1;
5432  uint32_t SRR:1;
5433  uint32_t IDE:1;
5434  uint32_t RTR:1;
5435  uint32_t LENGTH:4;
5436  uint32_t TIMESTAMP:16;
5437  } B;
5438  } CS;
5439 
5440  union {
5441  uint32_t R;
5442  struct {
5443  uint32_t PRIO:3;
5444  uint32_t STD_ID:11;
5445  uint32_t EXT_ID:18;
5446  } B;
5447  } ID;
5448 
5449  union {
5450  uint8_t B[8]; /* Data buffer in Bytes (8 bits) */
5451  uint16_t H[4]; /* Data buffer in Half-words (16 bits) */
5452  uint32_t W[2]; /* Data buffer in words (32 bits) */
5453  uint32_t R[2]; /* Data buffer in words (32 bits) */
5454  } DATA;
5455 
5456  } BUF[64];
5457 
5458  int32_t FLEXCAN_reserved0480[256]; /* 0x0480-0x087F */
5459 
5460  union { /* RX Individual Mask Registers */
5461  uint32_t R;
5462  struct {
5463  uint32_t MI31:1;
5464  uint32_t MI30:1;
5465  uint32_t MI29:1;
5466  uint32_t MI28:1;
5467  uint32_t MI27:1;
5468  uint32_t MI26:1;
5469  uint32_t MI25:1;
5470  uint32_t MI24:1;
5471  uint32_t MI23:1;
5472  uint32_t MI22:1;
5473  uint32_t MI21:1;
5474  uint32_t MI20:1;
5475  uint32_t MI19:1;
5476  uint32_t MI18:1;
5477  uint32_t MI17:1;
5478  uint32_t MI16:1;
5479  uint32_t MI15:1;
5480  uint32_t MI14:1;
5481  uint32_t MI13:1;
5482  uint32_t MI12:1;
5483  uint32_t MI11:1;
5484  uint32_t MI10:1;
5485  uint32_t MI9:1;
5486  uint32_t MI8:1;
5487  uint32_t MI7:1;
5488  uint32_t MI6:1;
5489  uint32_t MI5:1;
5490  uint32_t MI4:1;
5491  uint32_t MI3:1;
5492  uint32_t MI2:1;
5493  uint32_t MI1:1;
5494  uint32_t MI0:1;
5495  } B;
5496  } RXIMR[64];
5497 
5498  int32_t FLEXCAN_reserved0980[3488]; /* 0x0980-0x3FFF */
5499 
5500  };
5501 
5502 /****************************************************************************/
5503 /* MODULE : FlexRay */
5504 /****************************************************************************/
5505 
5506  typedef union uMVR {
5507  uint16_t R;
5508  struct {
5509  uint16_t CHIVER:8; /* CHI Version Number */
5510  uint16_t PEVER:8; /* PE Version Number */
5511  } B;
5512  } MVR_t;
5513 
5514  typedef union uMCR {
5515  uint16_t R;
5516  struct {
5517  uint16_t MEN:1; /* module enable */
5518  uint16_t:1;
5519  uint16_t SCMD:1; /* single channel mode */
5520  uint16_t CHB:1; /* channel B enable */
5521  uint16_t CHA:1; /* channel A enable */
5522  uint16_t SFFE:1; /* synchronization frame filter enable */
5523  uint16_t:5;
5524  uint16_t CLKSEL:1; /* protocol engine clock source select */
5525  uint16_t PRESCALE:3; /* protocol engine clock prescaler */
5526  uint16_t:1;
5527  } B;
5528  } MCR_t;
5529 
5530  typedef union uSTBSCR {
5531  uint16_t R;
5532  struct {
5533  uint16_t WMD:1; /* write mode */
5534  uint16_t STBSSEL:7; /* strobe signal select */
5535  uint16_t:3;
5536  uint16_t ENB:1; /* strobe signal enable */
5537  uint16_t:2;
5538  uint16_t STBPSEL:2; /* strobe port select */
5539  } B;
5540  } STBSCR_t;
5541  typedef union uSTBPCR {
5542  uint16_t R;
5543  struct {
5544  uint16_t:12;
5545  uint16_t STB3EN:1; /* strobe port enable */
5546  uint16_t STB2EN:1; /* strobe port enable */
5547  uint16_t STB1EN:1; /* strobe port enable */
5548  uint16_t STB0EN:1; /* strobe port enable */
5549  } B;
5550  } STBPCR_t;
5551 
5552  typedef union uMBDSR {
5553  uint16_t R;
5554  struct {
5555  uint16_t:1;
5556  uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */
5557  uint16_t:1;
5558  uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */
5559  } B;
5560  } MBDSR_t;
5561  typedef union uMBSSUTR {
5562  uint16_t R;
5563  struct {
5564 
5565  uint16_t:1;
5566  uint16_t LAST_MB_SEG1:7; /* last message buffer control register for message buffer segment 1 */
5567  uint16_t:1;
5568  uint16_t LAST_MB_UTIL:7; /* last message buffer utilized */
5569  } B;
5570  } MBSSUTR_t;
5571 
5572  typedef union uPOCR {
5573  uint16_t R;
5574  uint8_t byte[2];
5575  struct {
5576  uint16_t WME:1; /* write mode external correction command */
5577  uint16_t:3;
5578  uint16_t EOC_AP:2; /* external offset correction application */
5579  uint16_t ERC_AP:2; /* external rate correction application */
5580  uint16_t BSY:1; /* command write busy / write mode command */
5581  uint16_t:3;
5582  uint16_t POCCMD:4; /* protocol command */
5583  } B;
5584  } POCR_t;
5585 /* protocol commands */
5586  typedef union uGIFER {
5587  uint16_t R;
5588  struct {
5589  uint16_t MIF:1; /* module interrupt flag */
5590  uint16_t PRIF:1; /* protocol interrupt flag */
5591  uint16_t CHIF:1; /* CHI interrupt flag */
5592  uint16_t WKUPIF:1; /* wakeup interrupt flag */
5593  uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
5594  uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
5595  uint16_t RBIF:1; /* receive message buffer interrupt flag */
5596  uint16_t TBIF:1; /* transmit buffer interrupt flag */
5597  uint16_t MIE:1; /* module interrupt enable */
5598  uint16_t PRIE:1; /* protocol interrupt enable */
5599  uint16_t CHIE:1; /* CHI interrupt enable */
5600  uint16_t WKUPIE:1; /* wakeup interrupt enable */
5601  uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
5602  uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
5603  uint16_t RBIE:1; /* receive message buffer interrupt enable */
5604  uint16_t TBIE:1; /* transmit buffer interrupt enable */
5605  } B;
5606  } GIFER_t;
5607  typedef union uPIFR0 {
5608  uint16_t R;
5609  struct {
5610  uint16_t FATLIF:1; /* fatal protocol error interrupt flag */
5611  uint16_t INTLIF:1; /* internal protocol error interrupt flag */
5612  uint16_t ILCFIF:1; /* illegal protocol configuration flag */
5613  uint16_t CSAIF:1; /* cold start abort interrupt flag */
5614  uint16_t MRCIF:1; /* missing rate correctio interrupt flag */
5615  uint16_t MOCIF:1; /* missing offset correctio interrupt flag */
5616  uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */
5617  uint16_t MXSIF:1; /* max sync frames detected interrupt flag */
5618  uint16_t MTXIF:1; /* media access test symbol received flag */
5619  uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
5620  uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
5621  uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
5622  uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
5623  uint16_t TI2IF:1; /* timer 2 expired interrupt flag */
5624  uint16_t TI1IF:1; /* timer 1 expired interrupt flag */
5625  uint16_t CYSIF:1; /* cycle start interrupt flag */
5626  } B;
5627  } PIFR0_t;
5628  typedef union uPIFR1 {
5629  uint16_t R;
5630  struct {
5631  uint16_t EMCIF:1; /* error mode changed interrupt flag */
5632  uint16_t IPCIF:1; /* illegal protocol command interrupt flag */
5633  uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
5634  uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */
5635  uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
5636  uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
5637  uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
5638  uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
5639  uint16_t:2;
5640  uint16_t EVTIF:1; /* even cycle table written interrupt flag */
5641  uint16_t ODTIF:1; /* odd cycle table written interrupt flag */
5642  uint16_t:4;
5643  } B;
5644  } PIFR1_t;
5645  typedef union uPIER0 {
5646  uint16_t R;
5647  struct {
5648  uint16_t FATLIE:1; /* fatal protocol error interrupt enable */
5649  uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */
5650  uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
5651  uint16_t CSAIE:1; /* cold start abort interrupt enable */
5652  uint16_t MRCIE:1; /* missing rate correctio interrupt enable */
5653  uint16_t MOCIE:1; /* missing offset correctio interrupt enable */
5654  uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */
5655  uint16_t MXSIE:1; /* max sync frames detected interrupt enable */
5656  uint16_t MTXIE:1; /* media access test symbol received interrupt enable */
5657  uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
5658  uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
5659  uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
5660  uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
5661  uint16_t TI2IE:1; /* timer 2 expired interrupt enable */
5662  uint16_t TI1IE:1; /* timer 1 expired interrupt enable */
5663  uint16_t CYSIE:1; /* cycle start interrupt enable */
5664  } B;
5665  } PIER0_t;
5666  typedef union uPIER1 {
5667  uint16_t R;
5668  struct {
5669  uint16_t EMCIE:1; /* error mode changed interrupt enable */
5670  uint16_t IPCIE:1; /* illegal protocol command interrupt enable */
5671  uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
5672  uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */
5673  uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
5674  uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
5675  uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
5676  uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
5677  uint16_t:2;
5678  uint16_t EVTIE:1; /* even cycle table written interrupt enable */
5679  uint16_t ODTIE:1; /* odd cycle table written interrupt enable */
5680  uint16_t:4;
5681  } B;
5682  } PIER1_t;
5683  typedef union uCHIERFR {
5684  uint16_t R;
5685  struct {
5686  uint16_t FRLBEF:1; /* flame lost channel B error flag */
5687  uint16_t FRLAEF:1; /* frame lost channel A error flag */
5688  uint16_t PCMIEF:1; /* command ignored error flag */
5689  uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
5690  uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
5691  uint16_t MSBEF:1; /* message buffer search error flag */
5692  uint16_t MBUEF:1; /* message buffer utilization error flag */
5693  uint16_t LCKEF:1; /* lock error flag */
5694  uint16_t DBLEF:1; /* double transmit message buffer lock error flag */
5695  uint16_t SBCFEF:1; /* system bus communication failure error flag */
5696  uint16_t FIDEF:1; /* frame ID error flag */
5697  uint16_t DPLEF:1; /* dynamic payload length error flag */
5698  uint16_t SPLEF:1; /* static payload length error flag */
5699  uint16_t NMLEF:1; /* network management length error flag */
5700  uint16_t NMFEF:1; /* network management frame error flag */
5701  uint16_t ILSAEF:1; /* illegal access error flag */
5702  } B;
5703  } CHIERFR_t;
5704  typedef union uMBIVEC {
5705  uint16_t R;
5706  struct {
5707 
5708  uint16_t:1;
5709  uint16_t TBIVEC:7; /* transmit buffer interrupt vector */
5710  uint16_t:1;
5711  uint16_t RBIVEC:7; /* receive buffer interrupt vector */
5712  } B;
5713  } MBIVEC_t;
5714 
5715  typedef union uPSR0 {
5716  uint16_t R;
5717  struct {
5718  uint16_t ERRMODE:2; /* error mode */
5719  uint16_t SLOTMODE:2; /* slot mode */
5720  uint16_t:1;
5721  uint16_t PROTSTATE:3; /* protocol state */
5722  uint16_t SUBSTATE:4; /* protocol sub state */
5723  uint16_t:1;
5724  uint16_t WAKEUPSTATUS:3; /* wakeup status */
5725  } B;
5726  } PSR0_t;
5727 
5728 /* protocol states */
5729 /* protocol sub-states */
5730 /* wakeup status */
5731  typedef union uPSR1 {
5732  uint16_t R;
5733  struct {
5734  uint16_t CSAA:1; /* cold start attempt abort flag */
5735  uint16_t SCP:1; /* cold start path */
5736  uint16_t:1;
5737  uint16_t REMCSAT:5; /* remanining coldstart attempts */
5738  uint16_t CPN:1; /* cold start noise path */
5739  uint16_t HHR:1; /* host halt request pending */
5740  uint16_t FRZ:1; /* freeze occured */
5741  uint16_t APTAC:5; /* allow passive to active counter */
5742  } B;
5743  } PSR1_t;
5744  typedef union uPSR2 {
5745  uint16_t R;
5746  struct {
5747  uint16_t NBVB:1; /* NIT boundary violation on channel B */
5748  uint16_t NSEB:1; /* NIT syntax error on channel B */
5749  uint16_t STCB:1; /* symbol window transmit conflict on channel B */
5750  uint16_t SBVB:1; /* symbol window boundary violation on channel B */
5751  uint16_t SSEB:1; /* symbol window syntax error on channel B */
5752  uint16_t MTB:1; /* media access test symbol MTS received on channel B */
5753  uint16_t NBVA:1; /* NIT boundary violation on channel A */
5754  uint16_t NSEA:1; /* NIT syntax error on channel A */
5755  uint16_t STCA:1; /* symbol window transmit conflict on channel A */
5756  uint16_t SBVA:1; /* symbol window boundary violation on channel A */
5757  uint16_t SSEA:1; /* symbol window syntax error on channel A */
5758  uint16_t MTA:1; /* media access test symbol MTS received on channel A */
5759  uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
5760  } B;
5761  } PSR2_t;
5762  typedef union uPSR3 {
5763  uint16_t R;
5764  struct {
5765  uint16_t:2;
5766  uint16_t WUB:1; /* wakeup symbol received on channel B */
5767  uint16_t ABVB:1; /* aggregated boundary violation on channel B */
5768  uint16_t AACB:1; /* aggregated additional communication on channel B */
5769  uint16_t ACEB:1; /* aggregated content error on channel B */
5770  uint16_t ASEB:1; /* aggregated syntax error on channel B */
5771  uint16_t AVFB:1; /* aggregated valid frame on channel B */
5772  uint16_t:2;
5773  uint16_t WUA:1; /* wakeup symbol received on channel A */
5774  uint16_t ABVA:1; /* aggregated boundary violation on channel A */
5775  uint16_t AACA:1; /* aggregated additional communication on channel A */
5776  uint16_t ACEA:1; /* aggregated content error on channel A */
5777  uint16_t ASEA:1; /* aggregated syntax error on channel A */
5778  uint16_t AVFA:1; /* aggregated valid frame on channel A */
5779  } B;
5780  } PSR3_t;
5781  typedef union uCIFRR {
5782  uint16_t R;
5783  struct {
5784  uint16_t:8;
5785  uint16_t MIFR:1; /* module interrupt flag */
5786  uint16_t PRIFR:1; /* protocol interrupt flag */
5787  uint16_t CHIFR:1; /* CHI interrupt flag */
5788  uint16_t WUPIFR:1; /* wakeup interrupt flag */
5789  uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */
5790  uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */
5791  uint16_t RBIFR:1; /* receive message buffer interrupt flag */
5792  uint16_t TBIFR:1; /* transmit buffer interrupt flag */
5793  } B;
5794  } CIFRR_t;
5795  typedef union uSFCNTR {
5796  uint16_t R;
5797  struct {
5798  uint16_t SFEVB:4; /* sync frames channel B, even cycle */
5799  uint16_t SFEVA:4; /* sync frames channel A, even cycle */
5800  uint16_t SFODB:4; /* sync frames channel B, odd cycle */
5801  uint16_t SFODA:4; /* sync frames channel A, odd cycle */
5802  } B;
5803  } SFCNTR_t;
5804 
5805  typedef union uSFTCCSR {
5806  uint16_t R;
5807  struct {
5808  uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */
5809  uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */
5810  uint16_t CYCNUM:6; /* cycle number */
5811  uint16_t ELKS:1; /* even cycle tables lock status */
5812  uint16_t OLKS:1; /* odd cycle tables lock status */
5813  uint16_t EVAL:1; /* even cycle tables valid */
5814  uint16_t OVAL:1; /* odd cycle tables valid */
5815  uint16_t:1;
5816  uint16_t OPT:1; /*one pair trigger */
5817  uint16_t SDVEN:1; /* sync frame deviation table enable */
5818  uint16_t SIDEN:1; /* sync frame ID table enable */
5819  } B;
5820  } SFTCCSR_t;
5821  typedef union uSFIDRFR {
5822  uint16_t R;
5823  struct {
5824  uint16_t:6;
5825  uint16_t SYNFRID:10; /* sync frame rejection ID */
5826  } B;
5827  } SFIDRFR_t;
5828 
5829  typedef union uTICCR {
5830  uint16_t R;
5831  struct {
5832  uint16_t:2;
5833  uint16_t T2CFG:1; /* timer 2 configuration */
5834  uint16_t T2REP:1; /* timer 2 repetitive mode */
5835  uint16_t:1;
5836  uint16_t T2SP:1; /* timer 2 stop */
5837  uint16_t T2TR:1; /* timer 2 trigger */
5838  uint16_t T2ST:1; /* timer 2 state */
5839  uint16_t:3;
5840  uint16_t T1REP:1; /* timer 1 repetitive mode */
5841  uint16_t:1;
5842  uint16_t T1SP:1; /* timer 1 stop */
5843  uint16_t T1TR:1; /* timer 1 trigger */
5844  uint16_t T1ST:1; /* timer 1 state */
5845 
5846  } B;
5847  } TICCR_t;
5848  typedef union uTI1CYSR {
5849  uint16_t R;
5850  struct {
5851  uint16_t:2;
5852  uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */
5853  uint16_t:2;
5854  uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */
5855 
5856  } B;
5857  } TI1CYSR_t;
5858 
5859  typedef union uSSSR {
5860  uint16_t R;
5861  struct {
5862  uint16_t WMD:1; /* write mode */
5863  uint16_t:1;
5864  uint16_t SEL:2; /* static slot number */
5865  uint16_t:1;
5866  uint16_t SLOTNUMBER:11; /* selector */
5867  } B;
5868  } SSSR_t;
5869 
5870  typedef union uSSCCR {
5871  uint16_t R;
5872  struct {
5873  uint16_t WMD:1; /* write mode */
5874  uint16_t:1;
5875  uint16_t SEL:2; /* selector */
5876  uint16_t:1;
5877  uint16_t CNTCFG:2; /* counter configuration */
5878  uint16_t MCY:1; /* multi cycle selection */
5879  uint16_t VFR:1; /* valid frame selection */
5880  uint16_t SYF:1; /* sync frame selection */
5881  uint16_t NUF:1; /* null frame selection */
5882  uint16_t SUF:1; /* startup frame selection */
5883  uint16_t STATUSMASK:4; /* slot status mask */
5884  } B;
5885  } SSCCR_t;
5886  typedef union uSSR {
5887  uint16_t R;
5888  struct {
5889  uint16_t VFB:1; /* valid frame on channel B */
5890  uint16_t SYB:1; /* valid sync frame on channel B */
5891  uint16_t NFB:1; /* valid null frame on channel B */
5892  uint16_t SUB:1; /* valid startup frame on channel B */
5893  uint16_t SEB:1; /* syntax error on channel B */
5894  uint16_t CEB:1; /* content error on channel B */
5895  uint16_t BVB:1; /* boundary violation on channel B */
5896  uint16_t TCB:1; /* tx conflict on channel B */
5897  uint16_t VFA:1; /* valid frame on channel A */
5898  uint16_t SYA:1; /* valid sync frame on channel A */
5899  uint16_t NFA:1; /* valid null frame on channel A */
5900  uint16_t SUA:1; /* valid startup frame on channel A */
5901  uint16_t SEA:1; /* syntax error on channel A */
5902  uint16_t CEA:1; /* content error on channel A */
5903  uint16_t BVA:1; /* boundary violation on channel A */
5904  uint16_t TCA:1; /* tx conflict on channel A */
5905  } B;
5906  } SSR_t;
5907  typedef union uMTSCFR {
5908  uint16_t R;
5909  struct {
5910  uint16_t MTE:1; /* media access test symbol transmission enable */
5911  uint16_t:1;
5912  uint16_t CYCCNTMSK:6; /* cycle counter mask */
5913  uint16_t:2;
5914  uint16_t CYCCNTVAL:6; /* cycle counter value */
5915  } B;
5916  } MTSCFR_t;
5917  typedef union uRSBIR {
5918  uint16_t R;
5919  struct {
5920  uint16_t WMD:1; /* write mode */
5921  uint16_t:1;
5922  uint16_t SEL:2; /* selector */
5923  uint16_t:4;
5924  uint16_t RSBIDX:8; /* receive shadow buffer index */
5925  } B;
5926  } RSBIR_t;
5927  typedef union uRFDSR {
5928  uint16_t R;
5929  struct {
5930  uint16_t FIFODEPTH:8; /* fifo depth */
5931  uint16_t:1;
5932  uint16_t ENTRYSIZE:7; /* entry size */
5933  } B;
5934  } RFDSR_t;
5935 
5936  typedef union uRFRFCFR {
5937  uint16_t R;
5938  struct {
5939  uint16_t WMD:1; /* write mode */
5940  uint16_t IBD:1; /* interval boundary */
5941  uint16_t SEL:2; /* filter number */
5942  uint16_t:1;
5943  uint16_t SID:11; /* slot ID */
5944  } B;
5945  } RFRFCFR_t;
5946 
5947  typedef union uRFRFCTR {
5948  uint16_t R;
5949  struct {
5950  uint16_t:4;
5951  uint16_t F3MD:1; /* filter mode */
5952  uint16_t F2MD:1; /* filter mode */
5953  uint16_t F1MD:1; /* filter mode */
5954  uint16_t F0MD:1; /* filter mode */
5955  uint16_t:4;
5956  uint16_t F3EN:1; /* filter enable */
5957  uint16_t F2EN:1; /* filter enable */
5958  uint16_t F1EN:1; /* filter enable */
5959  uint16_t F0EN:1; /* filter enable */
5960  } B;
5961  } RFRFCTR_t;
5962  typedef union uPCR0 {
5963  uint16_t R;
5964  struct {
5965  uint16_t ACTION_POINT_OFFSET:6;
5966  uint16_t STATIC_SLOT_LENGTH:10;
5967  } B;
5968  } PCR0_t;
5969 
5970  typedef union uPCR1 {
5971  uint16_t R;
5972  struct {
5973  uint16_t:2;
5974  uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
5975  } B;
5976  } PCR1_t;
5977 
5978  typedef union uPCR2 {
5979  uint16_t R;
5980  struct {
5981  uint16_t MINISLOT_AFTER_ACTION_POINT:6;
5982  uint16_t NUMBER_OF_STATIC_SLOTS:10;
5983  } B;
5984  } PCR2_t;
5985 
5986  typedef union uPCR3 {
5987  uint16_t R;
5988  struct {
5989  uint16_t WAKEUP_SYMBOL_RX_LOW:6;
5990  uint16_t MINISLOT_ACTION_POINT_OFFSET:5;
5991  uint16_t COLDSTART_ATTEMPTS:5;
5992  } B;
5993  } PCR3_t;
5994 
5995  typedef union uPCR4 {
5996  uint16_t R;
5997  struct {
5998  uint16_t CAS_RX_LOW_MAX:7;
5999  uint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
6000  } B;
6001  } PCR4_t;
6002 
6003  typedef union uPCR5 {
6004  uint16_t R;
6005  struct {
6006  uint16_t TSS_TRANSMITTER:4;
6007  uint16_t WAKEUP_SYMBOL_TX_LOW:6;
6008  uint16_t WAKEUP_SYMBOL_RX_IDLE:6;
6009  } B;
6010  } PCR5_t;
6011 
6012  typedef union uPCR6 {
6013  uint16_t R;
6014  struct {
6015  uint16_t:1;
6016  uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
6017  uint16_t MACRO_INITIAL_OFFSET_A:7;
6018  } B;
6019  } PCR6_t;
6020 
6021  typedef union uPCR7 {
6022  uint16_t R;
6023  struct {
6024  uint16_t DECODING_CORRECTION_B:9;
6025  uint16_t MICRO_PER_MACRO_NOM_HALF:7;
6026  } B;
6027  } PCR7_t;
6028 
6029  typedef union uPCR8 {
6030  uint16_t R;
6031  struct {
6032  uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
6033  uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
6034  uint16_t WAKEUP_SYMBOL_TX_IDLE:8;
6035  } B;
6036  } PCR8_t;
6037 
6038  typedef union uPCR9 {
6039  uint16_t R;
6040  struct {
6041  uint16_t MINISLOT_EXISTS:1;
6042  uint16_t SYMBOL_WINDOW_EXISTS:1;
6043  uint16_t OFFSET_CORRECTION_OUT:14;
6044  } B;
6045  } PCR9_t;
6046 
6047  typedef union uPCR10 {
6048  uint16_t R;
6049  struct {
6050  uint16_t SINGLE_SLOT_ENABLED:1;
6051  uint16_t WAKEUP_CHANNEL:1;
6052  uint16_t MACRO_PER_CYCLE:14;
6053  } B;
6054  } PCR10_t;
6055 
6056  typedef union uPCR11 {
6057  uint16_t R;
6058  struct {
6059  uint16_t KEY_SLOT_USED_FOR_STARTUP:1;
6060  uint16_t KEY_SLOT_USED_FOR_SYNC:1;
6061  uint16_t OFFSET_CORRECTION_START:14;
6062  } B;
6063  } PCR11_t;
6064 
6065  typedef union uPCR12 {
6066  uint16_t R;
6067  struct {
6068  uint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
6069  uint16_t KEY_SLOT_HEADER_CRC:11;
6070  } B;
6071  } PCR12_t;
6072 
6073  typedef union uPCR13 {
6074  uint16_t R;
6075  struct {
6076  uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
6077  uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
6078  } B;
6079  } PCR13_t;
6080 
6081  typedef union uPCR14 {
6082  uint16_t R;
6083  struct {
6084  uint16_t RATE_CORRECTION_OUT:11;
6085  uint16_t LISTEN_TIMEOUT_H:5;
6086  } B;
6087  } PCR14_t;
6088 
6089  typedef union uPCR15 {
6090  uint16_t R;
6091  struct {
6092  uint16_t LISTEN_TIMEOUT_L:16;
6093  } B;
6094  } PCR15_t;
6095 
6096  typedef union uPCR16 {
6097  uint16_t R;
6098  struct {
6099  uint16_t MACRO_INITIAL_OFFSET_B:7;
6100  uint16_t NOISE_LISTEN_TIMEOUT_H:9;
6101  } B;
6102  } PCR16_t;
6103 
6104  typedef union uPCR17 {
6105  uint16_t R;
6106  struct {
6107  uint16_t NOISE_LISTEN_TIMEOUT_L:16;
6108  } B;
6109  } PCR17_t;
6110 
6111  typedef union uPCR18 {
6112  uint16_t R;
6113  struct {
6114  uint16_t WAKEUP_PATTERN:6;
6115  uint16_t KEY_SLOT_ID:10;
6116  } B;
6117  } PCR18_t;
6118 
6119  typedef union uPCR19 {
6120  uint16_t R;
6121  struct {
6122  uint16_t DECODING_CORRECTION_A:9;
6123  uint16_t PAYLOAD_LENGTH_STATIC:7;
6124  } B;
6125  } PCR19_t;
6126 
6127  typedef union uPCR20 {
6128  uint16_t R;
6129  struct {
6130  uint16_t MICRO_INITIAL_OFFSET_B:8;
6131  uint16_t MICRO_INITIAL_OFFSET_A:8;
6132  } B;
6133  } PCR20_t;
6134 
6135  typedef union uPCR21 {
6136  uint16_t R;
6137  struct {
6138  uint16_t EXTERN_RATE_CORRECTION:3;
6139  uint16_t LATEST_TX:13;
6140  } B;
6141  } PCR21_t;
6142 
6143  typedef union uPCR22 {
6144  uint16_t R;
6145  struct {
6146  uint16_t:1;
6147  uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
6148  uint16_t MICRO_PER_CYCLE_H:4;
6149  } B;
6150  } PCR22_t;
6151 
6152  typedef union uPCR23 {
6153  uint16_t R;
6154  struct {
6155  uint16_t micro_per_cycle_l:16;
6156  } B;
6157  } PCR23_t;
6158 
6159  typedef union uPCR24 {
6160  uint16_t R;
6161  struct {
6162  uint16_t CLUSTER_DRIFT_DAMPING:5;
6163  uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
6164  uint16_t MICRO_PER_CYCLE_MIN_H:4;
6165  } B;
6166  } PCR24_t;
6167 
6168  typedef union uPCR25 {
6169  uint16_t R;
6170  struct {
6171  uint16_t MICRO_PER_CYCLE_MIN_L:16;
6172  } B;
6173  } PCR25_t;
6174 
6175  typedef union uPCR26 {
6176  uint16_t R;
6177  struct {
6178  uint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
6179  uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
6180  uint16_t MICRO_PER_CYCLE_MAX_H:4;
6181  } B;
6182  } PCR26_t;
6183 
6184  typedef union uPCR27 {
6185  uint16_t R;
6186  struct {
6187  uint16_t MICRO_PER_CYCLE_MAX_L:16;
6188  } B;
6189  } PCR27_t;
6190 
6191  typedef union uPCR28 {
6192  uint16_t R;
6193  struct {
6194  uint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
6195  uint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
6196  } B;
6197  } PCR28_t;
6198 
6199  typedef union uPCR29 {
6200  uint16_t R;
6201  struct {
6202  uint16_t EXTERN_OFFSET_CORRECTION:3;
6203  uint16_t MINISLOTS_MAX:13;
6204  } B;
6205  } PCR29_t;
6206 
6207  typedef union uPCR30 {
6208  uint16_t R;
6209  struct {
6210  uint16_t:12;
6211  uint16_t SYNC_NODE_MAX:4;
6212  } B;
6213  } PCR30_t;
6214 
6215  typedef struct uMSG_BUFF_CCS {
6216  union {
6217  uint16_t R;
6218  struct {
6219  uint16_t:1;
6220  uint16_t MCM:1; /* message buffer commit mode */
6221  uint16_t MBT:1; /* message buffer type */
6222  uint16_t MTD:1; /* message buffer direction */
6223  uint16_t CMT:1; /* commit for transmission */
6224  uint16_t EDT:1; /* enable / disable trigger */
6225  uint16_t LCKT:1; /* lock request trigger */
6226  uint16_t MBIE:1; /* message buffer interrupt enable */
6227  uint16_t:3;
6228  uint16_t DUP:1; /* data updated */
6229  uint16_t DVAL:1; /* data valid */
6230  uint16_t EDS:1; /* lock status */
6231  uint16_t LCKS:1; /* enable / disable status */
6232  uint16_t MBIF:1; /* message buffer interrupt flag */
6233  } B;
6234  } MBCCSR;
6235  union {
6236  uint16_t R;
6237  struct {
6238  uint16_t MTM:1; /* message buffer transmission mode */
6239  uint16_t CHNLA:1; /* channel assignement */
6240  uint16_t CHNLB:1; /* channel assignement */
6241  uint16_t CCFE:1; /* cycle counter filter enable */
6242  uint16_t CCFMSK:6; /* cycle counter filter mask */
6243  uint16_t CCFVAL:6; /* cycle counter filter value */
6244  } B;
6245  } MBCCFR;
6246  union {
6247  uint16_t R;
6248  struct {
6249  uint16_t:5;
6250  uint16_t FID:11; /* frame ID */
6251  } B;
6252  } MBFIDR;
6253  union {
6254  uint16_t R;
6255  struct {
6256  uint16_t:8;
6257  uint16_t MBIDX:8; /* message buffer index */
6258  } B;
6259  } MBIDXR;
6260  } MSG_BUFF_CCS_t;
6261  typedef union uSYSBADHR {
6262  uint16_t R;
6263  } SYSBADHR_t;
6264  typedef union uSYSBADLR {
6265  uint16_t R;
6266  } SYSBADLR_t;
6267  typedef union uPDAR {
6268  uint16_t R;
6269  } PDAR_t;
6270  typedef union uCASERCR {
6271  uint16_t R;
6272  } CASERCR_t;
6273  typedef union uCBSERCR {
6274  uint16_t R;
6275  } CBSERCR_t;
6276  typedef union uCYCTR {
6277  uint16_t R;
6278  } CYCTR_t;
6279  typedef union uMTCTR {
6280  uint16_t R;
6281  } MTCTR_t;
6282  typedef union uSLTCTAR {
6283  uint16_t R;
6284  } SLTCTAR_t;
6285  typedef union uSLTCTBR {
6286  uint16_t R;
6287  } SLTCTBR_t;
6288  typedef union uRTCORVR {
6289  uint16_t R;
6290  } RTCORVR_t;
6291  typedef union uOFCORVR {
6292  uint16_t R;
6293  } OFCORVR_t;
6294  typedef union uSFTOR {
6295  uint16_t R;
6296  } SFTOR_t;
6297  typedef union uSFIDAFVR {
6298  uint16_t R;
6299  } SFIDAFVR_t;
6300  typedef union uSFIDAFMR {
6301  uint16_t R;
6302  } SFIDAFMR_t;
6303  typedef union uNMVR {
6304  uint16_t R;
6305  } NMVR_t;
6306  typedef union uNMVLR {
6307  uint16_t R;
6308  } NMVLR_t;
6309  typedef union uT1MTOR {
6310  uint16_t R;
6311  } T1MTOR_t;
6312  typedef union uTI2CR0 {
6313  uint16_t R;
6314  } TI2CR0_t;
6315  typedef union uTI2CR1 {
6316  uint16_t R;
6317  } TI2CR1_t;
6318  typedef union uSSCR {
6319  uint16_t R;
6320  } SSCR_t;
6321  typedef union uRFSR {
6322  uint16_t R;
6323  } RFSR_t;
6324  typedef union uRFSIR {
6325  uint16_t R;
6326  } RFSIR_t;
6327  typedef union uRFARIR {
6328  uint16_t R;
6329  } RFARIR_t;
6330  typedef union uRFBRIR {
6331  uint16_t R;
6332  } RFBRIR_t;
6333  typedef union uRFMIDAFVR {
6334  uint16_t R;
6335  } RFMIDAFVR_t;
6336  typedef union uRFMIAFMR {
6337  uint16_t R;
6338  } RFMIAFMR_t;
6339  typedef union uRFFIDRFVR {
6340  uint16_t R;
6341  } RFFIDRFVR_t;
6342  typedef union uRFFIDRFMR {
6343  uint16_t R;
6344  } RFFIDRFMR_t;
6345  typedef union uLDTXSLAR {
6346  uint16_t R;
6347  } LDTXSLAR_t;
6348  typedef union uLDTXSLBR {
6349  uint16_t R;
6350  } LDTXSLBR_t;
6351 
6352  typedef struct FR_tag {
6353  volatile MVR_t MVR; /*module version register *//*0 */
6354  volatile MCR_t MCR; /*module configuration register *//*2 */
6355  volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */
6356  volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */
6357  volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */
6358  volatile STBPCR_t STBPCR; /*strobe port control register *//*A */
6359  volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */
6360  volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */
6361  uint16_t reserved3a[1]; /*10 */
6362  volatile PDAR_t PDAR; /*PE data register *//*12 */
6363  volatile POCR_t POCR; /*Protocol operation control register *//*14 */
6364  volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */
6365  volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */
6366  volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */
6367  volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */
6368  volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */
6369  volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */
6370  volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */
6371  volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */
6372  volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */
6373  volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */
6374  volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */
6375  volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */
6376  volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */
6377  volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */
6378  volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */
6379  volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */
6380  volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */
6381  volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */
6382  volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */
6383  volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */
6384  uint16_t reserved3[1]; /*3E */
6385  volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */
6386  volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */
6387  volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */
6388  volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */
6389  volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */
6390  volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */
6391  volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */
6392  volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */
6393  volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */
6394  volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */
6395  volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */
6396  volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */
6397  volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */
6398  volatile SSSR_t SSSR; /*slot status selection register *//*64 */
6399  volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */
6400  volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */
6401  volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */
6402  volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */
6403  volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */
6404  volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */
6405  volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */
6406  volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */
6407  volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */
6408  volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */
6409  volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */
6410  volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */
6411  volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */
6412  volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */
6413  volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */
6414  volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */
6415  volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */
6416  volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */
6417  volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */
6418  volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */
6419  volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */
6420  volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */
6421  volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */
6422  volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */
6423  volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */
6424  volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */
6425  volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */
6426  volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */
6427  volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */
6428  volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */
6429  volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */
6430  volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */
6431  volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */
6432  volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */
6433  volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */
6434  volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */
6435  volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */
6436  volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */
6437  volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */
6438  volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */
6439  volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */
6440  volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */
6441  volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */
6442  volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */
6443  volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */
6444  volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */
6445  volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */
6446  volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */
6447  volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */
6448  volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */
6449  uint16_t reserved2[17];
6450  volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */
6451  } FR_tag_t;
6452 
6453  typedef union uF_HEADER /* frame header */
6454  {
6455  struct {
6456  uint16_t:5;
6457  uint16_t HDCRC:11; /* Header CRC */
6458  uint16_t:2;
6459  uint16_t CYCCNT:6; /* Cycle Count */
6460  uint16_t:1;
6461  uint16_t PLDLEN:7; /* Payload Length */
6462  uint16_t:1;
6463  uint16_t PPI:1; /* Payload Preamble Indicator */
6464  uint16_t NUF:1; /* Null Frame Indicator */
6465  uint16_t SYF:1; /* Sync Frame Indicator */
6466  uint16_t SUF:1; /* Startup Frame Indicator */
6467  uint16_t FID:11; /* Frame ID */
6468  } B;
6469  uint16_t WORDS[3];
6470  } F_HEADER_t;
6471  typedef union uS_STSTUS /* slot status */
6472  {
6473  struct {
6474  uint16_t VFB:1; /* Valid Frame on channel B */
6475  uint16_t SYB:1; /* Sync Frame Indicator channel B */
6476  uint16_t NFB:1; /* Null Frame Indicator channel B */
6477  uint16_t SUB:1; /* Startup Frame Indicator channel B */
6478  uint16_t SEB:1; /* Syntax Error on channel B */
6479  uint16_t CEB:1; /* Content Error on channel B */
6480  uint16_t BVB:1; /* Boundary Violation on channel B */
6481  uint16_t CH:1; /* Channel */
6482  uint16_t VFA:1; /* Valid Frame on channel A */
6483  uint16_t SYA:1; /* Sync Frame Indicator channel A */
6484  uint16_t NFA:1; /* Null Frame Indicator channel A */
6485  uint16_t SUA:1; /* Startup Frame Indicator channel A */
6486  uint16_t SEA:1; /* Syntax Error on channel A */
6487  uint16_t CEA:1; /* Content Error on channel A */
6488  uint16_t BVA:1; /* Boundary Violation on channel A */
6489  uint16_t:1;
6490  } RX;
6491  struct {
6492  uint16_t VFB:1; /* Valid Frame on channel B */
6493  uint16_t SYB:1; /* Sync Frame Indicator channel B */
6494  uint16_t NFB:1; /* Null Frame Indicator channel B */
6495  uint16_t SUB:1; /* Startup Frame Indicator channel B */
6496  uint16_t SEB:1; /* Syntax Error on channel B */
6497  uint16_t CEB:1; /* Content Error on channel B */
6498  uint16_t BVB:1; /* Boundary Violation on channel B */
6499  uint16_t TCB:1; /* Tx Conflict on channel B */
6500  uint16_t VFA:1; /* Valid Frame on channel A */
6501  uint16_t SYA:1; /* Sync Frame Indicator channel A */
6502  uint16_t NFA:1; /* Null Frame Indicator channel A */
6503  uint16_t SUA:1; /* Startup Frame Indicator channel A */
6504  uint16_t SEA:1; /* Syntax Error on channel A */
6505  uint16_t CEA:1; /* Content Error on channel A */
6506  uint16_t BVA:1; /* Boundary Violation on channel A */
6507  uint16_t TCA:1; /* Tx Conflict on channel A */
6508  } TX;
6509  uint16_t R;
6510  } S_STATUS_t;
6511 
6512  typedef struct uMB_HEADER /* message buffer header */
6513  {
6514  F_HEADER_t FRAME_HEADER;
6515  uint16_t DATA_OFFSET;
6516  S_STATUS_t SLOT_STATUS;
6517  } MB_HEADER_t;
6518 
6519 /* Define memories */
6520 
6521 #define SRAM_START 0x40000000
6522 #define SRAM_SIZE 0x40000
6523 #define SRAM_END 0x4003FFFF
6524 
6525 #define FLASH_START 0x00000000
6526 #define FLASH_SIZE 0x400000
6527 #define FLASH_END 0x003FFFFF
6528 
6529 /* Define instances of modules */
6530 #define PBRIDGE_A (*( volatile struct PBRIDGE_A_tag *) 0xC3F00000)
6531 #define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000)
6532 #define EBI (*( volatile struct EBI_tag *) 0xC3F84000)
6533 #define FLASH_A (*( volatile struct FLASH_tag *) 0xC3F88000)
6534 #define FLASH FLASH_A
6535 #define FLASH_B (*( volatile struct FLASH_tag *) 0xC3F8C000)
6536 #define SIU (*( volatile struct SIU_tag *) 0xC3F90000)
6537 
6538 #define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000)
6539 #define PMC (*( volatile struct PMC_tag *) 0xC3FBC000)
6540 
6541 #define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000)
6542 #define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000)
6543 #define ETPU_DATA_RAM_END 0xC3FC8FFC
6544 #define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000)
6545 #define CODE_RAM (*( uint32_t *) 0xC3FD0000)
6546 #define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000)
6547 
6548 #define PIT (*( volatile struct PIT_tag *) 0xC3FF0000)
6549 
6550 #define PBRIDGE_B (*( volatile struct PBRIDGE_B_tag *) 0xFFF00000)
6551 #define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000)
6552 #define MPU (*( volatile struct MPU_tag *) 0xFFF10000)
6553 #define SWT (*( volatile struct SWT_tag *) 0xFFF38000)
6554 #define STM (*( volatile struct STM_tag *) 0xFFF3C000)
6555 #define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000)
6556 #define EDMA_A (*( volatile struct EDMA_tag *) 0xFFF44000)
6557 #define EDMA EDMA_A
6558 #define INTC (*( volatile struct INTC_tag *) 0xFFF48000)
6559 #define EDMA_B (*( volatile struct EDMA_tag *) 0xFFF54000)
6560 
6561 #define EQADC_A (*( volatile struct EQADC_tag *) 0xFFF80000)
6562 #define EQADC EQADC_A
6563 #define EQADC_B (*( volatile struct EQADC_tag *) 0xFFF84000)
6564 
6565 #define DECFIL_A (*( volatile struct DECFIL_tag *) 0xFFF88000)
6566 #define DECFIL_B (*( volatile struct DECFIL_tag *) 0xFFF88800)
6567 #define DECFIL_C (*( volatile struct DECFIL_tag *) 0xFFF89000)
6568 #define DECFIL_D (*( volatile struct DECFIL_tag *) 0xFFF89800)
6569 #define DECFIL_E (*( volatile struct DECFIL_tag *) 0xFFF8A000)
6570 #define DECFIL_F (*( volatile struct DECFIL_tag *) 0xFFF8A800)
6571 #define DECFIL_G (*( volatile struct DECFIL_tag *) 0xFFF8B000)
6572 #define DECFIL_H (*( volatile struct DECFIL_tag *) 0xFFF8B800)
6573 
6574 #define DSPI_A (*( volatile struct DSPI_tag *) 0xFFF90000)
6575 #define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000)
6576 #define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000)
6577 #define DSPI_D (*( volatile struct DSPI_tag *) 0xFFF9C000)
6578 
6579 #define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000)
6580 #define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000)
6581 #define ESCI_C (*( volatile struct ESCI_tag *) 0xFFFB8000)
6582 #define ESCI_D (*( volatile struct ESCI_tag *) 0xFFFBC000)
6583 
6584 #define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000)
6585 #define CAN_B (*( volatile struct FLEXCAN2_tag *) 0xFFFC4000)
6586 #define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000)
6587 #define CAN_D (*( volatile struct FLEXCAN2_tag *) 0xFFFCC000)
6588 
6589 #define FR (*( volatile struct FR_tag *) 0xFFFE0000)
6590 #define TSENS (*( volatile struct TSENS_tag *) 0xFFFEC000)
6591 
6592 #ifdef __MWERKS__
6593 #pragma pop
6594 #endif
6595 
6596 #ifdef __cplusplus
6597 }
6598 #endif
6599 #endif /* ASM */
6600 #endif /* ifdef _MPC5674_H */
6601 /*********************************************************************
6602  *
6603  * Copyright:
6604  * Freescale Semiconductor, INC. All Rights Reserved.
6605  * You are hereby granted a copyright license to use, modify, and
6606  * distribute the SOFTWARE so long as this entire notice is
6607  * retained without alteration in any modified and/or redistributed
6608  * versions, and that such modified versions are clearly identified
6609  * as such. No licenses are granted by implication, estoppel or
6610  * otherwise under any patents or trademarks of Freescale
6611  * Semiconductor, Inc. This software is provided on an "AS IS"
6612  * basis and without warranty.
6613  *
6614  * To the maximum extent permitted by applicable law, Freescale
6615  * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
6616  * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
6617  * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH
6618  * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
6619  * AND ANY ACCOMPANYING WRITTEN MATERIALS.
6620  *
6621  * To the maximum extent permitted by applicable law, IN NO EVENT
6622  * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER
6623  * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS,
6624  * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER
6625  * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
6626  *
6627  * Freescale Semiconductor assumes no responsibility for the
6628  * maintenance and support of this software
6629  *
6630  ********************************************************************/
uTICCR
Definition: fsl-mpc551x.h:3093
uSLTCTAR
Definition: fsl-mpc551x.h:3552
uRSBIR
Definition: fsl-mpc551x.h:3182
EQADC_tag::EQADC_RFPR_tag
Definition: fsl-mpc567x.h:4311
EQADC_tag::EQADC_SSICR_tag
Definition: fsl-mpc567x.h:4453
uNMVLR
Definition: fsl-mpc551x.h:3576
uPCR8
Definition: fsl-mpc551x.h:3295
uRFFIDRFMR
Definition: fsl-mpc551x.h:3612
TCR
#define TCR
tx configuration reg
Definition: wd80x3.h:99
uSFIDAFMR
Definition: fsl-mpc551x.h:3570
uPCR23
Definition: fsl-mpc551x.h:3418
uRFRFCTR
Definition: fsl-mpc551x.h:3213
PE
#define PE
Parity Error.
Definition: uart.h:125
uRFMIDAFVR
Definition: fsl-mpc551x.h:3603
XBAR_tag
Definition: fsl-mpc555x.h:1982
EQADC_tag::EQADC_CFCR_tag
Definition: fsl-mpc555x.h:2451
uPCR15
Definition: fsl-mpc551x.h:3355
uPIFR1
Definition: fsl-mpc551x.h:2884
DR
#define DR
Bits definition of the Line Status Register (LSR)
Definition: uart.h:123
uPIER1
Definition: fsl-mpc551x.h:2922
uRFFIDRFVR
Definition: fsl-mpc551x.h:3609
ESCI_tag
Definition: fsl-mpc551x.h:899
uSFIDAFVR
Definition: fsl-mpc551x.h:3567
uSSCCR
Definition: fsl-mpc551x.h:3134
uSSCR
Definition: fsl-mpc551x.h:3588
uSFTCCSR
Definition: fsl-mpc551x.h:3069
uRFRFCFR
Definition: fsl-mpc551x.h:3202
uPCR28
Definition: fsl-mpc551x.h:3457
uSSSR
Definition: fsl-mpc551x.h:3123
EQADC_tag::EQADC_IDCR_tag
Definition: fsl-mpc555x.h:2465
DSPI_RSER_tag
Definition: fsl-mpc564xL.h:16627
PBRIDGE_A_tag
Definition: fsl-mpc555x.h:124
uPCR4
Definition: fsl-mpc551x.h:3261
uCYCTR
Definition: fsl-mpc551x.h:3546
EQADC_tag::EQADC_MCR_tag
Definition: fsl-mpc567x.h:4271
uPCR2
Definition: fsl-mpc551x.h:3244
uRFARIR
Definition: fsl-mpc551x.h:3597
uCASERCR
Definition: fsl-mpc551x.h:3540
SCR
#define SCR
Scratch register.
Definition: uart.h:94
EBI_CS_tag
Definition: fsl-mpc551x.h:447
FMPLL_tag
Definition: fsl-mpc551x.h:1484
uPSR2
Definition: fsl-mpc551x.h:3000
uPCR21
Definition: fsl-mpc551x.h:3401
uRFBRIR
Definition: fsl-mpc551x.h:3600
uPCR30
Definition: fsl-mpc551x.h:3473
DSPI_CTAR_tag
Definition: fsl-mpc564xL.h:16586
EQADC_tag::EQADC_ETDFR_tag
Definition: fsl-mpc567x.h:4294
uS_STSTUS
Definition: fsl-mpc551x.h:3741
uPCR7
Definition: fsl-mpc551x.h:3287
SIU_PCR_tag
Definition: fsl-mpc564xL.h:966
uMBIVEC
Definition: fsl-mpc551x.h:2960
uRFSIR
Definition: fsl-mpc551x.h:3594
uPCR24
Definition: fsl-mpc551x.h:3425
uMCR
Definition: fsl-mpc551x.h:2781
SWT_tag
Definition: fsl-mpc5668.h:6576
uPCR16
Definition: fsl-mpc551x.h:3362
uGIFER
Definition: fsl-mpc551x.h:2842
uRFMIAFMR
Definition: fsl-mpc551x.h:3606
FLEXCAN2_tag
Definition: fsl-mpc555x.h:2999
uPCR10
Definition: fsl-mpc551x.h:3313
uSSR
Definition: fsl-mpc551x.h:3150
uMTSCFR
Definition: fsl-mpc551x.h:3171
DECFIL_tag
Definition: fsl-mpc567x.h:4507
FR_tag
Definition: fsl-mpc551x.h:3622
uLDTXSLAR
Definition: fsl-mpc551x.h:3615
uPCR17
Definition: fsl-mpc551x.h:3370
uTI2CR0
Definition: fsl-mpc551x.h:3582
uPCR3
Definition: fsl-mpc551x.h:3252
DSPI_PUSHR_tag
Definition: fsl-mpc564xL.h:16678
EQADC_tag
Definition: fsl-mpc551x.h:716
uPCR1
Definition: fsl-mpc551x.h:3236
uPSR3
Definition: fsl-mpc551x.h:3018
uSLTCTBR
Definition: fsl-mpc551x.h:3555
uSYSBADLR
Definition: fsl-mpc551x.h:3531
uPSR1
Definition: fsl-mpc551x.h:2987
uPCR22
Definition: fsl-mpc551x.h:3409
BI
#define BI
Break Interrupt.
Definition: uart.h:127
uSTBPCR
Definition: fsl-mpc556x.h:3496
uSTBSCR
Definition: fsl-mpc551x.h:2796
ETPU_tag
Definition: fsl-mpc555x.h:1136
PMC_tag
Definition: fsl-mpc567x.h:2343
STM_tag
Definition: fsl-mpc5668.h:6467
uCHIERFR
Definition: fsl-mpc551x.h:2939
DSPI_SR_tag
Definition: fsl-mpc564xL.h:16605
DSPI_tag
Definition: fsl-mpc551x.h:244
uPCR29
Definition: fsl-mpc551x.h:3465
uMSG_BUFF_CCS
Definition: fsl-mpc551x.h:3481
uPCR13
Definition: fsl-mpc551x.h:3339
uMBDSR
Definition: fsl-mpc551x.h:2807
uSFTOR
Definition: fsl-mpc551x.h:3564
uPCR18
Definition: fsl-mpc551x.h:3377
DSPI_POPR_tag
Definition: fsl-mpc564xL.h:16698
uRFDSR
Definition: fsl-mpc551x.h:3193
uPCR6
Definition: fsl-mpc551x.h:3278
SIU_tag
Definition: fsl-mpc551x.h:2221
uSYSBADHR
Definition: fsl-mpc551x.h:3528
uPCR25
Definition: fsl-mpc551x.h:3434
uCIFRR
Definition: fsl-mpc551x.h:3037
EBI_tag
Definition: fsl-mpc551x.h:483
ECSM_tag
Definition: fsl-mpc555x.h:2179
uMTCTR
Definition: fsl-mpc551x.h:3549
uTI1CYSR
Definition: fsl-mpc551x.h:3112
uPCR11
Definition: fsl-mpc551x.h:3322
LCR
#define LCR
Line Control Register.
Definition: uart.h:90
uPCR9
Definition: fsl-mpc551x.h:3304
uNMVR
Definition: fsl-mpc551x.h:3573
uPCR14
Definition: fsl-mpc551x.h:3347
uTI2CR1
Definition: fsl-mpc551x.h:3585
uMBSSUTR
Definition: fsl-mpc551x.h:2817
uPDAR
Definition: fsl-mpc551x.h:3537
uPIFR0
Definition: fsl-mpc551x.h:2863
uPIER0
Definition: fsl-mpc551x.h:2901
uCBSERCR
Definition: fsl-mpc551x.h:3543
uPCR0
Definition: fsl-mpc551x.h:3228
uRFSR
Definition: fsl-mpc551x.h:3591
uPSR0
Definition: fsl-mpc551x.h:2971
uF_HEADER
Definition: fsl-mpc551x.h:3723
EQADC_tag::EQADC_NMSFR_tag
Definition: fsl-mpc567x.h:4286
uOFCORVR
Definition: fsl-mpc551x.h:3561
uT1MTOR
Definition: fsl-mpc551x.h:3579
FE
#define FE
Framing Error.
Definition: uart.h:126
PBRIDGE_B_tag
Definition: fsl-mpc555x.h:236
INTC_tag
Definition: fsl-mpc551x.h:1603
uPCR5
Definition: fsl-mpc551x.h:3269
uMVR
Definition: fsl-mpc551x.h:2773
RSR
#define RSR
rx status reg for rd
Definition: wd80x3.h:63
uPCR26
Definition: fsl-mpc551x.h:3441
uPOCR
Definition: fsl-mpc551x.h:2828
MCR
#define MCR
Modem Control Register.
Definition: uart.h:91
FLASH_tag
Definition: fsl-mpc551x.h:1027
uPCR20
Definition: fsl-mpc551x.h:3393
uPCR12
Definition: fsl-mpc551x.h:3331
DSPI_MCR_tag
Definition: fsl-mpc564xL.h:16541
MPU_tag
Definition: fsl-mpc551x.h:1843
EBI_CAL_CS_tag
Definition: fsl-mpc551x.h:479
uLDTXSLBR
Definition: fsl-mpc551x.h:3618
EQADC_tag::EQADC_CFPR_tag
Definition: fsl-mpc567x.h:4302
uSFIDRFR
Definition: fsl-mpc551x.h:3085
PIT_tag
Definition: fsl-mpc551x.h:1991
uMB_HEADER
Definition: fsl-mpc551x.h:3782
uPCR27
Definition: fsl-mpc551x.h:3450
uRTCORVR
Definition: fsl-mpc551x.h:3558
uSFCNTR
Definition: fsl-mpc551x.h:3059
uPCR19
Definition: fsl-mpc551x.h:3385
EMIOS_tag
Definition: fsl-mpc551x.h:531
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