|
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t GEC:1 |
| |
|
uint32_t __pad0__:3 |
| |
|
uint32_t MGE1:1 |
| |
|
uint32_t MGE2:1 |
| |
|
uint32_t ILF1:1 |
| |
|
uint32_t ILF2:1 |
| |
|
uint32_t __pad1__:3 |
| |
|
uint32_t SCMSIZE:5 |
| |
|
uint32_t __pad2__:5 |
| |
|
uint32_t SCMMISF:1 |
| |
|
uint32_t SCMMISEN:1 |
| |
|
uint32_t __pad3__:2 |
| |
|
uint32_t VIS:1 |
| |
|
uint32_t __pad4__:5 |
| |
|
uint32_t GTBE:1 |
| |
| } B |
| |
| } | MCR |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t STS:1 |
| |
|
uint32_t CTBASE:5 |
| |
|
uint32_t PBASE:10 |
| |
|
uint32_t PWIDTH:1 |
| |
|
uint32_t PARAM0:7 |
| |
|
uint32_t WR:1 |
| |
|
uint32_t PARAM1:7 |
| |
| } B |
| |
| } | CDCR |
| |
|
uint32_t | etpu_reserved1 |
| |
|
union { |
|
uint32_t R |
| |
| } | MISCCMPR |
| |
|
union { |
|
uint32_t R |
| |
| } | SCMOFFDATAR |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t FEND:1 |
| |
|
uint32_t MDIS:1 |
| |
|
uint32_t __pad0__:1 |
| |
|
uint32_t STF:1 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t HLTF:1 |
| |
|
uint32_t __pad2__:4 |
| |
|
uint32_t FPSCK:3 |
| |
|
uint32_t CDFC:2 |
| |
|
uint32_t __pad3__:9 |
| |
|
uint32_t ETB:5 |
| |
| } B |
| |
| } | ECR_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t FEND:1 |
| |
|
uint32_t MDIS:1 |
| |
|
uint32_t __pad0__:1 |
| |
|
uint32_t STF:1 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t HLTF:1 |
| |
|
uint32_t __pad2__:4 |
| |
|
uint32_t FPSCK:3 |
| |
|
uint32_t CDFC:2 |
| |
|
uint32_t __pad3__:9 |
| |
|
uint32_t ETB:5 |
| |
| } B |
| |
| } | ECR_B |
| |
|
uint32_t | etpu_reserved4 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t TCR2CTL:3 |
| |
|
uint32_t TCRCF:2 |
| |
|
uint32_t __pad0__:1 |
| |
|
uint32_t AM:1 |
| |
|
uint32_t __pad1__:3 |
| |
|
uint32_t TCR2P:6 |
| |
|
uint32_t TCR1CTL:2 |
| |
|
uint32_t __pad2__:6 |
| |
|
uint32_t TCR1P:8 |
| |
| } B |
| |
| } | TBCR_A |
| |
|
union { |
|
uint32_t R |
| |
| } | TB1R_A |
| |
|
union { |
|
uint32_t R |
| |
| } | TB2R_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t REN1:1 |
| |
|
uint32_t RSC1:1 |
| |
|
uint32_t __pad0__:2 |
| |
|
uint32_t SERVER_ID1:4 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t SRV1:4 |
| |
|
uint32_t REN2:1 |
| |
|
uint32_t RSC2:1 |
| |
|
uint32_t __pad2__:2 |
| |
|
uint32_t SERVER_ID2:4 |
| |
|
uint32_t __pad3__:4 |
| |
|
uint32_t SRV2:4 |
| |
| } B |
| |
| } | REDCR_A |
| |
|
uint32_t | etpu_reserved5 [4] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t TCR2CTL:3 |
| |
|
uint32_t TCRCF:2 |
| |
|
uint32_t __pad0__:1 |
| |
|
uint32_t AM:1 |
| |
|
uint32_t __pad1__:3 |
| |
|
uint32_t TCR2P:6 |
| |
|
uint32_t TCR1CTL:2 |
| |
|
uint32_t __pad2__:6 |
| |
|
uint32_t TCR1P:8 |
| |
| } B |
| |
| } | TBCR_B |
| |
|
union { |
|
uint32_t R |
| |
| } | TB1R_B |
| |
|
union { |
|
uint32_t R |
| |
| } | TB2R_B |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t REN1:1 |
| |
|
uint32_t RSC1:1 |
| |
|
uint32_t __pad0__:2 |
| |
|
uint32_t SERVER_ID1:4 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t SRV1:4 |
| |
|
uint32_t REN2:1 |
| |
|
uint32_t RSC2:1 |
| |
|
uint32_t __pad2__:2 |
| |
|
uint32_t SERVER_ID2:4 |
| |
|
uint32_t __pad3__:4 |
| |
|
uint32_t SRV2:4 |
| |
| } B |
| |
| } | REDCR_B |
| |
|
uint32_t | etpu_reserved7 [108] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIS31:1 |
| |
|
uint32_t CIS30:1 |
| |
|
uint32_t CIS29:1 |
| |
|
uint32_t CIS28:1 |
| |
|
uint32_t CIS27:1 |
| |
|
uint32_t CIS26:1 |
| |
|
uint32_t CIS25:1 |
| |
|
uint32_t CIS24:1 |
| |
|
uint32_t CIS23:1 |
| |
|
uint32_t CIS22:1 |
| |
|
uint32_t CIS21:1 |
| |
|
uint32_t CIS20:1 |
| |
|
uint32_t CIS19:1 |
| |
|
uint32_t CIS18:1 |
| |
|
uint32_t CIS17:1 |
| |
|
uint32_t CIS16:1 |
| |
|
uint32_t CIS15:1 |
| |
|
uint32_t CIS14:1 |
| |
|
uint32_t CIS13:1 |
| |
|
uint32_t CIS12:1 |
| |
|
uint32_t CIS11:1 |
| |
|
uint32_t CIS10:1 |
| |
|
uint32_t CIS9:1 |
| |
|
uint32_t CIS8:1 |
| |
|
uint32_t CIS7:1 |
| |
|
uint32_t CIS6:1 |
| |
|
uint32_t CIS5:1 |
| |
|
uint32_t CIS4:1 |
| |
|
uint32_t CIS3:1 |
| |
|
uint32_t CIS2:1 |
| |
|
uint32_t CIS1:1 |
| |
|
uint32_t CIS0:1 |
| |
| } B |
| |
| } | CISR_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIS31:1 |
| |
|
uint32_t CIS30:1 |
| |
|
uint32_t CIS29:1 |
| |
|
uint32_t CIS28:1 |
| |
|
uint32_t CIS27:1 |
| |
|
uint32_t CIS26:1 |
| |
|
uint32_t CIS25:1 |
| |
|
uint32_t CIS24:1 |
| |
|
uint32_t CIS23:1 |
| |
|
uint32_t CIS22:1 |
| |
|
uint32_t CIS21:1 |
| |
|
uint32_t CIS20:1 |
| |
|
uint32_t CIS19:1 |
| |
|
uint32_t CIS18:1 |
| |
|
uint32_t CIS17:1 |
| |
|
uint32_t CIS16:1 |
| |
|
uint32_t CIS15:1 |
| |
|
uint32_t CIS14:1 |
| |
|
uint32_t CIS13:1 |
| |
|
uint32_t CIS12:1 |
| |
|
uint32_t CIS11:1 |
| |
|
uint32_t CIS10:1 |
| |
|
uint32_t CIS9:1 |
| |
|
uint32_t CIS8:1 |
| |
|
uint32_t CIS7:1 |
| |
|
uint32_t CIS6:1 |
| |
|
uint32_t CIS5:1 |
| |
|
uint32_t CIS4:1 |
| |
|
uint32_t CIS3:1 |
| |
|
uint32_t CIS2:1 |
| |
|
uint32_t CIS1:1 |
| |
|
uint32_t CIS0:1 |
| |
| } B |
| |
| } | CISR_B |
| |
|
uint32_t | etpu_reserved9 [2] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t DTRS31:1 |
| |
|
uint32_t DTRS30:1 |
| |
|
uint32_t DTRS29:1 |
| |
|
uint32_t DTRS28:1 |
| |
|
uint32_t DTRS27:1 |
| |
|
uint32_t DTRS26:1 |
| |
|
uint32_t DTRS25:1 |
| |
|
uint32_t DTRS24:1 |
| |
|
uint32_t DTRS23:1 |
| |
|
uint32_t DTRS22:1 |
| |
|
uint32_t DTRS21:1 |
| |
|
uint32_t DTRS20:1 |
| |
|
uint32_t DTRS19:1 |
| |
|
uint32_t DTRS18:1 |
| |
|
uint32_t DTRS17:1 |
| |
|
uint32_t DTRS16:1 |
| |
|
uint32_t DTRS15:1 |
| |
|
uint32_t DTRS14:1 |
| |
|
uint32_t DTRS13:1 |
| |
|
uint32_t DTRS12:1 |
| |
|
uint32_t DTRS11:1 |
| |
|
uint32_t DTRS10:1 |
| |
|
uint32_t DTRS9:1 |
| |
|
uint32_t DTRS8:1 |
| |
|
uint32_t DTRS7:1 |
| |
|
uint32_t DTRS6:1 |
| |
|
uint32_t DTRS5:1 |
| |
|
uint32_t DTRS4:1 |
| |
|
uint32_t DTRS3:1 |
| |
|
uint32_t DTRS2:1 |
| |
|
uint32_t DTRS1:1 |
| |
|
uint32_t DTRS0:1 |
| |
| } B |
| |
| } | CDTRSR_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t DTRS31:1 |
| |
|
uint32_t DTRS30:1 |
| |
|
uint32_t DTRS29:1 |
| |
|
uint32_t DTRS28:1 |
| |
|
uint32_t DTRS27:1 |
| |
|
uint32_t DTRS26:1 |
| |
|
uint32_t DTRS25:1 |
| |
|
uint32_t DTRS24:1 |
| |
|
uint32_t DTRS23:1 |
| |
|
uint32_t DTRS22:1 |
| |
|
uint32_t DTRS21:1 |
| |
|
uint32_t DTRS20:1 |
| |
|
uint32_t DTRS19:1 |
| |
|
uint32_t DTRS18:1 |
| |
|
uint32_t DTRS17:1 |
| |
|
uint32_t DTRS16:1 |
| |
|
uint32_t DTRS15:1 |
| |
|
uint32_t DTRS14:1 |
| |
|
uint32_t DTRS13:1 |
| |
|
uint32_t DTRS12:1 |
| |
|
uint32_t DTRS11:1 |
| |
|
uint32_t DTRS10:1 |
| |
|
uint32_t DTRS9:1 |
| |
|
uint32_t DTRS8:1 |
| |
|
uint32_t DTRS7:1 |
| |
|
uint32_t DTRS6:1 |
| |
|
uint32_t DTRS5:1 |
| |
|
uint32_t DTRS4:1 |
| |
|
uint32_t DTRS3:1 |
| |
|
uint32_t DTRS2:1 |
| |
|
uint32_t DTRS1:1 |
| |
|
uint32_t DTRS0:1 |
| |
| } B |
| |
| } | CDTRSR_B |
| |
|
uint32_t | etpu_reserved11 [2] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIOS31:1 |
| |
|
uint32_t CIOS30:1 |
| |
|
uint32_t CIOS29:1 |
| |
|
uint32_t CIOS28:1 |
| |
|
uint32_t CIOS27:1 |
| |
|
uint32_t CIOS26:1 |
| |
|
uint32_t CIOS25:1 |
| |
|
uint32_t CIOS24:1 |
| |
|
uint32_t CIOS23:1 |
| |
|
uint32_t CIOS22:1 |
| |
|
uint32_t CIOS21:1 |
| |
|
uint32_t CIOS20:1 |
| |
|
uint32_t CIOS19:1 |
| |
|
uint32_t CIOS18:1 |
| |
|
uint32_t CIOS17:1 |
| |
|
uint32_t CIOS16:1 |
| |
|
uint32_t CIOS15:1 |
| |
|
uint32_t CIOS14:1 |
| |
|
uint32_t CIOS13:1 |
| |
|
uint32_t CIOS12:1 |
| |
|
uint32_t CIOS11:1 |
| |
|
uint32_t CIOS10:1 |
| |
|
uint32_t CIOS9:1 |
| |
|
uint32_t CIOS8:1 |
| |
|
uint32_t CIOS7:1 |
| |
|
uint32_t CIOS6:1 |
| |
|
uint32_t CIOS5:1 |
| |
|
uint32_t CIOS4:1 |
| |
|
uint32_t CIOS3:1 |
| |
|
uint32_t CIOS2:1 |
| |
|
uint32_t CIOS1:1 |
| |
|
uint32_t CIOS0:1 |
| |
| } B |
| |
| } | CIOSR_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIOS31:1 |
| |
|
uint32_t CIOS30:1 |
| |
|
uint32_t CIOS29:1 |
| |
|
uint32_t CIOS28:1 |
| |
|
uint32_t CIOS27:1 |
| |
|
uint32_t CIOS26:1 |
| |
|
uint32_t CIOS25:1 |
| |
|
uint32_t CIOS24:1 |
| |
|
uint32_t CIOS23:1 |
| |
|
uint32_t CIOS22:1 |
| |
|
uint32_t CIOS21:1 |
| |
|
uint32_t CIOS20:1 |
| |
|
uint32_t CIOS19:1 |
| |
|
uint32_t CIOS18:1 |
| |
|
uint32_t CIOS17:1 |
| |
|
uint32_t CIOS16:1 |
| |
|
uint32_t CIOS15:1 |
| |
|
uint32_t CIOS14:1 |
| |
|
uint32_t CIOS13:1 |
| |
|
uint32_t CIOS12:1 |
| |
|
uint32_t CIOS11:1 |
| |
|
uint32_t CIOS10:1 |
| |
|
uint32_t CIOS9:1 |
| |
|
uint32_t CIOS8:1 |
| |
|
uint32_t CIOS7:1 |
| |
|
uint32_t CIOS6:1 |
| |
|
uint32_t CIOS5:1 |
| |
|
uint32_t CIOS4:1 |
| |
|
uint32_t CIOS3:1 |
| |
|
uint32_t CIOS2:1 |
| |
|
uint32_t CIOS1:1 |
| |
|
uint32_t CIOS0:1 |
| |
| } B |
| |
| } | CIOSR_B |
| |
|
uint32_t | etpu_reserved13 [2] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t DTROS31:1 |
| |
|
uint32_t DTROS30:1 |
| |
|
uint32_t DTROS29:1 |
| |
|
uint32_t DTROS28:1 |
| |
|
uint32_t DTROS27:1 |
| |
|
uint32_t DTROS26:1 |
| |
|
uint32_t DTROS25:1 |
| |
|
uint32_t DTROS24:1 |
| |
|
uint32_t DTROS23:1 |
| |
|
uint32_t DTROS22:1 |
| |
|
uint32_t DTROS21:1 |
| |
|
uint32_t DTROS20:1 |
| |
|
uint32_t DTROS19:1 |
| |
|
uint32_t DTROS18:1 |
| |
|
uint32_t DTROS17:1 |
| |
|
uint32_t DTROS16:1 |
| |
|
uint32_t DTROS15:1 |
| |
|
uint32_t DTROS14:1 |
| |
|
uint32_t DTROS13:1 |
| |
|
uint32_t DTROS12:1 |
| |
|
uint32_t DTROS11:1 |
| |
|
uint32_t DTROS10:1 |
| |
|
uint32_t DTROS9:1 |
| |
|
uint32_t DTROS8:1 |
| |
|
uint32_t DTROS7:1 |
| |
|
uint32_t DTROS6:1 |
| |
|
uint32_t DTROS5:1 |
| |
|
uint32_t DTROS4:1 |
| |
|
uint32_t DTROS3:1 |
| |
|
uint32_t DTROS2:1 |
| |
|
uint32_t DTROS1:1 |
| |
|
uint32_t DTROS0:1 |
| |
| } B |
| |
| } | CDTROSR_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t DTROS31:1 |
| |
|
uint32_t DTROS30:1 |
| |
|
uint32_t DTROS29:1 |
| |
|
uint32_t DTROS28:1 |
| |
|
uint32_t DTROS27:1 |
| |
|
uint32_t DTROS26:1 |
| |
|
uint32_t DTROS25:1 |
| |
|
uint32_t DTROS24:1 |
| |
|
uint32_t DTROS23:1 |
| |
|
uint32_t DTROS22:1 |
| |
|
uint32_t DTROS21:1 |
| |
|
uint32_t DTROS20:1 |
| |
|
uint32_t DTROS19:1 |
| |
|
uint32_t DTROS18:1 |
| |
|
uint32_t DTROS17:1 |
| |
|
uint32_t DTROS16:1 |
| |
|
uint32_t DTROS15:1 |
| |
|
uint32_t DTROS14:1 |
| |
|
uint32_t DTROS13:1 |
| |
|
uint32_t DTROS12:1 |
| |
|
uint32_t DTROS11:1 |
| |
|
uint32_t DTROS10:1 |
| |
|
uint32_t DTROS9:1 |
| |
|
uint32_t DTROS8:1 |
| |
|
uint32_t DTROS7:1 |
| |
|
uint32_t DTROS6:1 |
| |
|
uint32_t DTROS5:1 |
| |
|
uint32_t DTROS4:1 |
| |
|
uint32_t DTROS3:1 |
| |
|
uint32_t DTROS2:1 |
| |
|
uint32_t DTROS1:1 |
| |
|
uint32_t DTROS0:1 |
| |
| } B |
| |
| } | CDTROSR_B |
| |
|
uint32_t | etpu_reserved15 [2] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIE31:1 |
| |
|
uint32_t CIE30:1 |
| |
|
uint32_t CIE29:1 |
| |
|
uint32_t CIE28:1 |
| |
|
uint32_t CIE27:1 |
| |
|
uint32_t CIE26:1 |
| |
|
uint32_t CIE25:1 |
| |
|
uint32_t CIE24:1 |
| |
|
uint32_t CIE23:1 |
| |
|
uint32_t CIE22:1 |
| |
|
uint32_t CIE21:1 |
| |
|
uint32_t CIE20:1 |
| |
|
uint32_t CIE19:1 |
| |
|
uint32_t CIE18:1 |
| |
|
uint32_t CIE17:1 |
| |
|
uint32_t CIE16:1 |
| |
|
uint32_t CIE15:1 |
| |
|
uint32_t CIE14:1 |
| |
|
uint32_t CIE13:1 |
| |
|
uint32_t CIE12:1 |
| |
|
uint32_t CIE11:1 |
| |
|
uint32_t CIE10:1 |
| |
|
uint32_t CIE9:1 |
| |
|
uint32_t CIE8:1 |
| |
|
uint32_t CIE7:1 |
| |
|
uint32_t CIE6:1 |
| |
|
uint32_t CIE5:1 |
| |
|
uint32_t CIE4:1 |
| |
|
uint32_t CIE3:1 |
| |
|
uint32_t CIE2:1 |
| |
|
uint32_t CIE1:1 |
| |
|
uint32_t CIE0:1 |
| |
| } B |
| |
| } | CIER_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIE31:1 |
| |
|
uint32_t CIE30:1 |
| |
|
uint32_t CIE29:1 |
| |
|
uint32_t CIE28:1 |
| |
|
uint32_t CIE27:1 |
| |
|
uint32_t CIE26:1 |
| |
|
uint32_t CIE25:1 |
| |
|
uint32_t CIE24:1 |
| |
|
uint32_t CIE23:1 |
| |
|
uint32_t CIE22:1 |
| |
|
uint32_t CIE21:1 |
| |
|
uint32_t CIE20:1 |
| |
|
uint32_t CIE19:1 |
| |
|
uint32_t CIE18:1 |
| |
|
uint32_t CIE17:1 |
| |
|
uint32_t CIE16:1 |
| |
|
uint32_t CIE15:1 |
| |
|
uint32_t CIE14:1 |
| |
|
uint32_t CIE13:1 |
| |
|
uint32_t CIE12:1 |
| |
|
uint32_t CIE11:1 |
| |
|
uint32_t CIE10:1 |
| |
|
uint32_t CIE9:1 |
| |
|
uint32_t CIE8:1 |
| |
|
uint32_t CIE7:1 |
| |
|
uint32_t CIE6:1 |
| |
|
uint32_t CIE5:1 |
| |
|
uint32_t CIE4:1 |
| |
|
uint32_t CIE3:1 |
| |
|
uint32_t CIE2:1 |
| |
|
uint32_t CIE1:1 |
| |
|
uint32_t CIE0:1 |
| |
| } B |
| |
| } | CIER_B |
| |
|
uint32_t | etpu_reserved17 [2] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t DTRE31:1 |
| |
|
uint32_t DTRE30:1 |
| |
|
uint32_t DTRE29:1 |
| |
|
uint32_t DTRE28:1 |
| |
|
uint32_t DTRE27:1 |
| |
|
uint32_t DTRE26:1 |
| |
|
uint32_t DTRE25:1 |
| |
|
uint32_t DTRE24:1 |
| |
|
uint32_t DTRE23:1 |
| |
|
uint32_t DTRE22:1 |
| |
|
uint32_t DTRE21:1 |
| |
|
uint32_t DTRE20:1 |
| |
|
uint32_t DTRE19:1 |
| |
|
uint32_t DTRE18:1 |
| |
|
uint32_t DTRE17:1 |
| |
|
uint32_t DTRE16:1 |
| |
|
uint32_t DTRE15:1 |
| |
|
uint32_t DTRE14:1 |
| |
|
uint32_t DTRE13:1 |
| |
|
uint32_t DTRE12:1 |
| |
|
uint32_t DTRE11:1 |
| |
|
uint32_t DTRE10:1 |
| |
|
uint32_t DTRE9:1 |
| |
|
uint32_t DTRE8:1 |
| |
|
uint32_t DTRE7:1 |
| |
|
uint32_t DTRE6:1 |
| |
|
uint32_t DTRE5:1 |
| |
|
uint32_t DTRE4:1 |
| |
|
uint32_t DTRE3:1 |
| |
|
uint32_t DTRE2:1 |
| |
|
uint32_t DTRE1:1 |
| |
|
uint32_t DTRE0:1 |
| |
| } B |
| |
| } | CDTRER_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t DTRE31:1 |
| |
|
uint32_t DTRE30:1 |
| |
|
uint32_t DTRE29:1 |
| |
|
uint32_t DTRE28:1 |
| |
|
uint32_t DTRE27:1 |
| |
|
uint32_t DTRE26:1 |
| |
|
uint32_t DTRE25:1 |
| |
|
uint32_t DTRE24:1 |
| |
|
uint32_t DTRE23:1 |
| |
|
uint32_t DTRE22:1 |
| |
|
uint32_t DTRE21:1 |
| |
|
uint32_t DTRE20:1 |
| |
|
uint32_t DTRE19:1 |
| |
|
uint32_t DTRE18:1 |
| |
|
uint32_t DTRE17:1 |
| |
|
uint32_t DTRE16:1 |
| |
|
uint32_t DTRE15:1 |
| |
|
uint32_t DTRE14:1 |
| |
|
uint32_t DTRE13:1 |
| |
|
uint32_t DTRE12:1 |
| |
|
uint32_t DTRE11:1 |
| |
|
uint32_t DTRE10:1 |
| |
|
uint32_t DTRE9:1 |
| |
|
uint32_t DTRE8:1 |
| |
|
uint32_t DTRE7:1 |
| |
|
uint32_t DTRE6:1 |
| |
|
uint32_t DTRE5:1 |
| |
|
uint32_t DTRE4:1 |
| |
|
uint32_t DTRE3:1 |
| |
|
uint32_t DTRE2:1 |
| |
|
uint32_t DTRE1:1 |
| |
|
uint32_t DTRE0:1 |
| |
| } B |
| |
| } | CDTRER_B |
| |
|
uint32_t | etpu_reserved20 [10] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t SR31:1 |
| |
|
uint32_t SR30:1 |
| |
|
uint32_t SR29:1 |
| |
|
uint32_t SR28:1 |
| |
|
uint32_t SR27:1 |
| |
|
uint32_t SR26:1 |
| |
|
uint32_t SR25:1 |
| |
|
uint32_t SR24:1 |
| |
|
uint32_t SR23:1 |
| |
|
uint32_t SR22:1 |
| |
|
uint32_t SR21:1 |
| |
|
uint32_t SR20:1 |
| |
|
uint32_t SR19:1 |
| |
|
uint32_t SR18:1 |
| |
|
uint32_t SR17:1 |
| |
|
uint32_t SR16:1 |
| |
|
uint32_t SR15:1 |
| |
|
uint32_t SR14:1 |
| |
|
uint32_t SR13:1 |
| |
|
uint32_t SR12:1 |
| |
|
uint32_t SR11:1 |
| |
|
uint32_t SR10:1 |
| |
|
uint32_t SR9:1 |
| |
|
uint32_t SR8:1 |
| |
|
uint32_t SR7:1 |
| |
|
uint32_t SR6:1 |
| |
|
uint32_t SR5:1 |
| |
|
uint32_t SR4:1 |
| |
|
uint32_t SR3:1 |
| |
|
uint32_t SR2:1 |
| |
|
uint32_t SR1:1 |
| |
|
uint32_t SR0:1 |
| |
| } B |
| |
| } | CPSSR_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t SR31:1 |
| |
|
uint32_t SR30:1 |
| |
|
uint32_t SR29:1 |
| |
|
uint32_t SR28:1 |
| |
|
uint32_t SR27:1 |
| |
|
uint32_t SR26:1 |
| |
|
uint32_t SR25:1 |
| |
|
uint32_t SR24:1 |
| |
|
uint32_t SR23:1 |
| |
|
uint32_t SR22:1 |
| |
|
uint32_t SR21:1 |
| |
|
uint32_t SR20:1 |
| |
|
uint32_t SR19:1 |
| |
|
uint32_t SR18:1 |
| |
|
uint32_t SR17:1 |
| |
|
uint32_t SR16:1 |
| |
|
uint32_t SR15:1 |
| |
|
uint32_t SR14:1 |
| |
|
uint32_t SR13:1 |
| |
|
uint32_t SR12:1 |
| |
|
uint32_t SR11:1 |
| |
|
uint32_t SR10:1 |
| |
|
uint32_t SR9:1 |
| |
|
uint32_t SR8:1 |
| |
|
uint32_t SR7:1 |
| |
|
uint32_t SR6:1 |
| |
|
uint32_t SR5:1 |
| |
|
uint32_t SR4:1 |
| |
|
uint32_t SR3:1 |
| |
|
uint32_t SR2:1 |
| |
|
uint32_t SR1:1 |
| |
|
uint32_t SR0:1 |
| |
| } B |
| |
| } | CPSSR_B |
| |
|
uint32_t | etpu_reserved20a [2] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t SS31:1 |
| |
|
uint32_t SS30:1 |
| |
|
uint32_t SS29:1 |
| |
|
uint32_t SS28:1 |
| |
|
uint32_t SS27:1 |
| |
|
uint32_t SS26:1 |
| |
|
uint32_t SS25:1 |
| |
|
uint32_t SS24:1 |
| |
|
uint32_t SS23:1 |
| |
|
uint32_t SS22:1 |
| |
|
uint32_t SS21:1 |
| |
|
uint32_t SS20:1 |
| |
|
uint32_t SS19:1 |
| |
|
uint32_t SS18:1 |
| |
|
uint32_t SS17:1 |
| |
|
uint32_t SS16:1 |
| |
|
uint32_t SS15:1 |
| |
|
uint32_t SS14:1 |
| |
|
uint32_t SS13:1 |
| |
|
uint32_t SS12:1 |
| |
|
uint32_t SS11:1 |
| |
|
uint32_t SS10:1 |
| |
|
uint32_t SS9:1 |
| |
|
uint32_t SS8:1 |
| |
|
uint32_t SS7:1 |
| |
|
uint32_t SS6:1 |
| |
|
uint32_t SS5:1 |
| |
|
uint32_t SS4:1 |
| |
|
uint32_t SS3:1 |
| |
|
uint32_t SS2:1 |
| |
|
uint32_t SS1:1 |
| |
|
uint32_t SS0:1 |
| |
| } B |
| |
| } | CSSR_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t SS31:1 |
| |
|
uint32_t SS30:1 |
| |
|
uint32_t SS29:1 |
| |
|
uint32_t SS28:1 |
| |
|
uint32_t SS27:1 |
| |
|
uint32_t SS26:1 |
| |
|
uint32_t SS25:1 |
| |
|
uint32_t SS24:1 |
| |
|
uint32_t SS23:1 |
| |
|
uint32_t SS22:1 |
| |
|
uint32_t SS21:1 |
| |
|
uint32_t SS20:1 |
| |
|
uint32_t SS19:1 |
| |
|
uint32_t SS18:1 |
| |
|
uint32_t SS17:1 |
| |
|
uint32_t SS16:1 |
| |
|
uint32_t SS15:1 |
| |
|
uint32_t SS14:1 |
| |
|
uint32_t SS13:1 |
| |
|
uint32_t SS12:1 |
| |
|
uint32_t SS11:1 |
| |
|
uint32_t SS10:1 |
| |
|
uint32_t SS9:1 |
| |
|
uint32_t SS8:1 |
| |
|
uint32_t SS7:1 |
| |
|
uint32_t SS6:1 |
| |
|
uint32_t SS5:1 |
| |
|
uint32_t SS4:1 |
| |
|
uint32_t SS3:1 |
| |
|
uint32_t SS2:1 |
| |
|
uint32_t SS1:1 |
| |
|
uint32_t SS0:1 |
| |
| } B |
| |
| } | CSSR_B |
| |
|
uint32_t | etpu_reserved23 [90] |
| |
|
struct { |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIE:1 |
| |
|
uint32_t DTRE:1 |
| |
|
uint32_t CPR:2 |
| |
|
uint32_t __pad0__:3 |
| |
|
uint32_t ETCS:1 |
| |
|
uint32_t __pad1__:3 |
| |
|
uint32_t CFS:5 |
| |
|
uint32_t ODIS:1 |
| |
|
uint32_t OPOL:1 |
| |
|
uint32_t __pad2__:3 |
| |
|
uint32_t CPBA:11 |
| |
| } B |
| |
| } CR |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIS:1 |
| |
|
uint32_t CIOS:1 |
| |
|
uint32_t __pad0__:6 |
| |
|
uint32_t DTRS:1 |
| |
|
uint32_t DTROS:1 |
| |
|
uint32_t __pad1__:6 |
| |
|
uint32_t IPS:1 |
| |
|
uint32_t OPS:1 |
| |
|
uint32_t OBE:1 |
| |
|
uint32_t __pad2__:11 |
| |
|
uint32_t FM1:1 |
| |
|
uint32_t FM0:1 |
| |
| } B |
| |
| } SCR |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t __pad0__:29 |
| |
|
uint32_t HSR:3 |
| |
| } B |
| |
| } HSRR |
| |
|
uint32_t etpu_reserved23 |
| |
| } | CHAN [127] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t GEC:1 |
| |
|
uint32_t __pad0__:3 |
| |
|
uint32_t MGE1:1 |
| |
|
uint32_t __pad1__:1 |
| |
|
uint32_t ILF1:1 |
| |
|
uint32_t __pad2__:1 |
| |
|
uint32_t __pad3__:3 |
| |
|
uint32_t SCMSIZE:5 |
| |
|
uint32_t __pad4__:5 |
| |
|
uint32_t SCMMISF:1 |
| |
|
uint32_t SCMMISEN:1 |
| |
|
uint32_t __pad5__:2 |
| |
|
uint32_t VIS:1 |
| |
|
uint32_t __pad6__:5 |
| |
|
uint32_t GTBE:1 |
| |
| } B |
| |
| } | MCR |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t STS:1 |
| |
|
uint32_t CTBASE:5 |
| |
|
uint32_t PBASE:10 |
| |
|
uint32_t PWIDTH:1 |
| |
|
uint32_t PARAM0:7 |
| |
|
uint32_t WR:1 |
| |
|
uint32_t PARAM1:7 |
| |
| } B |
| |
| } | CDCR |
| |
|
union { |
|
uint32_t R |
| |
| } | MISCCMPR |
| |
|
union { |
|
uint32_t R |
| |
| } | SCMOFFDATAR |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t FEND:1 |
| |
|
uint32_t MDIS:1 |
| |
|
uint32_t __pad0__:1 |
| |
|
uint32_t STF:1 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t HLTF:1 |
| |
|
uint32_t __pad2__:4 |
| |
|
uint32_t FPSCK:3 |
| |
|
uint32_t CDFC:2 |
| |
|
uint32_t __pad3__:9 |
| |
|
uint32_t ETB:5 |
| |
| } B |
| |
| } | ECR_A |
| |
|
uint32_t | etpu_reserved3 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t TCR2CTL:3 |
| |
|
uint32_t TCRCF:2 |
| |
|
uint32_t __pad0__:1 |
| |
|
uint32_t AM:1 |
| |
|
uint32_t __pad1__:3 |
| |
|
uint32_t TCR2P:6 |
| |
|
uint32_t TCR1CTL:2 |
| |
|
uint32_t __pad2__:6 |
| |
|
uint32_t TCR1P:8 |
| |
| } B |
| |
| } | TBCR_A |
| |
|
union { |
|
uint32_t R |
| |
| } | TB1R_A |
| |
|
union { |
|
uint32_t R |
| |
| } | TB2R_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t REN1:1 |
| |
|
uint32_t RSC1:1 |
| |
|
uint32_t __pad0__:2 |
| |
|
uint32_t SERVER_ID1:4 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t SRV1:4 |
| |
|
uint32_t REN2:1 |
| |
|
uint32_t RSC2:1 |
| |
|
uint32_t __pad2__:2 |
| |
|
uint32_t SERVER_ID2:4 |
| |
|
uint32_t __pad3__:4 |
| |
|
uint32_t SRV2:4 |
| |
| } B |
| |
| } | REDCR_A |
| |
|
uint32_t | etpu_reserved6 [4] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIS31:1 |
| |
|
uint32_t CIS30:1 |
| |
|
uint32_t CIS29:1 |
| |
|
uint32_t CIS28:1 |
| |
|
uint32_t CIS27:1 |
| |
|
uint32_t CIS26:1 |
| |
|
uint32_t CIS25:1 |
| |
|
uint32_t CIS24:1 |
| |
|
uint32_t CIS23:1 |
| |
|
uint32_t CIS22:1 |
| |
|
uint32_t CIS21:1 |
| |
|
uint32_t CIS20:1 |
| |
|
uint32_t CIS19:1 |
| |
|
uint32_t CIS18:1 |
| |
|
uint32_t CIS17:1 |
| |
|
uint32_t CIS16:1 |
| |
|
uint32_t CIS15:1 |
| |
|
uint32_t CIS14:1 |
| |
|
uint32_t CIS13:1 |
| |
|
uint32_t CIS12:1 |
| |
|
uint32_t CIS11:1 |
| |
|
uint32_t CIS10:1 |
| |
|
uint32_t CIS9:1 |
| |
|
uint32_t CIS8:1 |
| |
|
uint32_t CIS7:1 |
| |
|
uint32_t CIS6:1 |
| |
|
uint32_t CIS5:1 |
| |
|
uint32_t CIS4:1 |
| |
|
uint32_t CIS3:1 |
| |
|
uint32_t CIS2:1 |
| |
|
uint32_t CIS1:1 |
| |
|
uint32_t CIS0:1 |
| |
| } B |
| |
| } | CISR_A |
| |
|
uint32_t | etpu_reserved8 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t DTRS31:1 |
| |
|
uint32_t DTRS30:1 |
| |
|
uint32_t DTRS29:1 |
| |
|
uint32_t DTRS28:1 |
| |
|
uint32_t DTRS27:1 |
| |
|
uint32_t DTRS26:1 |
| |
|
uint32_t DTRS25:1 |
| |
|
uint32_t DTRS24:1 |
| |
|
uint32_t DTRS23:1 |
| |
|
uint32_t DTRS22:1 |
| |
|
uint32_t DTRS21:1 |
| |
|
uint32_t DTRS20:1 |
| |
|
uint32_t DTRS19:1 |
| |
|
uint32_t DTRS18:1 |
| |
|
uint32_t DTRS17:1 |
| |
|
uint32_t DTRS16:1 |
| |
|
uint32_t DTRS15:1 |
| |
|
uint32_t DTRS14:1 |
| |
|
uint32_t DTRS13:1 |
| |
|
uint32_t DTRS12:1 |
| |
|
uint32_t DTRS11:1 |
| |
|
uint32_t DTRS10:1 |
| |
|
uint32_t DTRS9:1 |
| |
|
uint32_t DTRS8:1 |
| |
|
uint32_t DTRS7:1 |
| |
|
uint32_t DTRS6:1 |
| |
|
uint32_t DTRS5:1 |
| |
|
uint32_t DTRS4:1 |
| |
|
uint32_t DTRS3:1 |
| |
|
uint32_t DTRS2:1 |
| |
|
uint32_t DTRS1:1 |
| |
|
uint32_t DTRS0:1 |
| |
| } B |
| |
| } | CDTRSR_A |
| |
|
uint32_t | etpu_reserved10 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIOS31:1 |
| |
|
uint32_t CIOS30:1 |
| |
|
uint32_t CIOS29:1 |
| |
|
uint32_t CIOS28:1 |
| |
|
uint32_t CIOS27:1 |
| |
|
uint32_t CIOS26:1 |
| |
|
uint32_t CIOS25:1 |
| |
|
uint32_t CIOS24:1 |
| |
|
uint32_t CIOS23:1 |
| |
|
uint32_t CIOS22:1 |
| |
|
uint32_t CIOS21:1 |
| |
|
uint32_t CIOS20:1 |
| |
|
uint32_t CIOS19:1 |
| |
|
uint32_t CIOS18:1 |
| |
|
uint32_t CIOS17:1 |
| |
|
uint32_t CIOS16:1 |
| |
|
uint32_t CIOS15:1 |
| |
|
uint32_t CIOS14:1 |
| |
|
uint32_t CIOS13:1 |
| |
|
uint32_t CIOS12:1 |
| |
|
uint32_t CIOS11:1 |
| |
|
uint32_t CIOS10:1 |
| |
|
uint32_t CIOS9:1 |
| |
|
uint32_t CIOS8:1 |
| |
|
uint32_t CIOS7:1 |
| |
|
uint32_t CIOS6:1 |
| |
|
uint32_t CIOS5:1 |
| |
|
uint32_t CIOS4:1 |
| |
|
uint32_t CIOS3:1 |
| |
|
uint32_t CIOS2:1 |
| |
|
uint32_t CIOS1:1 |
| |
|
uint32_t CIOS0:1 |
| |
| } B |
| |
| } | CIOSR_A |
| |
|
uint32_t | etpu_reserved12 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t DTROS31:1 |
| |
|
uint32_t DTROS30:1 |
| |
|
uint32_t DTROS29:1 |
| |
|
uint32_t DTROS28:1 |
| |
|
uint32_t DTROS27:1 |
| |
|
uint32_t DTROS26:1 |
| |
|
uint32_t DTROS25:1 |
| |
|
uint32_t DTROS24:1 |
| |
|
uint32_t DTROS23:1 |
| |
|
uint32_t DTROS22:1 |
| |
|
uint32_t DTROS21:1 |
| |
|
uint32_t DTROS20:1 |
| |
|
uint32_t DTROS19:1 |
| |
|
uint32_t DTROS18:1 |
| |
|
uint32_t DTROS17:1 |
| |
|
uint32_t DTROS16:1 |
| |
|
uint32_t DTROS15:1 |
| |
|
uint32_t DTROS14:1 |
| |
|
uint32_t DTROS13:1 |
| |
|
uint32_t DTROS12:1 |
| |
|
uint32_t DTROS11:1 |
| |
|
uint32_t DTROS10:1 |
| |
|
uint32_t DTROS9:1 |
| |
|
uint32_t DTROS8:1 |
| |
|
uint32_t DTROS7:1 |
| |
|
uint32_t DTROS6:1 |
| |
|
uint32_t DTROS5:1 |
| |
|
uint32_t DTROS4:1 |
| |
|
uint32_t DTROS3:1 |
| |
|
uint32_t DTROS2:1 |
| |
|
uint32_t DTROS1:1 |
| |
|
uint32_t DTROS0:1 |
| |
| } B |
| |
| } | CDTROSR_A |
| |
|
uint32_t | etpu_reserved14 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIE31:1 |
| |
|
uint32_t CIE30:1 |
| |
|
uint32_t CIE29:1 |
| |
|
uint32_t CIE28:1 |
| |
|
uint32_t CIE27:1 |
| |
|
uint32_t CIE26:1 |
| |
|
uint32_t CIE25:1 |
| |
|
uint32_t CIE24:1 |
| |
|
uint32_t CIE23:1 |
| |
|
uint32_t CIE22:1 |
| |
|
uint32_t CIE21:1 |
| |
|
uint32_t CIE20:1 |
| |
|
uint32_t CIE19:1 |
| |
|
uint32_t CIE18:1 |
| |
|
uint32_t CIE17:1 |
| |
|
uint32_t CIE16:1 |
| |
|
uint32_t CIE15:1 |
| |
|
uint32_t CIE14:1 |
| |
|
uint32_t CIE13:1 |
| |
|
uint32_t CIE12:1 |
| |
|
uint32_t CIE11:1 |
| |
|
uint32_t CIE10:1 |
| |
|
uint32_t CIE9:1 |
| |
|
uint32_t CIE8:1 |
| |
|
uint32_t CIE7:1 |
| |
|
uint32_t CIE6:1 |
| |
|
uint32_t CIE5:1 |
| |
|
uint32_t CIE4:1 |
| |
|
uint32_t CIE3:1 |
| |
|
uint32_t CIE2:1 |
| |
|
uint32_t CIE1:1 |
| |
|
uint32_t CIE0:1 |
| |
| } B |
| |
| } | CIER_A |
| |
|
uint32_t | etpu_reserved16 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t DTRE31:1 |
| |
|
uint32_t DTRE30:1 |
| |
|
uint32_t DTRE29:1 |
| |
|
uint32_t DTRE28:1 |
| |
|
uint32_t DTRE27:1 |
| |
|
uint32_t DTRE26:1 |
| |
|
uint32_t DTRE25:1 |
| |
|
uint32_t DTRE24:1 |
| |
|
uint32_t DTRE23:1 |
| |
|
uint32_t DTRE22:1 |
| |
|
uint32_t DTRE21:1 |
| |
|
uint32_t DTRE20:1 |
| |
|
uint32_t DTRE19:1 |
| |
|
uint32_t DTRE18:1 |
| |
|
uint32_t DTRE17:1 |
| |
|
uint32_t DTRE16:1 |
| |
|
uint32_t DTRE15:1 |
| |
|
uint32_t DTRE14:1 |
| |
|
uint32_t DTRE13:1 |
| |
|
uint32_t DTRE12:1 |
| |
|
uint32_t DTRE11:1 |
| |
|
uint32_t DTRE10:1 |
| |
|
uint32_t DTRE9:1 |
| |
|
uint32_t DTRE8:1 |
| |
|
uint32_t DTRE7:1 |
| |
|
uint32_t DTRE6:1 |
| |
|
uint32_t DTRE5:1 |
| |
|
uint32_t DTRE4:1 |
| |
|
uint32_t DTRE3:1 |
| |
|
uint32_t DTRE2:1 |
| |
|
uint32_t DTRE1:1 |
| |
|
uint32_t DTRE0:1 |
| |
| } B |
| |
| } | CDTRER_A |
| |
|
uint32_t | etpu_reserved19 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t SR31:1 |
| |
|
uint32_t SR30:1 |
| |
|
uint32_t SR29:1 |
| |
|
uint32_t SR28:1 |
| |
|
uint32_t SR27:1 |
| |
|
uint32_t SR26:1 |
| |
|
uint32_t SR25:1 |
| |
|
uint32_t SR24:1 |
| |
|
uint32_t SR23:1 |
| |
|
uint32_t SR22:1 |
| |
|
uint32_t SR21:1 |
| |
|
uint32_t SR20:1 |
| |
|
uint32_t SR19:1 |
| |
|
uint32_t SR18:1 |
| |
|
uint32_t SR17:1 |
| |
|
uint32_t SR16:1 |
| |
|
uint32_t SR15:1 |
| |
|
uint32_t SR14:1 |
| |
|
uint32_t SR13:1 |
| |
|
uint32_t SR12:1 |
| |
|
uint32_t SR11:1 |
| |
|
uint32_t SR10:1 |
| |
|
uint32_t SR9:1 |
| |
|
uint32_t SR8:1 |
| |
|
uint32_t SR7:1 |
| |
|
uint32_t SR6:1 |
| |
|
uint32_t SR5:1 |
| |
|
uint32_t SR4:1 |
| |
|
uint32_t SR3:1 |
| |
|
uint32_t SR2:1 |
| |
|
uint32_t SR1:1 |
| |
|
uint32_t SR0:1 |
| |
| } B |
| |
| } | CPSSR_A |
| |
|
uint32_t | etpu_reserved22 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t SS31:1 |
| |
|
uint32_t SS30:1 |
| |
|
uint32_t SS29:1 |
| |
|
uint32_t SS28:1 |
| |
|
uint32_t SS27:1 |
| |
|
uint32_t SS26:1 |
| |
|
uint32_t SS25:1 |
| |
|
uint32_t SS24:1 |
| |
|
uint32_t SS23:1 |
| |
|
uint32_t SS22:1 |
| |
|
uint32_t SS21:1 |
| |
|
uint32_t SS20:1 |
| |
|
uint32_t SS19:1 |
| |
|
uint32_t SS18:1 |
| |
|
uint32_t SS17:1 |
| |
|
uint32_t SS16:1 |
| |
|
uint32_t SS15:1 |
| |
|
uint32_t SS14:1 |
| |
|
uint32_t SS13:1 |
| |
|
uint32_t SS12:1 |
| |
|
uint32_t SS11:1 |
| |
|
uint32_t SS10:1 |
| |
|
uint32_t SS9:1 |
| |
|
uint32_t SS8:1 |
| |
|
uint32_t SS7:1 |
| |
|
uint32_t SS6:1 |
| |
|
uint32_t SS5:1 |
| |
|
uint32_t SS4:1 |
| |
|
uint32_t SS3:1 |
| |
|
uint32_t SS2:1 |
| |
|
uint32_t SS1:1 |
| |
|
uint32_t SS0:1 |
| |
| } B |
| |
| } | CSSR_A |
| |
|
uint32_t | etpu_reserved22a |
| |
|
struct { |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIE:1 |
| |
|
uint32_t DTRE:1 |
| |
|
uint32_t CPR:2 |
| |
|
uint32_t __pad0__:3 |
| |
|
uint32_t ETCS:1 |
| |
|
uint32_t __pad1__:3 |
| |
|
uint32_t CFS:5 |
| |
|
uint32_t ODIS:1 |
| |
|
uint32_t OPOL:1 |
| |
|
uint32_t __pad2__:3 |
| |
|
uint32_t CPBA:11 |
| |
| } B |
| |
| } CR |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIS:1 |
| |
|
uint32_t CIOS:1 |
| |
|
uint32_t __pad0__:6 |
| |
|
uint32_t DTRS:1 |
| |
|
uint32_t DTROS:1 |
| |
|
uint32_t __pad1__:6 |
| |
|
uint32_t IPS:1 |
| |
|
uint32_t OPS:1 |
| |
|
uint32_t OBE:1 |
| |
|
uint32_t __pad2__:11 |
| |
|
uint32_t FM1:1 |
| |
|
uint32_t FM0:1 |
| |
| } B |
| |
| } SCR |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t __pad0__:29 |
| |
|
uint32_t HSR:3 |
| |
| } B |
| |
| } HSRR |
| |
|
uint32_t etpu_reserved23 |
| |
| } | CHAN [127] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t GEC:1 |
| |
|
uint32_t SDMERR:1 |
| |
|
uint32_t WDTOA:1 |
| |
|
uint32_t WDTOB:1 |
| |
|
uint32_t MGE1:1 |
| |
|
uint32_t MGE2:1 |
| |
|
uint32_t ILF1:1 |
| |
|
uint32_t ILF2:1 |
| |
|
uint32_t __pad0__:3 |
| |
|
uint32_t SCMSIZE:5 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t SCMMISC:1 |
| |
|
uint32_t SCMMISF:1 |
| |
|
uint32_t SCMMISEN:1 |
| |
|
uint32_t __pad2__:2 |
| |
|
uint32_t VIS:1 |
| |
|
uint32_t __pad3__:5 |
| |
|
uint32_t GTBE:1 |
| |
| } B |
| |
| } | MCR |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t STS:1 |
| |
|
uint32_t CTBASE:5 |
| |
|
uint32_t PBASE:10 |
| |
|
uint32_t PWIDTH:1 |
| |
|
uint32_t PARAM0:7 |
| |
|
uint32_t WR:1 |
| |
|
uint32_t PARAM1:7 |
| |
| } B |
| |
| } | CDCR |
| |
|
uint32_t | eTPU_reserved0008 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t ETPUMISCCMP:32 |
| |
| } B |
| |
| } | MISCCMPR |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t ETPUSCMOFFDATA:32 |
| |
| } B |
| |
| } | SCMOFFDATAR |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t FEND:1 |
| |
|
uint32_t MDIS:1 |
| |
|
uint32_t __pad0__:1 |
| |
|
uint32_t STF:1 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t HLTF:1 |
| |
|
uint32_t __pad2__:3 |
| |
|
uint32_t FCSS:1 |
| |
|
uint32_t FPSCK:3 |
| |
|
uint32_t CDFC:2 |
| |
|
uint32_t __pad3__:1 |
| |
|
uint32_t ERBA:5 |
| |
|
uint32_t SPPDIS:1 |
| |
|
uint32_t __pad4__:2 |
| |
|
uint32_t ETB:5 |
| |
| } B |
| |
| } | ECR_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t FEND:1 |
| |
|
uint32_t MDIS:1 |
| |
|
uint32_t __pad0__:1 |
| |
|
uint32_t STF:1 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t HLTF:1 |
| |
|
uint32_t __pad2__:3 |
| |
|
uint32_t FCSS:1 |
| |
|
uint32_t FPSCK:3 |
| |
|
uint32_t CDFC:2 |
| |
|
uint32_t __pad3__:1 |
| |
|
uint32_t ERBA:5 |
| |
|
uint32_t SPPDIS:1 |
| |
|
uint32_t __pad4__:2 |
| |
|
uint32_t ETB:5 |
| |
| } B |
| |
| } | ECR_B |
| |
|
uint32_t | eTPU_reserved001C |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t TCR2CTL:3 |
| |
|
uint32_t TCRCF:2 |
| |
|
uint32_t AM:2 |
| |
|
uint32_t __pad0__:3 |
| |
|
uint32_t TCR2P:6 |
| |
|
uint32_t TCR1CTL:2 |
| |
|
uint32_t TCR1CS:1 |
| |
|
uint32_t __pad1__:5 |
| |
|
uint32_t TCR1P:8 |
| |
| } B |
| |
| } | TBCR_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t __pad0__:8 |
| |
|
uint32_t TCR1:24 |
| |
| } B |
| |
| } | TB1R_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t __pad0__:8 |
| |
|
uint32_t TCR2:24 |
| |
| } B |
| |
| } | TB2R_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t REN1:1 |
| |
|
uint32_t RSC1:1 |
| |
|
uint32_t __pad0__:2 |
| |
|
uint32_t SERVER_ID1:4 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t SRV1:4 |
| |
|
uint32_t REN2:1 |
| |
|
uint32_t RSC2:1 |
| |
|
uint32_t __pad2__:2 |
| |
|
uint32_t SERVER_ID2:4 |
| |
|
uint32_t __pad3__:4 |
| |
|
uint32_t SRV2:4 |
| |
| } B |
| |
| } | REDCR_A |
| |
|
uint32_t | eTPU_reserved0030 [4] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t TCR2CTL:3 |
| |
|
uint32_t TCRCF:2 |
| |
|
uint32_t AM:2 |
| |
|
uint32_t __pad0__:3 |
| |
|
uint32_t TCR2P:6 |
| |
|
uint32_t TCR1CTL:2 |
| |
|
uint32_t TCR1CS:1 |
| |
|
uint32_t __pad1__:5 |
| |
|
uint32_t TCR1P:8 |
| |
| } B |
| |
| } | TBCR_B |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t __pad0__:8 |
| |
|
uint32_t TCR1:24 |
| |
| } B |
| |
| } | TB1R_B |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t __pad0__:8 |
| |
|
uint32_t TCR2:24 |
| |
| } B |
| |
| } | TB2R_B |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t REN1:1 |
| |
|
uint32_t RSC1:1 |
| |
|
uint32_t __pad0__:2 |
| |
|
uint32_t SERVER_ID1:4 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t SRV1:4 |
| |
|
uint32_t REN2:1 |
| |
|
uint32_t RSC2:1 |
| |
|
uint32_t __pad2__:2 |
| |
|
uint32_t SERVER_ID2:4 |
| |
|
uint32_t __pad3__:4 |
| |
|
uint32_t SRV2:4 |
| |
| } B |
| |
| } | REDCR_B |
| |
|
uint32_t | eTPU_reserved0050 [4] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t WDM:2 |
| |
|
uint32_t __pad0__:14 |
| |
|
uint32_t WDCNT:16 |
| |
| } B |
| |
| } | WDTR_A |
| |
|
uint32_t | eTPU_reserved0064 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t IDLE_CNT:31 |
| |
|
uint32_t ICLR:1 |
| |
| } B |
| |
| } | IDLE_A |
| |
|
uint32_t | eTPU_reserved006C |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t WDM:2 |
| |
|
uint32_t __pad0__:14 |
| |
|
uint32_t WDCNT:16 |
| |
| } B |
| |
| } | WDTR_B |
| |
|
uint32_t | eTPU_reserved0074 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t IDLE_CNT:31 |
| |
|
uint32_t ICLR:1 |
| |
| } B |
| |
| } | IDLE_B |
| |
|
uint32_t | eTPU_reserved007C |
| |
|
uint32_t | eTPU_reserved0080 [96] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIS31:1 |
| |
|
uint32_t CIS30:1 |
| |
|
uint32_t CIS29:1 |
| |
|
uint32_t CIS28:1 |
| |
|
uint32_t CIS27:1 |
| |
|
uint32_t CIS26:1 |
| |
|
uint32_t CIS25:1 |
| |
|
uint32_t CIS24:1 |
| |
|
uint32_t CIS23:1 |
| |
|
uint32_t CIS22:1 |
| |
|
uint32_t CIS21:1 |
| |
|
uint32_t CIS20:1 |
| |
|
uint32_t CIS19:1 |
| |
|
uint32_t CIS18:1 |
| |
|
uint32_t CIS17:1 |
| |
|
uint32_t CIS16:1 |
| |
|
uint32_t CIS15:1 |
| |
|
uint32_t CIS14:1 |
| |
|
uint32_t CIS13:1 |
| |
|
uint32_t CIS12:1 |
| |
|
uint32_t CIS11:1 |
| |
|
uint32_t CIS10:1 |
| |
|
uint32_t CIS9:1 |
| |
|
uint32_t CIS8:1 |
| |
|
uint32_t CIS7:1 |
| |
|
uint32_t CIS6:1 |
| |
|
uint32_t CIS5:1 |
| |
|
uint32_t CIS4:1 |
| |
|
uint32_t CIS3:1 |
| |
|
uint32_t CIS2:1 |
| |
|
uint32_t CIS1:1 |
| |
|
uint32_t CIS0:1 |
| |
| } B |
| |
| } | CISR_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIS31:1 |
| |
|
uint32_t CIS30:1 |
| |
|
uint32_t CIS29:1 |
| |
|
uint32_t CIS28:1 |
| |
|
uint32_t CIS27:1 |
| |
|
uint32_t CIS26:1 |
| |
|
uint32_t CIS25:1 |
| |
|
uint32_t CIS24:1 |
| |
|
uint32_t CIS23:1 |
| |
|
uint32_t CIS22:1 |
| |
|
uint32_t CIS21:1 |
| |
|
uint32_t CIS20:1 |
| |
|
uint32_t CIS19:1 |
| |
|
uint32_t CIS18:1 |
| |
|
uint32_t CIS17:1 |
| |
|
uint32_t CIS16:1 |
| |
|
uint32_t CIS15:1 |
| |
|
uint32_t CIS14:1 |
| |
|
uint32_t CIS13:1 |
| |
|
uint32_t CIS12:1 |
| |
|
uint32_t CIS11:1 |
| |
|
uint32_t CIS10:1 |
| |
|
uint32_t CIS9:1 |
| |
|
uint32_t CIS8:1 |
| |
|
uint32_t CIS7:1 |
| |
|
uint32_t CIS6:1 |
| |
|
uint32_t CIS5:1 |
| |
|
uint32_t CIS4:1 |
| |
|
uint32_t CIS3:1 |
| |
|
uint32_t CIS2:1 |
| |
|
uint32_t CIS1:1 |
| |
|
uint32_t CIS0:1 |
| |
| } B |
| |
| } | CISR_B |
| |
|
uint32_t | eTPU_reserved0208 [2] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t DTRS31:1 |
| |
|
uint32_t DTRS30:1 |
| |
|
uint32_t DTRS29:1 |
| |
|
uint32_t DTRS28:1 |
| |
|
uint32_t DTRS27:1 |
| |
|
uint32_t DTRS26:1 |
| |
|
uint32_t DTRS25:1 |
| |
|
uint32_t DTRS24:1 |
| |
|
uint32_t DTRS23:1 |
| |
|
uint32_t DTRS22:1 |
| |
|
uint32_t DTRS21:1 |
| |
|
uint32_t DTRS20:1 |
| |
|
uint32_t DTRS19:1 |
| |
|
uint32_t DTRS18:1 |
| |
|
uint32_t DTRS17:1 |
| |
|
uint32_t DTRS16:1 |
| |
|
uint32_t DTRS15:1 |
| |
|
uint32_t DTRS14:1 |
| |
|
uint32_t DTRS13:1 |
| |
|
uint32_t DTRS12:1 |
| |
|
uint32_t DTRS11:1 |
| |
|
uint32_t DTRS10:1 |
| |
|
uint32_t DTRS9:1 |
| |
|
uint32_t DTRS8:1 |
| |
|
uint32_t DTRS7:1 |
| |
|
uint32_t DTRS6:1 |
| |
|
uint32_t DTRS5:1 |
| |
|
uint32_t DTRS4:1 |
| |
|
uint32_t DTRS3:1 |
| |
|
uint32_t DTRS2:1 |
| |
|
uint32_t DTRS1:1 |
| |
|
uint32_t DTRS0:1 |
| |
| } B |
| |
| } | CDTRSR_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t DTRS31:1 |
| |
|
uint32_t DTRS30:1 |
| |
|
uint32_t DTRS29:1 |
| |
|
uint32_t DTRS28:1 |
| |
|
uint32_t DTRS27:1 |
| |
|
uint32_t DTRS26:1 |
| |
|
uint32_t DTRS25:1 |
| |
|
uint32_t DTRS24:1 |
| |
|
uint32_t DTRS23:1 |
| |
|
uint32_t DTRS22:1 |
| |
|
uint32_t DTRS21:1 |
| |
|
uint32_t DTRS20:1 |
| |
|
uint32_t DTRS19:1 |
| |
|
uint32_t DTRS18:1 |
| |
|
uint32_t DTRS17:1 |
| |
|
uint32_t DTRS16:1 |
| |
|
uint32_t DTRS15:1 |
| |
|
uint32_t DTRS14:1 |
| |
|
uint32_t DTRS13:1 |
| |
|
uint32_t DTRS12:1 |
| |
|
uint32_t DTRS11:1 |
| |
|
uint32_t DTRS10:1 |
| |
|
uint32_t DTRS9:1 |
| |
|
uint32_t DTRS8:1 |
| |
|
uint32_t DTRS7:1 |
| |
|
uint32_t DTRS6:1 |
| |
|
uint32_t DTRS5:1 |
| |
|
uint32_t DTRS4:1 |
| |
|
uint32_t DTRS3:1 |
| |
|
uint32_t DTRS2:1 |
| |
|
uint32_t DTRS1:1 |
| |
|
uint32_t DTRS0:1 |
| |
| } B |
| |
| } | CDTRSR_B |
| |
|
uint32_t | eTPU_reserved0218 [2] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIOS31:1 |
| |
|
uint32_t CIOS30:1 |
| |
|
uint32_t CIOS29:1 |
| |
|
uint32_t CIOS28:1 |
| |
|
uint32_t CIOS27:1 |
| |
|
uint32_t CIOS26:1 |
| |
|
uint32_t CIOS25:1 |
| |
|
uint32_t CIOS24:1 |
| |
|
uint32_t CIOS23:1 |
| |
|
uint32_t CIOS22:1 |
| |
|
uint32_t CIOS21:1 |
| |
|
uint32_t CIOS20:1 |
| |
|
uint32_t CIOS19:1 |
| |
|
uint32_t CIOS18:1 |
| |
|
uint32_t CIOS17:1 |
| |
|
uint32_t CIOS16:1 |
| |
|
uint32_t CIOS15:1 |
| |
|
uint32_t CIOS14:1 |
| |
|
uint32_t CIOS13:1 |
| |
|
uint32_t CIOS12:1 |
| |
|
uint32_t CIOS11:1 |
| |
|
uint32_t CIOS10:1 |
| |
|
uint32_t CIOS9:1 |
| |
|
uint32_t CIOS8:1 |
| |
|
uint32_t CIOS7:1 |
| |
|
uint32_t CIOS6:1 |
| |
|
uint32_t CIOS5:1 |
| |
|
uint32_t CIOS4:1 |
| |
|
uint32_t CIOS3:1 |
| |
|
uint32_t CIOS2:1 |
| |
|
uint32_t CIOS1:1 |
| |
|
uint32_t CIOS0:1 |
| |
| } B |
| |
| } | CIOSR_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIOS31:1 |
| |
|
uint32_t CIOS30:1 |
| |
|
uint32_t CIOS29:1 |
| |
|
uint32_t CIOS28:1 |
| |
|
uint32_t CIOS27:1 |
| |
|
uint32_t CIOS26:1 |
| |
|
uint32_t CIOS25:1 |
| |
|
uint32_t CIOS24:1 |
| |
|
uint32_t CIOS23:1 |
| |
|
uint32_t CIOS22:1 |
| |
|
uint32_t CIOS21:1 |
| |
|
uint32_t CIOS20:1 |
| |
|
uint32_t CIOS19:1 |
| |
|
uint32_t CIOS18:1 |
| |
|
uint32_t CIOS17:1 |
| |
|
uint32_t CIOS16:1 |
| |
|
uint32_t CIOS15:1 |
| |
|
uint32_t CIOS14:1 |
| |
|
uint32_t CIOS13:1 |
| |
|
uint32_t CIOS12:1 |
| |
|
uint32_t CIOS11:1 |
| |
|
uint32_t CIOS10:1 |
| |
|
uint32_t CIOS9:1 |
| |
|
uint32_t CIOS8:1 |
| |
|
uint32_t CIOS7:1 |
| |
|
uint32_t CIOS6:1 |
| |
|
uint32_t CIOS5:1 |
| |
|
uint32_t CIOS4:1 |
| |
|
uint32_t CIOS3:1 |
| |
|
uint32_t CIOS2:1 |
| |
|
uint32_t CIOS1:1 |
| |
|
uint32_t CIOS0:1 |
| |
| } B |
| |
| } | CIOSR_B |
| |
|
uint32_t | eTPU_reserved0228 [2] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t DTROS31:1 |
| |
|
uint32_t DTROS30:1 |
| |
|
uint32_t DTROS29:1 |
| |
|
uint32_t DTROS28:1 |
| |
|
uint32_t DTROS27:1 |
| |
|
uint32_t DTROS26:1 |
| |
|
uint32_t DTROS25:1 |
| |
|
uint32_t DTROS24:1 |
| |
|
uint32_t DTROS23:1 |
| |
|
uint32_t DTROS22:1 |
| |
|
uint32_t DTROS21:1 |
| |
|
uint32_t DTROS20:1 |
| |
|
uint32_t DTROS19:1 |
| |
|
uint32_t DTROS18:1 |
| |
|
uint32_t DTROS17:1 |
| |
|
uint32_t DTROS16:1 |
| |
|
uint32_t DTROS15:1 |
| |
|
uint32_t DTROS14:1 |
| |
|
uint32_t DTROS13:1 |
| |
|
uint32_t DTROS12:1 |
| |
|
uint32_t DTROS11:1 |
| |
|
uint32_t DTROS10:1 |
| |
|
uint32_t DTROS9:1 |
| |
|
uint32_t DTROS8:1 |
| |
|
uint32_t DTROS7:1 |
| |
|
uint32_t DTROS6:1 |
| |
|
uint32_t DTROS5:1 |
| |
|
uint32_t DTROS4:1 |
| |
|
uint32_t DTROS3:1 |
| |
|
uint32_t DTROS2:1 |
| |
|
uint32_t DTROS1:1 |
| |
|
uint32_t DTROS0:1 |
| |
| } B |
| |
| } | CDTROSR_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t DTROS31:1 |
| |
|
uint32_t DTROS30:1 |
| |
|
uint32_t DTROS29:1 |
| |
|
uint32_t DTROS28:1 |
| |
|
uint32_t DTROS27:1 |
| |
|
uint32_t DTROS26:1 |
| |
|
uint32_t DTROS25:1 |
| |
|
uint32_t DTROS24:1 |
| |
|
uint32_t DTROS23:1 |
| |
|
uint32_t DTROS22:1 |
| |
|
uint32_t DTROS21:1 |
| |
|
uint32_t DTROS20:1 |
| |
|
uint32_t DTROS19:1 |
| |
|
uint32_t DTROS18:1 |
| |
|
uint32_t DTROS17:1 |
| |
|
uint32_t DTROS16:1 |
| |
|
uint32_t DTROS15:1 |
| |
|
uint32_t DTROS14:1 |
| |
|
uint32_t DTROS13:1 |
| |
|
uint32_t DTROS12:1 |
| |
|
uint32_t DTROS11:1 |
| |
|
uint32_t DTROS10:1 |
| |
|
uint32_t DTROS9:1 |
| |
|
uint32_t DTROS8:1 |
| |
|
uint32_t DTROS7:1 |
| |
|
uint32_t DTROS6:1 |
| |
|
uint32_t DTROS5:1 |
| |
|
uint32_t DTROS4:1 |
| |
|
uint32_t DTROS3:1 |
| |
|
uint32_t DTROS2:1 |
| |
|
uint32_t DTROS1:1 |
| |
|
uint32_t DTROS0:1 |
| |
| } B |
| |
| } | CDTROSR_B |
| |
|
uint32_t | eTPU_reserved0238 [2] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIE31:1 |
| |
|
uint32_t CIE30:1 |
| |
|
uint32_t CIE29:1 |
| |
|
uint32_t CIE28:1 |
| |
|
uint32_t CIE27:1 |
| |
|
uint32_t CIE26:1 |
| |
|
uint32_t CIE25:1 |
| |
|
uint32_t CIE24:1 |
| |
|
uint32_t CIE23:1 |
| |
|
uint32_t CIE22:1 |
| |
|
uint32_t CIE21:1 |
| |
|
uint32_t CIE20:1 |
| |
|
uint32_t CIE19:1 |
| |
|
uint32_t CIE18:1 |
| |
|
uint32_t CIE17:1 |
| |
|
uint32_t CIE16:1 |
| |
|
uint32_t CIE15:1 |
| |
|
uint32_t CIE14:1 |
| |
|
uint32_t CIE13:1 |
| |
|
uint32_t CIE12:1 |
| |
|
uint32_t CIE11:1 |
| |
|
uint32_t CIE10:1 |
| |
|
uint32_t CIE9:1 |
| |
|
uint32_t CIE8:1 |
| |
|
uint32_t CIE7:1 |
| |
|
uint32_t CIE6:1 |
| |
|
uint32_t CIE5:1 |
| |
|
uint32_t CIE4:1 |
| |
|
uint32_t CIE3:1 |
| |
|
uint32_t CIE2:1 |
| |
|
uint32_t CIE1:1 |
| |
|
uint32_t CIE0:1 |
| |
| } B |
| |
| } | CIER_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIE31:1 |
| |
|
uint32_t CIE30:1 |
| |
|
uint32_t CIE29:1 |
| |
|
uint32_t CIE28:1 |
| |
|
uint32_t CIE27:1 |
| |
|
uint32_t CIE26:1 |
| |
|
uint32_t CIE25:1 |
| |
|
uint32_t CIE24:1 |
| |
|
uint32_t CIE23:1 |
| |
|
uint32_t CIE22:1 |
| |
|
uint32_t CIE21:1 |
| |
|
uint32_t CIE20:1 |
| |
|
uint32_t CIE19:1 |
| |
|
uint32_t CIE18:1 |
| |
|
uint32_t CIE17:1 |
| |
|
uint32_t CIE16:1 |
| |
|
uint32_t CIE15:1 |
| |
|
uint32_t CIE14:1 |
| |
|
uint32_t CIE13:1 |
| |
|
uint32_t CIE12:1 |
| |
|
uint32_t CIE11:1 |
| |
|
uint32_t CIE10:1 |
| |
|
uint32_t CIE9:1 |
| |
|
uint32_t CIE8:1 |
| |
|
uint32_t CIE7:1 |
| |
|
uint32_t CIE6:1 |
| |
|
uint32_t CIE5:1 |
| |
|
uint32_t CIE4:1 |
| |
|
uint32_t CIE3:1 |
| |
|
uint32_t CIE2:1 |
| |
|
uint32_t CIE1:1 |
| |
|
uint32_t CIE0:1 |
| |
| } B |
| |
| } | CIER_B |
| |
|
uint32_t | eTPU_reserved0248 [2] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t DTRE31:1 |
| |
|
uint32_t DTRE30:1 |
| |
|
uint32_t DTRE29:1 |
| |
|
uint32_t DTRE28:1 |
| |
|
uint32_t DTRE27:1 |
| |
|
uint32_t DTRE26:1 |
| |
|
uint32_t DTRE25:1 |
| |
|
uint32_t DTRE24:1 |
| |
|
uint32_t DTRE23:1 |
| |
|
uint32_t DTRE22:1 |
| |
|
uint32_t DTRE21:1 |
| |
|
uint32_t DTRE20:1 |
| |
|
uint32_t DTRE19:1 |
| |
|
uint32_t DTRE18:1 |
| |
|
uint32_t DTRE17:1 |
| |
|
uint32_t DTRE16:1 |
| |
|
uint32_t DTRE15:1 |
| |
|
uint32_t DTRE14:1 |
| |
|
uint32_t DTRE13:1 |
| |
|
uint32_t DTRE12:1 |
| |
|
uint32_t DTRE11:1 |
| |
|
uint32_t DTRE10:1 |
| |
|
uint32_t DTRE9:1 |
| |
|
uint32_t DTRE8:1 |
| |
|
uint32_t DTRE7:1 |
| |
|
uint32_t DTRE6:1 |
| |
|
uint32_t DTRE5:1 |
| |
|
uint32_t DTRE4:1 |
| |
|
uint32_t DTRE3:1 |
| |
|
uint32_t DTRE2:1 |
| |
|
uint32_t DTRE1:1 |
| |
|
uint32_t DTRE0:1 |
| |
| } B |
| |
| } | CDTRER_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t DTRE31:1 |
| |
|
uint32_t DTRE30:1 |
| |
|
uint32_t DTRE29:1 |
| |
|
uint32_t DTRE28:1 |
| |
|
uint32_t DTRE27:1 |
| |
|
uint32_t DTRE26:1 |
| |
|
uint32_t DTRE25:1 |
| |
|
uint32_t DTRE24:1 |
| |
|
uint32_t DTRE23:1 |
| |
|
uint32_t DTRE22:1 |
| |
|
uint32_t DTRE21:1 |
| |
|
uint32_t DTRE20:1 |
| |
|
uint32_t DTRE19:1 |
| |
|
uint32_t DTRE18:1 |
| |
|
uint32_t DTRE17:1 |
| |
|
uint32_t DTRE16:1 |
| |
|
uint32_t DTRE15:1 |
| |
|
uint32_t DTRE14:1 |
| |
|
uint32_t DTRE13:1 |
| |
|
uint32_t DTRE12:1 |
| |
|
uint32_t DTRE11:1 |
| |
|
uint32_t DTRE10:1 |
| |
|
uint32_t DTRE9:1 |
| |
|
uint32_t DTRE8:1 |
| |
|
uint32_t DTRE7:1 |
| |
|
uint32_t DTRE6:1 |
| |
|
uint32_t DTRE5:1 |
| |
|
uint32_t DTRE4:1 |
| |
|
uint32_t DTRE3:1 |
| |
|
uint32_t DTRE2:1 |
| |
|
uint32_t DTRE1:1 |
| |
|
uint32_t DTRE0:1 |
| |
| } B |
| |
| } | CDTRER_B |
| |
|
uint32_t | eTPU_reserved0258 [2] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t WDS31:1 |
| |
|
uint32_t WDS30:1 |
| |
|
uint32_t WDS29:1 |
| |
|
uint32_t WDS28:1 |
| |
|
uint32_t WDS27:1 |
| |
|
uint32_t WDS26:1 |
| |
|
uint32_t WDS25:1 |
| |
|
uint32_t WDS24:1 |
| |
|
uint32_t WDS23:1 |
| |
|
uint32_t WDS22:1 |
| |
|
uint32_t WDS21:1 |
| |
|
uint32_t WDS20:1 |
| |
|
uint32_t WDS19:1 |
| |
|
uint32_t WDS18:1 |
| |
|
uint32_t WDS17:1 |
| |
|
uint32_t WDS16:1 |
| |
|
uint32_t WDS15:1 |
| |
|
uint32_t WDS14:1 |
| |
|
uint32_t WDS13:1 |
| |
|
uint32_t WDS12:1 |
| |
|
uint32_t WDS11:1 |
| |
|
uint32_t WDS10:1 |
| |
|
uint32_t WDS9:1 |
| |
|
uint32_t WDS8:1 |
| |
|
uint32_t WDS7:1 |
| |
|
uint32_t WDS6:1 |
| |
|
uint32_t WDS5:1 |
| |
|
uint32_t WDS4:1 |
| |
|
uint32_t WDS3:1 |
| |
|
uint32_t WDS2:1 |
| |
|
uint32_t WDS1:1 |
| |
|
uint32_t WDS0:1 |
| |
| } B |
| |
| } | WDSR_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t WDS31:1 |
| |
|
uint32_t WDS30:1 |
| |
|
uint32_t WDS29:1 |
| |
|
uint32_t WDS28:1 |
| |
|
uint32_t WDS27:1 |
| |
|
uint32_t WDS26:1 |
| |
|
uint32_t WDS25:1 |
| |
|
uint32_t WDS24:1 |
| |
|
uint32_t WDS23:1 |
| |
|
uint32_t WDS22:1 |
| |
|
uint32_t WDS21:1 |
| |
|
uint32_t WDS20:1 |
| |
|
uint32_t WDS19:1 |
| |
|
uint32_t WDS18:1 |
| |
|
uint32_t WDS17:1 |
| |
|
uint32_t WDS16:1 |
| |
|
uint32_t WDS15:1 |
| |
|
uint32_t WDS14:1 |
| |
|
uint32_t WDS13:1 |
| |
|
uint32_t WDS12:1 |
| |
|
uint32_t WDS11:1 |
| |
|
uint32_t WDS10:1 |
| |
|
uint32_t WDS9:1 |
| |
|
uint32_t WDS8:1 |
| |
|
uint32_t WDS7:1 |
| |
|
uint32_t WDS6:1 |
| |
|
uint32_t WDS5:1 |
| |
|
uint32_t WDS4:1 |
| |
|
uint32_t WDS3:1 |
| |
|
uint32_t WDS2:1 |
| |
|
uint32_t WDS1:1 |
| |
|
uint32_t WDS0:1 |
| |
| } B |
| |
| } | WDSR_B |
| |
|
uint32_t | eTPU_reserved0268 [6] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t SR31:1 |
| |
|
uint32_t SR30:1 |
| |
|
uint32_t SR29:1 |
| |
|
uint32_t SR28:1 |
| |
|
uint32_t SR27:1 |
| |
|
uint32_t SR26:1 |
| |
|
uint32_t SR25:1 |
| |
|
uint32_t SR24:1 |
| |
|
uint32_t SR23:1 |
| |
|
uint32_t SR22:1 |
| |
|
uint32_t SR21:1 |
| |
|
uint32_t SR20:1 |
| |
|
uint32_t SR19:1 |
| |
|
uint32_t SR18:1 |
| |
|
uint32_t SR17:1 |
| |
|
uint32_t SR16:1 |
| |
|
uint32_t SR15:1 |
| |
|
uint32_t SR14:1 |
| |
|
uint32_t SR13:1 |
| |
|
uint32_t SR12:1 |
| |
|
uint32_t SR11:1 |
| |
|
uint32_t SR10:1 |
| |
|
uint32_t SR9:1 |
| |
|
uint32_t SR8:1 |
| |
|
uint32_t SR7:1 |
| |
|
uint32_t SR6:1 |
| |
|
uint32_t SR5:1 |
| |
|
uint32_t SR4:1 |
| |
|
uint32_t SR3:1 |
| |
|
uint32_t SR2:1 |
| |
|
uint32_t SR1:1 |
| |
|
uint32_t SR0:1 |
| |
| } B |
| |
| } | CPSSR_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t SR31:1 |
| |
|
uint32_t SR30:1 |
| |
|
uint32_t SR29:1 |
| |
|
uint32_t SR28:1 |
| |
|
uint32_t SR27:1 |
| |
|
uint32_t SR26:1 |
| |
|
uint32_t SR25:1 |
| |
|
uint32_t SR24:1 |
| |
|
uint32_t SR23:1 |
| |
|
uint32_t SR22:1 |
| |
|
uint32_t SR21:1 |
| |
|
uint32_t SR20:1 |
| |
|
uint32_t SR19:1 |
| |
|
uint32_t SR18:1 |
| |
|
uint32_t SR17:1 |
| |
|
uint32_t SR16:1 |
| |
|
uint32_t SR15:1 |
| |
|
uint32_t SR14:1 |
| |
|
uint32_t SR13:1 |
| |
|
uint32_t SR12:1 |
| |
|
uint32_t SR11:1 |
| |
|
uint32_t SR10:1 |
| |
|
uint32_t SR9:1 |
| |
|
uint32_t SR8:1 |
| |
|
uint32_t SR7:1 |
| |
|
uint32_t SR6:1 |
| |
|
uint32_t SR5:1 |
| |
|
uint32_t SR4:1 |
| |
|
uint32_t SR3:1 |
| |
|
uint32_t SR2:1 |
| |
|
uint32_t SR1:1 |
| |
|
uint32_t SR0:1 |
| |
| } B |
| |
| } | CPSSR_B |
| |
|
uint32_t | eTPU_reserved0288 [2] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t SS31:1 |
| |
|
uint32_t SS30:1 |
| |
|
uint32_t SS29:1 |
| |
|
uint32_t SS28:1 |
| |
|
uint32_t SS27:1 |
| |
|
uint32_t SS26:1 |
| |
|
uint32_t SS25:1 |
| |
|
uint32_t SS24:1 |
| |
|
uint32_t SS23:1 |
| |
|
uint32_t SS22:1 |
| |
|
uint32_t SS21:1 |
| |
|
uint32_t SS20:1 |
| |
|
uint32_t SS19:1 |
| |
|
uint32_t SS18:1 |
| |
|
uint32_t SS17:1 |
| |
|
uint32_t SS16:1 |
| |
|
uint32_t SS15:1 |
| |
|
uint32_t SS14:1 |
| |
|
uint32_t SS13:1 |
| |
|
uint32_t SS12:1 |
| |
|
uint32_t SS11:1 |
| |
|
uint32_t SS10:1 |
| |
|
uint32_t SS9:1 |
| |
|
uint32_t SS8:1 |
| |
|
uint32_t SS7:1 |
| |
|
uint32_t SS6:1 |
| |
|
uint32_t SS5:1 |
| |
|
uint32_t SS4:1 |
| |
|
uint32_t SS3:1 |
| |
|
uint32_t SS2:1 |
| |
|
uint32_t SS1:1 |
| |
|
uint32_t SS0:1 |
| |
| } B |
| |
| } | CSSR_A |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t SS31:1 |
| |
|
uint32_t SS30:1 |
| |
|
uint32_t SS29:1 |
| |
|
uint32_t SS28:1 |
| |
|
uint32_t SS27:1 |
| |
|
uint32_t SS26:1 |
| |
|
uint32_t SS25:1 |
| |
|
uint32_t SS24:1 |
| |
|
uint32_t SS23:1 |
| |
|
uint32_t SS22:1 |
| |
|
uint32_t SS21:1 |
| |
|
uint32_t SS20:1 |
| |
|
uint32_t SS19:1 |
| |
|
uint32_t SS18:1 |
| |
|
uint32_t SS17:1 |
| |
|
uint32_t SS16:1 |
| |
|
uint32_t SS15:1 |
| |
|
uint32_t SS14:1 |
| |
|
uint32_t SS13:1 |
| |
|
uint32_t SS12:1 |
| |
|
uint32_t SS11:1 |
| |
|
uint32_t SS10:1 |
| |
|
uint32_t SS9:1 |
| |
|
uint32_t SS8:1 |
| |
|
uint32_t SS7:1 |
| |
|
uint32_t SS6:1 |
| |
|
uint32_t SS5:1 |
| |
|
uint32_t SS4:1 |
| |
|
uint32_t SS3:1 |
| |
|
uint32_t SS2:1 |
| |
|
uint32_t SS1:1 |
| |
|
uint32_t SS0:1 |
| |
| } B |
| |
| } | CSSR_B |
| |
|
uint32_t | eTPU_reserved0298 [2] |
| |
|
uint32_t | eTPU_reserved02A0 [88] |
| |
|
struct { |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIE:1 |
| |
|
uint32_t DTRE:1 |
| |
|
uint32_t CPR:2 |
| |
|
uint32_t __pad0__:2 |
| |
|
uint32_t ETPD:1 |
| |
|
uint32_t ETCS:1 |
| |
|
uint32_t __pad1__:3 |
| |
|
uint32_t CFS:5 |
| |
|
uint32_t ODIS:1 |
| |
|
uint32_t OPOL:1 |
| |
|
uint32_t __pad2__:3 |
| |
|
uint32_t CPBA:11 |
| |
| } B |
| |
| } CR |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t CIS:1 |
| |
|
uint32_t CIOS:1 |
| |
|
uint32_t __pad0__:6 |
| |
|
uint32_t DTRS:1 |
| |
|
uint32_t DTROS:1 |
| |
|
uint32_t __pad1__:6 |
| |
|
uint32_t IPS:1 |
| |
|
uint32_t OPS:1 |
| |
|
uint32_t OBE:1 |
| |
|
uint32_t __pad2__:11 |
| |
|
uint32_t FM1:1 |
| |
|
uint32_t FM0:1 |
| |
| } B |
| |
| } SCR |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t __pad0__:29 |
| |
|
uint32_t HSR:3 |
| |
| } B |
| |
| } HSRR |
| |
|
uint32_t eTPU_ch_reserved00C |
| |
| } | CHAN [127] |
| |
|
uint32_t | eTPU_reserved1000 [7168] |
| |
The documentation for this struct was generated from the following files:
1.8.13