|
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t MBW0:1 |
| |
|
uint32_t MTR0:1 |
| |
|
uint32_t MTW0:1 |
| |
|
uint32_t MPL0:1 |
| |
|
uint32_t MBW1:1 |
| |
|
uint32_t MTR1:1 |
| |
|
uint32_t MTW1:1 |
| |
|
uint32_t MPL1:1 |
| |
|
uint32_t MBW2:1 |
| |
|
uint32_t MTR2:1 |
| |
|
uint32_t MTW2:1 |
| |
|
uint32_t MPL2:1 |
| |
|
uint32_t MBW3:1 |
| |
|
uint32_t MTR3:1 |
| |
|
uint32_t MTW3:1 |
| |
|
uint32_t MPL3:1 |
| |
|
uint32_t __pad0__:4 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t __pad2__:4 |
| |
|
uint32_t __pad3__:4 |
| |
| } B |
| |
| } | MPCR |
| |
|
uint32_t | pbridge_b_reserved2 [7] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t BW0:1 |
| |
|
uint32_t SP0:1 |
| |
|
uint32_t WP0:1 |
| |
|
uint32_t TP0:1 |
| |
|
uint32_t BW1:1 |
| |
|
uint32_t SP1:1 |
| |
|
uint32_t WP1:1 |
| |
|
uint32_t TP1:1 |
| |
|
uint32_t __pad0__:24 |
| |
| } B |
| |
| } | PACR0 |
| |
|
uint32_t | pbridge_b_reserved3 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t BW0:1 |
| |
|
uint32_t SP0:1 |
| |
|
uint32_t WP0:1 |
| |
|
uint32_t TP0:1 |
| |
|
uint32_t BW1:1 |
| |
|
uint32_t SP1:1 |
| |
|
uint32_t WP1:1 |
| |
|
uint32_t TP1:1 |
| |
|
uint32_t BW2:1 |
| |
|
uint32_t SP2:1 |
| |
|
uint32_t WP2:1 |
| |
|
uint32_t TP2:1 |
| |
|
uint32_t __pad0__:4 |
| |
|
uint32_t __pad1__:16 |
| |
| } B |
| |
| } | PACR2 |
| |
|
uint32_t | pbridge_b_reserved4 [5] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t BW0:1 |
| |
|
uint32_t SP0:1 |
| |
|
uint32_t WP0:1 |
| |
|
uint32_t TP0:1 |
| |
|
uint32_t __pad0__:12 |
| |
|
uint32_t BW4:1 |
| |
|
uint32_t SP4:1 |
| |
|
uint32_t WP4:1 |
| |
|
uint32_t TP4:1 |
| |
|
uint32_t BW5:1 |
| |
|
uint32_t SP5:1 |
| |
|
uint32_t WP5:1 |
| |
|
uint32_t TP5:1 |
| |
|
uint32_t BW6:1 |
| |
|
uint32_t SP6:1 |
| |
|
uint32_t WP6:1 |
| |
|
uint32_t TP6:1 |
| |
|
uint32_t BW7:1 |
| |
|
uint32_t SP7:1 |
| |
|
uint32_t WP7:1 |
| |
|
uint32_t TP7:1 |
| |
| } B |
| |
| } | OPACR0 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t __pad0__:16 |
| |
|
uint32_t BW4:1 |
| |
|
uint32_t SP4:1 |
| |
|
uint32_t WP4:1 |
| |
|
uint32_t TP4:1 |
| |
|
uint32_t BW5:1 |
| |
|
uint32_t SP5:1 |
| |
|
uint32_t WP5:1 |
| |
|
uint32_t TP5:1 |
| |
|
uint32_t __pad1__:8 |
| |
| } B |
| |
| } | OPACR1 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t BW0:1 |
| |
|
uint32_t SP0:1 |
| |
|
uint32_t WP0:1 |
| |
|
uint32_t TP0:1 |
| |
|
uint32_t BW1:1 |
| |
|
uint32_t SP1:1 |
| |
|
uint32_t WP1:1 |
| |
|
uint32_t TP1:1 |
| |
|
uint32_t BW2:1 |
| |
|
uint32_t SP2:1 |
| |
|
uint32_t WP2:1 |
| |
|
uint32_t TP2:1 |
| |
|
uint32_t __pad0__:4 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t __pad2__:12 |
| |
| } B |
| |
| } | OPACR2 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t __pad0__:4 |
| |
|
uint32_t __pad1__:24 |
| |
|
uint32_t BW7:1 |
| |
|
uint32_t SP7:1 |
| |
|
uint32_t WP7:1 |
| |
|
uint32_t TP7:1 |
| |
| } B |
| |
| } | OPACR3 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t MBW0:1 |
| |
|
uint32_t MTR0:1 |
| |
|
uint32_t MTW0:1 |
| |
|
uint32_t MPL0:1 |
| |
|
uint32_t MBW1:1 |
| |
|
uint32_t MTR1:1 |
| |
|
uint32_t MTW1:1 |
| |
|
uint32_t MPL1:1 |
| |
|
uint32_t MBW2:1 |
| |
|
uint32_t MTR2:1 |
| |
|
uint32_t MTW2:1 |
| |
|
uint32_t MPL2:1 |
| |
|
uint32_t MBW3:1 |
| |
|
uint32_t MTR3:1 |
| |
|
uint32_t MTW3:1 |
| |
|
uint32_t MPL3:1 |
| |
|
uint32_t MBW4:1 |
| |
|
uint32_t MTR4:1 |
| |
|
uint32_t MTW4:1 |
| |
|
uint32_t MPL4:1 |
| |
|
uint32_t __pad0__:4 |
| |
|
uint32_t MBW6:1 |
| |
|
uint32_t MTR6:1 |
| |
|
uint32_t MTW6:1 |
| |
|
uint32_t MPL6:1 |
| |
|
uint32_t __pad1__:4 |
| |
| } B |
| |
| } | MPCR |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t BW0:1 |
| |
|
uint32_t SP0:1 |
| |
|
uint32_t WP0:1 |
| |
|
uint32_t TP0:1 |
| |
|
uint32_t BW1:1 |
| |
|
uint32_t SP1:1 |
| |
|
uint32_t WP1:1 |
| |
|
uint32_t TP1:1 |
| |
|
uint32_t __pad0__:24 |
| |
| } B |
| |
| } | PACR0 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t BW0:1 |
| |
|
uint32_t SP0:1 |
| |
|
uint32_t WP0:1 |
| |
|
uint32_t TP0:1 |
| |
|
uint32_t BW1:1 |
| |
|
uint32_t SP1:1 |
| |
|
uint32_t WP1:1 |
| |
|
uint32_t TP1:1 |
| |
|
uint32_t BW2:1 |
| |
|
uint32_t SP2:1 |
| |
|
uint32_t WP2:1 |
| |
|
uint32_t TP2:1 |
| |
|
uint32_t BW3:1 |
| |
|
uint32_t SP3:1 |
| |
|
uint32_t WP3:1 |
| |
|
uint32_t TP3:1 |
| |
|
uint32_t __pad0__:16 |
| |
| } B |
| |
| } | PACR2 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t BW0:1 |
| |
|
uint32_t SP0:1 |
| |
|
uint32_t WP0:1 |
| |
|
uint32_t TP0:1 |
| |
|
uint32_t __pad0__:12 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t BW5:1 |
| |
|
uint32_t SP5:1 |
| |
|
uint32_t WP5:1 |
| |
|
uint32_t TP5:1 |
| |
|
uint32_t BW6:1 |
| |
|
uint32_t SP6:1 |
| |
|
uint32_t WP6:1 |
| |
|
uint32_t TP6:1 |
| |
|
uint32_t BW7:1 |
| |
|
uint32_t SP7:1 |
| |
|
uint32_t WP7:1 |
| |
|
uint32_t TP7:1 |
| |
| } B |
| |
| } | OPACR0 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t __pad0__:16 |
| |
|
uint32_t BW4:1 |
| |
|
uint32_t SP4:1 |
| |
|
uint32_t WP4:1 |
| |
|
uint32_t TP4:1 |
| |
|
uint32_t BW5:1 |
| |
|
uint32_t SP5:1 |
| |
|
uint32_t WP5:1 |
| |
|
uint32_t TP5:1 |
| |
|
uint32_t __pad1__:8 |
| |
| } B |
| |
| } | OPACR1 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t BW0:1 |
| |
|
uint32_t SP0:1 |
| |
|
uint32_t WP0:1 |
| |
|
uint32_t TP0:1 |
| |
|
uint32_t BW1:1 |
| |
|
uint32_t SP1:1 |
| |
|
uint32_t WP1:1 |
| |
|
uint32_t TP1:1 |
| |
|
uint32_t BW2:1 |
| |
|
uint32_t SP2:1 |
| |
|
uint32_t WP2:1 |
| |
|
uint32_t TP2:1 |
| |
|
uint32_t BW3:1 |
| |
|
uint32_t SP3:1 |
| |
|
uint32_t WP3:1 |
| |
|
uint32_t TP3:1 |
| |
|
uint32_t BW4:1 |
| |
|
uint32_t SP4:1 |
| |
|
uint32_t WP4:1 |
| |
|
uint32_t TP4:1 |
| |
|
uint32_t __pad0__:12 |
| |
| } B |
| |
| } | OPACR2 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t BW0:1 |
| |
|
uint32_t SP0:1 |
| |
|
uint32_t WP0:1 |
| |
|
uint32_t TP0:1 |
| |
|
uint32_t __pad0__:24 |
| |
|
uint32_t BW7:1 |
| |
|
uint32_t SP7:1 |
| |
|
uint32_t WP7:1 |
| |
|
uint32_t TP7:1 |
| |
| } B |
| |
| } | OPACR3 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t MBW0:1 |
| |
|
uint32_t MTR0:1 |
| |
|
uint32_t MTW0:1 |
| |
|
uint32_t MPL0:1 |
| |
|
uint32_t MBW1:1 |
| |
|
uint32_t MTR1:1 |
| |
|
uint32_t MTW1:1 |
| |
|
uint32_t MPL1:1 |
| |
|
uint32_t MBW2:1 |
| |
|
uint32_t MTR2:1 |
| |
|
uint32_t MTW2:1 |
| |
|
uint32_t MPL2:1 |
| |
|
uint32_t MBW3:1 |
| |
|
uint32_t MTR3:1 |
| |
|
uint32_t MTW3:1 |
| |
|
uint32_t MPL3:1 |
| |
|
uint32_t MBW4:1 |
| |
|
uint32_t MTR4:1 |
| |
|
uint32_t MTW4:1 |
| |
|
uint32_t MPL4:1 |
| |
|
uint32_t MBW5:1 |
| |
|
uint32_t MTR5:1 |
| |
|
uint32_t MTW5:1 |
| |
|
uint32_t MPL5:1 |
| |
|
uint32_t MBW6:1 |
| |
|
uint32_t MTR6:1 |
| |
|
uint32_t MTW6:1 |
| |
|
uint32_t MPL6:1 |
| |
|
uint32_t MBW7:1 |
| |
|
uint32_t MTR7:1 |
| |
|
uint32_t MTW7:1 |
| |
|
uint32_t MPL7:1 |
| |
| } B |
| |
| } | MPCR |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t __pad0__:32 |
| |
| } B |
| |
| } | MPCR1 |
| |
|
uint32_t | PBRIDGE_B_reserved0008 [6] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t BW0:1 |
| |
|
uint32_t SP0:1 |
| |
|
uint32_t WP0:1 |
| |
|
uint32_t TP0:1 |
| |
|
uint32_t BW1:1 |
| |
|
uint32_t SP1:1 |
| |
|
uint32_t WP1:1 |
| |
|
uint32_t TP1:1 |
| |
|
uint32_t __pad0__:4 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t BW4:1 |
| |
|
uint32_t SP4:1 |
| |
|
uint32_t WP4:1 |
| |
|
uint32_t TP4:1 |
| |
|
uint32_t __pad2__:4 |
| |
|
uint32_t __pad3__:4 |
| |
|
uint32_t __pad4__:4 |
| |
| } B |
| |
| } | PACR0 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t __pad0__:4 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t __pad2__:4 |
| |
|
uint32_t __pad3__:4 |
| |
|
uint32_t __pad4__:4 |
| |
|
uint32_t __pad5__:4 |
| |
|
uint32_t BW6:1 |
| |
|
uint32_t SP6:1 |
| |
|
uint32_t WP6:1 |
| |
|
uint32_t TP6:1 |
| |
|
uint32_t BW7:1 |
| |
|
uint32_t SP7:1 |
| |
|
uint32_t WP7:1 |
| |
|
uint32_t TP7:1 |
| |
| } B |
| |
| } | PACR1 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t BW0:1 |
| |
|
uint32_t SP0:1 |
| |
|
uint32_t WP0:1 |
| |
|
uint32_t TP0:1 |
| |
|
uint32_t BW1:1 |
| |
|
uint32_t SP1:1 |
| |
|
uint32_t WP1:1 |
| |
|
uint32_t TP1:1 |
| |
|
uint32_t BW2:1 |
| |
|
uint32_t SP2:1 |
| |
|
uint32_t WP2:1 |
| |
|
uint32_t TP2:1 |
| |
|
uint32_t __pad0__:4 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t BW5:1 |
| |
|
uint32_t SP5:1 |
| |
|
uint32_t WP5:1 |
| |
|
uint32_t TP5:1 |
| |
|
uint32_t __pad2__:4 |
| |
|
uint32_t __pad3__:4 |
| |
| } B |
| |
| } | PACR2 |
| |
|
uint32_t | PBRIDGE_B_reserved002C [5] |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t BW0:1 |
| |
|
uint32_t SP0:1 |
| |
|
uint32_t WP0:1 |
| |
|
uint32_t TP0:1 |
| |
|
uint32_t BW1:1 |
| |
|
uint32_t SP1:1 |
| |
|
uint32_t WP1:1 |
| |
|
uint32_t TP1:1 |
| |
|
uint32_t BW2:1 |
| |
|
uint32_t SP2:1 |
| |
|
uint32_t WP2:1 |
| |
|
uint32_t TP2:1 |
| |
|
uint32_t __pad0__:4 |
| |
|
uint32_t BW4:1 |
| |
|
uint32_t SP4:1 |
| |
|
uint32_t WP4:1 |
| |
|
uint32_t TP4:1 |
| |
|
uint32_t BW5:1 |
| |
|
uint32_t SP5:1 |
| |
|
uint32_t WP5:1 |
| |
|
uint32_t TP5:1 |
| |
|
uint32_t BW6:1 |
| |
|
uint32_t SP6:1 |
| |
|
uint32_t WP6:1 |
| |
|
uint32_t TP6:1 |
| |
|
uint32_t BW7:1 |
| |
|
uint32_t SP7:1 |
| |
|
uint32_t WP7:1 |
| |
|
uint32_t TP7:1 |
| |
| } B |
| |
| } | OPACR0 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t __pad0__:4 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t __pad2__:4 |
| |
|
uint32_t __pad3__:4 |
| |
|
uint32_t BW4:1 |
| |
|
uint32_t SP4:1 |
| |
|
uint32_t WP4:1 |
| |
|
uint32_t TP4:1 |
| |
|
uint32_t BW5:1 |
| |
|
uint32_t SP5:1 |
| |
|
uint32_t WP5:1 |
| |
|
uint32_t TP5:1 |
| |
|
uint32_t BW6:1 |
| |
|
uint32_t SP6:1 |
| |
|
uint32_t WP6:1 |
| |
|
uint32_t TP6:1 |
| |
|
uint32_t __pad4__:4 |
| |
| } B |
| |
| } | OPACR1 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t BW0:1 |
| |
|
uint32_t SP0:1 |
| |
|
uint32_t WP0:1 |
| |
|
uint32_t TP0:1 |
| |
|
uint32_t BW1:1 |
| |
|
uint32_t SP1:1 |
| |
|
uint32_t WP1:1 |
| |
|
uint32_t TP1:1 |
| |
|
uint32_t BW2:1 |
| |
|
uint32_t SP2:1 |
| |
|
uint32_t WP2:1 |
| |
|
uint32_t TP2:1 |
| |
|
uint32_t BW3:1 |
| |
|
uint32_t SP3:1 |
| |
|
uint32_t WP3:1 |
| |
|
uint32_t TP3:1 |
| |
|
uint32_t __pad0__:4 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t __pad2__:4 |
| |
|
uint32_t __pad3__:4 |
| |
| } B |
| |
| } | OPACR2 |
| |
|
union { |
|
uint32_t R |
| |
|
struct { |
|
uint32_t BW0:1 |
| |
|
uint32_t SP0:1 |
| |
|
uint32_t WP0:1 |
| |
|
uint32_t TP0:1 |
| |
|
uint32_t __pad0__:4 |
| |
|
uint32_t __pad1__:4 |
| |
|
uint32_t BW3:1 |
| |
|
uint32_t SP3:1 |
| |
|
uint32_t WP3:1 |
| |
|
uint32_t TP3:1 |
| |
|
uint32_t __pad2__:4 |
| |
|
uint32_t __pad3__:4 |
| |
|
uint32_t __pad4__:4 |
| |
|
uint32_t BW7:1 |
| |
|
uint32_t SP7:1 |
| |
|
uint32_t WP7:1 |
| |
|
uint32_t TP7:1 |
| |
| } B |
| |
| } | OPACR3 |
| |
|
uint32_t | PBRIDGE_B_reserved0050 [4076] |
| |
The documentation for this struct was generated from the following files:
1.8.13