ITM Functions

Functions that access the ITM debug interface. More...

Variables
uint32_t   APSR_Type::_reserved0:16
uint32_t   APSR_Type::GE:4
uint32_t   APSR_Type::_reserved1:7
uint32_t   APSR_Type::Q:1
uint32_t   APSR_Type::V:1
uint32_t   APSR_Type::C:1
uint32_t   APSR_Type::Z:1
uint32_t   APSR_Type::N:1
struct {
uint32_t   APSR_Type::_reserved0:16
uint32_t   APSR_Type::GE:4
uint32_t   APSR_Type::_reserved1:7
uint32_t   APSR_Type::Q:1
uint32_t   APSR_Type::V:1
uint32_t   APSR_Type::C:1
uint32_t   APSR_Type::Z:1
uint32_t   APSR_Type::N:1
}	APSR_Type::b
uint32_t	APSR_Type::w
uint32_t   IPSR_Type::ISR:9
uint32_t   IPSR_Type::_reserved0:23
struct {
uint32_t   IPSR_Type::ISR:9
uint32_t   IPSR_Type::_reserved0:23
}	IPSR_Type::b
uint32_t	IPSR_Type::w
uint32_t   xPSR_Type::ISR:9
uint32_t   xPSR_Type::_reserved0:7
uint32_t   xPSR_Type::GE:4
uint32_t   xPSR_Type::_reserved1:4
uint32_t   xPSR_Type::T:1
uint32_t   xPSR_Type::IT:2
uint32_t   xPSR_Type::Q:1
uint32_t   xPSR_Type::V:1
uint32_t   xPSR_Type::C:1
uint32_t   xPSR_Type::Z:1
uint32_t   xPSR_Type::N:1
struct {
uint32_t   xPSR_Type::ISR:9
uint32_t   xPSR_Type::_reserved0:7
uint32_t   xPSR_Type::GE:4
uint32_t   xPSR_Type::_reserved1:4
uint32_t   xPSR_Type::T:1
uint32_t   xPSR_Type::IT:2
uint32_t   xPSR_Type::Q:1
uint32_t   xPSR_Type::V:1
uint32_t   xPSR_Type::C:1
uint32_t   xPSR_Type::Z:1
uint32_t   xPSR_Type::N:1
}	xPSR_Type::b
uint32_t	xPSR_Type::w
uint32_t   CONTROL_Type::nPRIV:1
uint32_t   CONTROL_Type::SPSEL:1
uint32_t   CONTROL_Type::FPCA:1
uint32_t   CONTROL_Type::_reserved0:29
struct {
uint32_t   CONTROL_Type::nPRIV:1
uint32_t   CONTROL_Type::SPSEL:1
uint32_t   CONTROL_Type::FPCA:1
uint32_t   CONTROL_Type::_reserved0:29
}	CONTROL_Type::b
uint32_t	CONTROL_Type::w
__IOM uint32_t	NVIC_Type::ISER [8U]
uint32_t	NVIC_Type::RESERVED0 [24U]
__IOM uint32_t	NVIC_Type::ICER [8U]
uint32_t	NVIC_Type::RSERVED1 [24U]
__IOM uint32_t	NVIC_Type::ISPR [8U]
uint32_t	NVIC_Type::RESERVED2 [24U]
__IOM uint32_t	NVIC_Type::ICPR [8U]
uint32_t	NVIC_Type::RESERVED3 [24U]
__IOM uint32_t	NVIC_Type::IABR [8U]
uint32_t	NVIC_Type::RESERVED4 [56U]
__IOM uint8_t	NVIC_Type::IP [240U]
uint32_t	NVIC_Type::RESERVED5 [644U]
__OM uint32_t	NVIC_Type::STIR
__IM uint32_t	SCB_Type::CPUID
__IOM uint32_t	SCB_Type::ICSR
__IOM uint32_t	SCB_Type::VTOR
__IOM uint32_t	SCB_Type::AIRCR
__IOM uint32_t	SCB_Type::SCR
__IOM uint32_t	SCB_Type::CCR
__IOM uint8_t	SCB_Type::SHPR [12U]
__IOM uint32_t	SCB_Type::SHCSR
__IOM uint32_t	SCB_Type::CFSR
__IOM uint32_t	SCB_Type::HFSR
__IOM uint32_t	SCB_Type::DFSR
__IOM uint32_t	SCB_Type::MMFAR
__IOM uint32_t	SCB_Type::BFAR
__IOM uint32_t	SCB_Type::AFSR
__IM uint32_t	SCB_Type::ID_PFR [2U]
__IM uint32_t	SCB_Type::ID_DFR
__IM uint32_t	SCB_Type::ID_AFR
__IM uint32_t	SCB_Type::ID_MFR [4U]
__IM uint32_t	SCB_Type::ID_ISAR [5U]
uint32_t	SCB_Type::RESERVED0 [1U]
__IM uint32_t	SCB_Type::CLIDR
__IM uint32_t	SCB_Type::CTR
__IM uint32_t	SCB_Type::CCSIDR
__IOM uint32_t	SCB_Type::CSSELR
__IOM uint32_t	SCB_Type::CPACR
uint32_t	SCB_Type::RESERVED3 [93U]
__OM uint32_t	SCB_Type::STIR
uint32_t	SCB_Type::RESERVED4 [15U]
__IM uint32_t	SCB_Type::MVFR0
__IM uint32_t	SCB_Type::MVFR1
__IM uint32_t	SCB_Type::MVFR2
uint32_t	SCB_Type::RESERVED5 [1U]
__OM uint32_t	SCB_Type::ICIALLU
uint32_t	SCB_Type::RESERVED6 [1U]
__OM uint32_t	SCB_Type::ICIMVAU
__OM uint32_t	SCB_Type::DCIMVAC
__OM uint32_t	SCB_Type::DCISW
__OM uint32_t	SCB_Type::DCCMVAU
__OM uint32_t	SCB_Type::DCCMVAC
__OM uint32_t	SCB_Type::DCCSW
__OM uint32_t	SCB_Type::DCCIMVAC
__OM uint32_t	SCB_Type::DCCISW
uint32_t	SCB_Type::RESERVED7 [6U]
__IOM uint32_t	SCB_Type::ITCMCR
__IOM uint32_t	SCB_Type::DTCMCR
__IOM uint32_t	SCB_Type::AHBPCR
__IOM uint32_t	SCB_Type::CACR
__IOM uint32_t	SCB_Type::AHBSCR
uint32_t	SCB_Type::RESERVED8 [1U]
__IOM uint32_t	SCB_Type::ABFSR
uint32_t	SCnSCB_Type::RESERVED0 [1U]
__IM uint32_t	SCnSCB_Type::ICTR
__IOM uint32_t	SCnSCB_Type::ACTLR
__IOM uint32_t	SysTick_Type::CTRL
__IOM uint32_t	SysTick_Type::LOAD
__IOM uint32_t	SysTick_Type::VAL
__IM uint32_t	SysTick_Type::CALIB
__OM uint8_t   ITM_Type::u8
__OM uint16_t   ITM_Type::u16
__OM uint32_t   ITM_Type::u32
union {
__OM uint8_t   ITM_Type::u8
__OM uint16_t   ITM_Type::u16
__OM uint32_t   ITM_Type::u32
}	ITM_Type::PORT [32U]
uint32_t	ITM_Type::RESERVED0 [864U]
__IOM uint32_t	ITM_Type::TER
uint32_t	ITM_Type::RESERVED1 [15U]
__IOM uint32_t	ITM_Type::TPR
uint32_t	ITM_Type::RESERVED2 [15U]
__IOM uint32_t	ITM_Type::TCR
uint32_t	ITM_Type::RESERVED3 [29U]
__OM uint32_t	ITM_Type::IWR
__IM uint32_t	ITM_Type::IRR
__IOM uint32_t	ITM_Type::IMCR
uint32_t	ITM_Type::RESERVED4 [43U]
__OM uint32_t	ITM_Type::LAR
__IM uint32_t	ITM_Type::LSR
uint32_t	ITM_Type::RESERVED5 [6U]
__IM uint32_t	ITM_Type::PID4
__IM uint32_t	ITM_Type::PID5
__IM uint32_t	ITM_Type::PID6
__IM uint32_t	ITM_Type::PID7
__IM uint32_t	ITM_Type::PID0
__IM uint32_t	ITM_Type::PID1
__IM uint32_t	ITM_Type::PID2
__IM uint32_t	ITM_Type::PID3
__IM uint32_t	ITM_Type::CID0
__IM uint32_t	ITM_Type::CID1
__IM uint32_t	ITM_Type::CID2
__IM uint32_t	ITM_Type::CID3
__IOM uint32_t	DWT_Type::CTRL
__IOM uint32_t	DWT_Type::CYCCNT
__IOM uint32_t	DWT_Type::CPICNT
__IOM uint32_t	DWT_Type::EXCCNT
__IOM uint32_t	DWT_Type::SLEEPCNT
__IOM uint32_t	DWT_Type::LSUCNT
__IOM uint32_t	DWT_Type::FOLDCNT
__IM uint32_t	DWT_Type::PCSR
__IOM uint32_t	DWT_Type::COMP0
__IOM uint32_t	DWT_Type::MASK0
__IOM uint32_t	DWT_Type::FUNCTION0
uint32_t	DWT_Type::RESERVED0 [1U]
__IOM uint32_t	DWT_Type::COMP1
__IOM uint32_t	DWT_Type::MASK1
__IOM uint32_t	DWT_Type::FUNCTION1
uint32_t	DWT_Type::RESERVED1 [1U]
__IOM uint32_t	DWT_Type::COMP2
__IOM uint32_t	DWT_Type::MASK2
__IOM uint32_t	DWT_Type::FUNCTION2
uint32_t	DWT_Type::RESERVED2 [1U]
__IOM uint32_t	DWT_Type::COMP3
__IOM uint32_t	DWT_Type::MASK3
__IOM uint32_t	DWT_Type::FUNCTION3
uint32_t	DWT_Type::RESERVED3 [981U]
__OM uint32_t	DWT_Type::LAR
__IM uint32_t	DWT_Type::LSR
__IOM uint32_t	TPI_Type::SSPSR
__IOM uint32_t	TPI_Type::CSPSR
uint32_t	TPI_Type::RESERVED0 [2U]
__IOM uint32_t	TPI_Type::ACPR
uint32_t	TPI_Type::RESERVED1 [55U]
__IOM uint32_t	TPI_Type::SPPR
uint32_t	TPI_Type::RESERVED2 [131U]
__IM uint32_t	TPI_Type::FFSR
__IOM uint32_t	TPI_Type::FFCR
__IM uint32_t	TPI_Type::FSCR
uint32_t	TPI_Type::RESERVED3 [759U]
__IM uint32_t	TPI_Type::TRIGGER
__IM uint32_t	TPI_Type::FIFO0
__IM uint32_t	TPI_Type::ITATBCTR2
uint32_t	TPI_Type::RESERVED4 [1U]
__IM uint32_t	TPI_Type::ITATBCTR0
__IM uint32_t	TPI_Type::FIFO1
__IOM uint32_t	TPI_Type::ITCTRL
uint32_t	TPI_Type::RESERVED5 [39U]
__IOM uint32_t	TPI_Type::CLAIMSET
__IOM uint32_t	TPI_Type::CLAIMCLR
uint32_t	TPI_Type::RESERVED7 [8U]
__IM uint32_t	TPI_Type::DEVID
__IM uint32_t	TPI_Type::DEVTYPE
__IOM uint32_t	CoreDebug_Type::DHCSR
__OM uint32_t	CoreDebug_Type::DCRSR
__IOM uint32_t	CoreDebug_Type::DCRDR
__IOM uint32_t	CoreDebug_Type::DEMCR
volatile int32_t	ITM_RxBuffer
__STATIC_INLINE uint32_t	ITM_SendChar (uint32_t ch)
	ITM Send Character. More...
__STATIC_INLINE int32_t	ITM_ReceiveChar (void)
	ITM Receive Character. More...
__STATIC_INLINE int32_t	ITM_CheckChar (void)
	ITM Check Character. More...
#define	ITM_RXBUFFER_EMPTY   0x5AA55AA5U

Detailed Description

Functions that access the ITM debug interface.

Macro Definition Documentation

ITM_RXBUFFER_EMPTY

#define ITM_RXBUFFER_EMPTY   0x5AA55AA5U

Value identifying ITM_RxBuffer is ready for next character.

Function Documentation

ITM_CheckChar()

__STATIC_INLINE int32_t ITM_CheckChar

(

void

)

ITM Check Character.

Checks whether a character is pending for reading in the variable ITM_RxBuffer.

Returns

0 No character available.

1 Character available.

ITM_ReceiveChar()

__STATIC_INLINE int32_t ITM_ReceiveChar

(

void

)

ITM Receive Character.

Inputs a character via the external variable ITM_RxBuffer.

Returns

Received character.

-1 No character pending.

ITM_SendChar()

__STATIC_INLINE uint32_t ITM_SendChar

(

uint32_t

ch

)

ITM Send Character.

Transmits a character via the ITM channel 0, and

• Just returns when no debugger is connected that has booked the output.
• Is blocking when a debugger is connected, but the previous character sent has not been transmitted.

  Parameters

  [in]

  ch

  Character to transmit.

  Returns

  Character to transmit.

Variable Documentation

_reserved0 [1/8]

uint32_t APSR_Type::_reserved0

bit: 0..15 Reserved

[2/8]

uint32_t { ... } ::_reserved0

bit: 0..15 Reserved

[3/8]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

_reserved0 [4/8]

uint32_t IPSR_Type::_reserved0

bit: 9..31 Reserved

[5/8]

uint32_t { ... } ::_reserved0

bit: 9..15 Reserved

_reserved0 [6/8]

uint32_t xPSR_Type::_reserved0

bit: 9..15 Reserved

[7/8]

uint32_t { ... } ::_reserved0

bit: 3..31 Reserved

_reserved0 [8/8]

uint32_t CONTROL_Type::_reserved0

bit: 3..31 Reserved

_reserved1 [1/4]

uint32_t APSR_Type::_reserved1

bit: 20..26 Reserved

[2/4]

uint32_t { ... } ::_reserved1

bit: 20..26 Reserved

[3/4]

uint32_t { ... } ::_reserved1

bit: 20..23 Reserved

_reserved1 [4/4]

uint32_t xPSR_Type::_reserved1

bit: 20..23 Reserved

ABFSR

__IOM uint32_t SCB_Type::ABFSR

Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register

ACPR

__IOM uint32_t TPI_Type::ACPR

Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register

ACTLR

__IOM uint32_t SCnSCB_Type::ACTLR

Offset: 0x008 (R/W) Auxiliary Control Register

AFSR

__IOM uint32_t SCB_Type::AFSR

Offset: 0x03C (R/W) Auxiliary Fault Status Register

AHBPCR

__IOM uint32_t SCB_Type::AHBPCR

Offset: 0x298 (R/W) AHBP Control Register

AHBSCR

__IOM uint32_t SCB_Type::AHBSCR

Offset: 0x2A0 (R/W) AHB Slave Control Register

AIRCR

__IOM uint32_t SCB_Type::AIRCR

Offset: 0x00C (R/W) Application Interrupt and Reset Control Register

[1/4]

struct { ... } APSR_Type::b

Structure used for bit access

[2/4]

struct { ... } IPSR_Type::b

Structure used for bit access

[3/4]

struct { ... } xPSR_Type::b

Structure used for bit access

[4/4]

struct { ... } CONTROL_Type::b

Structure used for bit access

BFAR

__IOM uint32_t SCB_Type::BFAR

Offset: 0x038 (R/W) BusFault Address Register

[1/4]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

C [2/4]

uint32_t APSR_Type::C

bit: 29 Carry condition code flag

C [3/4]

uint32_t xPSR_Type::C

bit: 29 Carry condition code flag

[4/4]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

CACR

__IOM uint32_t SCB_Type::CACR

Offset: 0x29C (R/W) L1 Cache Control Register

CALIB

__IM uint32_t SysTick_Type::CALIB

Offset: 0x00C (R/ ) SysTick Calibration Register

CCR

__IOM uint32_t SCB_Type::CCR

Offset: 0x014 (R/W) Configuration Control Register

CCSIDR

__IM uint32_t SCB_Type::CCSIDR

Offset: 0x080 (R/ ) Cache Size ID Register

CFSR

__IOM uint32_t SCB_Type::CFSR

Offset: 0x028 (R/W) Configurable Fault Status Register

CID0

__IM uint32_t ITM_Type::CID0

Offset: 0xFF0 (R/ ) ITM Component Identification Register #0

CID1

__IM uint32_t ITM_Type::CID1

Offset: 0xFF4 (R/ ) ITM Component Identification Register #1

CID2

__IM uint32_t ITM_Type::CID2

Offset: 0xFF8 (R/ ) ITM Component Identification Register #2

CID3

__IM uint32_t ITM_Type::CID3

Offset: 0xFFC (R/ ) ITM Component Identification Register #3

CLAIMCLR

__IOM uint32_t TPI_Type::CLAIMCLR

Offset: 0xFA4 (R/W) Claim tag clear

CLAIMSET

__IOM uint32_t TPI_Type::CLAIMSET

Offset: 0xFA0 (R/W) Claim tag set

CLIDR

__IM uint32_t SCB_Type::CLIDR

Offset: 0x078 (R/ ) Cache Level ID register

COMP0

__IOM uint32_t DWT_Type::COMP0

Offset: 0x020 (R/W) Comparator Register 0

COMP1

__IOM uint32_t DWT_Type::COMP1

Offset: 0x030 (R/W) Comparator Register 1

COMP2

__IOM uint32_t DWT_Type::COMP2

Offset: 0x040 (R/W) Comparator Register 2

COMP3

__IOM uint32_t DWT_Type::COMP3

Offset: 0x050 (R/W) Comparator Register 3

CPACR

__IOM uint32_t SCB_Type::CPACR

Offset: 0x088 (R/W) Coprocessor Access Control Register

CPICNT

__IOM uint32_t DWT_Type::CPICNT

Offset: 0x008 (R/W) CPI Count Register

CPUID

__IM uint32_t SCB_Type::CPUID

Offset: 0x000 (R/ ) CPUID Base Register

CSPSR

__IOM uint32_t TPI_Type::CSPSR

Offset: 0x004 (R/W) Current Parallel Port Size Register

CSSELR

__IOM uint32_t SCB_Type::CSSELR

Offset: 0x084 (R/W) Cache Size Selection Register

CTR

__IM uint32_t SCB_Type::CTR

Offset: 0x07C (R/ ) Cache Type register

CTRL [1/2]

__IOM uint32_t SysTick_Type::CTRL

Offset: 0x000 (R/W) SysTick Control and Status Register

CTRL [2/2]

__IOM uint32_t DWT_Type::CTRL

Offset: 0x000 (R/W) Control Register

CYCCNT

__IOM uint32_t DWT_Type::CYCCNT

Offset: 0x004 (R/W) Cycle Count Register

DCCIMVAC

__OM uint32_t SCB_Type::DCCIMVAC

Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC

DCCISW

__OM uint32_t SCB_Type::DCCISW

Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way

DCCMVAC

__OM uint32_t SCB_Type::DCCMVAC

Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC

DCCMVAU

__OM uint32_t SCB_Type::DCCMVAU

Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU

DCCSW

__OM uint32_t SCB_Type::DCCSW

Offset: 0x26C ( /W) D-Cache Clean by Set-way

DCIMVAC

__OM uint32_t SCB_Type::DCIMVAC

Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC

DCISW

__OM uint32_t SCB_Type::DCISW

Offset: 0x260 ( /W) D-Cache Invalidate by Set-way

DCRDR

__IOM uint32_t CoreDebug_Type::DCRDR

Offset: 0x008 (R/W) Debug Core Register Data Register

DCRSR

__OM uint32_t CoreDebug_Type::DCRSR

Offset: 0x004 ( /W) Debug Core Register Selector Register

DEMCR

__IOM uint32_t CoreDebug_Type::DEMCR

Offset: 0x00C (R/W) Debug Exception and Monitor Control Register

DEVID

__IM uint32_t TPI_Type::DEVID

Offset: 0xFC8 (R/ ) TPIU_DEVID

DEVTYPE

__IM uint32_t TPI_Type::DEVTYPE

Offset: 0xFCC (R/ ) TPIU_DEVTYPE

DFSR

__IOM uint32_t SCB_Type::DFSR

Offset: 0x030 (R/W) Debug Fault Status Register

DHCSR

__IOM uint32_t CoreDebug_Type::DHCSR

Offset: 0x000 (R/W) Debug Halting Control and Status Register

DTCMCR

__IOM uint32_t SCB_Type::DTCMCR

Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers

EXCCNT

__IOM uint32_t DWT_Type::EXCCNT

Offset: 0x00C (R/W) Exception Overhead Count Register

FFCR

__IOM uint32_t TPI_Type::FFCR

Offset: 0x304 (R/W) Formatter and Flush Control Register

FFSR

__IM uint32_t TPI_Type::FFSR

Offset: 0x300 (R/ ) Formatter and Flush Status Register

FIFO0

__IM uint32_t TPI_Type::FIFO0

Offset: 0xEEC (R/ ) Integration ETM Data

FIFO1

__IM uint32_t TPI_Type::FIFO1

Offset: 0xEFC (R/ ) Integration ITM Data

FOLDCNT

__IOM uint32_t DWT_Type::FOLDCNT

Offset: 0x018 (R/W) Folded-instruction Count Register

FPCA [1/2]

uint32_t CONTROL_Type::FPCA

bit: 2 FP extension active flag

[2/2]

uint32_t { ... } ::FPCA

bit: 2 FP extension active flag

FSCR

__IM uint32_t TPI_Type::FSCR

Offset: 0x308 (R/ ) Formatter Synchronization Counter Register

FUNCTION0

__IOM uint32_t DWT_Type::FUNCTION0

Offset: 0x028 (R/W) Function Register 0

FUNCTION1

__IOM uint32_t DWT_Type::FUNCTION1

Offset: 0x038 (R/W) Function Register 1

FUNCTION2

__IOM uint32_t DWT_Type::FUNCTION2

Offset: 0x048 (R/W) Function Register 2

FUNCTION3

__IOM uint32_t DWT_Type::FUNCTION3

Offset: 0x058 (R/W) Function Register 3

GE [1/4]

uint32_t APSR_Type::GE

bit: 16..19 Greater than or Equal flags

[2/4]

uint32_t { ... } ::GE

bit: 16..19 Greater than or Equal flags

[3/4]

uint32_t { ... } ::GE

bit: 16..19 Greater than or Equal flags

GE [4/4]

uint32_t xPSR_Type::GE

bit: 16..19 Greater than or Equal flags

HFSR

__IOM uint32_t SCB_Type::HFSR

Offset: 0x02C (R/W) HardFault Status Register

IABR

__IOM uint32_t NVIC_Type::IABR[8U]

Offset: 0x200 (R/W) Interrupt Active bit Register

ICER

__IOM uint32_t NVIC_Type::ICER[8U]

Offset: 0x080 (R/W) Interrupt Clear Enable Register

ICIALLU

__OM uint32_t SCB_Type::ICIALLU

Offset: 0x250 ( /W) I-Cache Invalidate All to PoU

ICIMVAU

__OM uint32_t SCB_Type::ICIMVAU

Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU

ICPR

__IOM uint32_t NVIC_Type::ICPR[8U]

Offset: 0x180 (R/W) Interrupt Clear Pending Register

ICSR

__IOM uint32_t SCB_Type::ICSR

Offset: 0x004 (R/W) Interrupt Control and State Register

ICTR

__IM uint32_t SCnSCB_Type::ICTR

Offset: 0x004 (R/ ) Interrupt Controller Type Register

ID_AFR

__IM uint32_t SCB_Type::ID_AFR

Offset: 0x04C (R/ ) Auxiliary Feature Register

ID_DFR

__IM uint32_t SCB_Type::ID_DFR

Offset: 0x048 (R/ ) Debug Feature Register

ID_ISAR

__IM uint32_t SCB_Type::ID_ISAR[5U]

Offset: 0x060 (R/ ) Instruction Set Attributes Register

ID_MFR

__IM uint32_t SCB_Type::ID_MFR[4U]

Offset: 0x050 (R/ ) Memory Model Feature Register

ID_PFR

__IM uint32_t SCB_Type::ID_PFR[2U]

Offset: 0x040 (R/ ) Processor Feature Register

IMCR

__IOM uint32_t ITM_Type::IMCR

Offset: 0xF00 (R/W) ITM Integration Mode Control Register

IP

__IOM uint8_t NVIC_Type::IP[240U]

Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

IRR

__IM uint32_t ITM_Type::IRR

Offset: 0xEFC (R/ ) ITM Integration Read Register

ISER

__IOM uint32_t NVIC_Type::ISER[8U]

Offset: 0x000 (R/W) Interrupt Set Enable Register

ISPR

__IOM uint32_t NVIC_Type::ISPR[8U]

Offset: 0x100 (R/W) Interrupt Set Pending Register

[1/4]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

ISR [2/4]

uint32_t IPSR_Type::ISR

bit: 0.. 8 Exception number

[3/4]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

ISR [4/4]

uint32_t xPSR_Type::ISR

bit: 0.. 8 Exception number

[1/2]

uint32_t { ... } ::IT

bit: 25..26 saved IT state (read 0)

IT [2/2]

uint32_t xPSR_Type::IT

bit: 25..26 saved IT state (read 0)

ITATBCTR0

__IM uint32_t TPI_Type::ITATBCTR0

Offset: 0xEF8 (R/ ) ITATBCTR0

ITATBCTR2

__IM uint32_t TPI_Type::ITATBCTR2

Offset: 0xEF0 (R/ ) ITATBCTR2

ITCMCR

__IOM uint32_t SCB_Type::ITCMCR

Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register

ITCTRL

__IOM uint32_t TPI_Type::ITCTRL

Offset: 0xF00 (R/W) Integration Mode Control

ITM_RxBuffer

volatile int32_t ITM_RxBuffer

extern

External variable to receive characters.

IWR

__OM uint32_t ITM_Type::IWR

Offset: 0xEF8 ( /W) ITM Integration Write Register

LAR [1/2]

__OM uint32_t ITM_Type::LAR

Offset: 0xFB0 ( /W) ITM Lock Access Register

LAR [2/2]

__OM uint32_t DWT_Type::LAR

Offset: 0xFB0 ( W) Lock Access Register

LOAD

__IOM uint32_t SysTick_Type::LOAD

Offset: 0x004 (R/W) SysTick Reload Value Register

LSR [1/2]

__IM uint32_t ITM_Type::LSR

Offset: 0xFB4 (R/ ) ITM Lock Status Register

LSR [2/2]

__IM uint32_t DWT_Type::LSR

Offset: 0xFB4 (R ) Lock Status Register

LSUCNT

__IOM uint32_t DWT_Type::LSUCNT

Offset: 0x014 (R/W) LSU Count Register

MASK0

__IOM uint32_t DWT_Type::MASK0

Offset: 0x024 (R/W) Mask Register 0

MASK1

__IOM uint32_t DWT_Type::MASK1

Offset: 0x034 (R/W) Mask Register 1

MASK2

__IOM uint32_t DWT_Type::MASK2

Offset: 0x044 (R/W) Mask Register 2

MASK3

__IOM uint32_t DWT_Type::MASK3

Offset: 0x054 (R/W) Mask Register 3

MMFAR

__IOM uint32_t SCB_Type::MMFAR

Offset: 0x034 (R/W) MemManage Fault Address Register

MVFR0

__IM uint32_t SCB_Type::MVFR0

Offset: 0x240 (R/ ) Media and VFP Feature Register 0

MVFR1

__IM uint32_t SCB_Type::MVFR1

Offset: 0x244 (R/ ) Media and VFP Feature Register 1

MVFR2

__IM uint32_t SCB_Type::MVFR2

Offset: 0x248 (R/ ) Media and VFP Feature Register 1

N [1/4]

uint32_t APSR_Type::N

bit: 31 Negative condition code flag

[2/4]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

[3/4]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

N [4/4]

uint32_t xPSR_Type::N

bit: 31 Negative condition code flag

[1/2]

uint32_t { ... } ::nPRIV

bit: 0 Execution privilege in Thread mode

nPRIV [2/2]

uint32_t CONTROL_Type::nPRIV

bit: 0 Execution privilege in Thread mode

PCSR

__IM uint32_t DWT_Type::PCSR

Offset: 0x01C (R/ ) Program Counter Sample Register

PID0

__IM uint32_t ITM_Type::PID0

Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0

PID1

__IM uint32_t ITM_Type::PID1

Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1

PID2

__IM uint32_t ITM_Type::PID2

Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2

PID3

__IM uint32_t ITM_Type::PID3

Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3

PID4

__IM uint32_t ITM_Type::PID4

Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4

PID5

__IM uint32_t ITM_Type::PID5

Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5

PID6

__IM uint32_t ITM_Type::PID6

Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6

PID7

__IM uint32_t ITM_Type::PID7

Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7

__OM union { ... } ITM_Type::PORT[32U]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

Q [1/4]

uint32_t APSR_Type::Q

bit: 27 Saturation condition flag

[2/4]

uint32_t { ... } ::Q

bit: 27 Saturation condition flag

Q [3/4]

uint32_t xPSR_Type::Q

bit: 27 Saturation condition flag

[4/4]

uint32_t { ... } ::Q

bit: 27 Saturation condition flag

SCR

__IOM uint32_t SCB_Type::SCR

Offset: 0x010 (R/W) System Control Register

SHCSR

__IOM uint32_t SCB_Type::SHCSR

Offset: 0x024 (R/W) System Handler Control and State Register

SHPR

__IOM uint8_t SCB_Type::SHPR[12U]

Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)

SLEEPCNT

__IOM uint32_t DWT_Type::SLEEPCNT

Offset: 0x010 (R/W) Sleep Count Register

SPPR

__IOM uint32_t TPI_Type::SPPR

Offset: 0x0F0 (R/W) Selected Pin Protocol Register

[1/2]

uint32_t { ... } ::SPSEL

bit: 1 Stack to be used

SPSEL [2/2]

uint32_t CONTROL_Type::SPSEL

bit: 1 Stack to be used

SSPSR

__IOM uint32_t TPI_Type::SSPSR

Offset: 0x000 (R/ ) Supported Parallel Port Size Register

STIR [1/2]

__OM uint32_t NVIC_Type::STIR

Offset: 0xE00 ( /W) Software Trigger Interrupt Register

STIR [2/2]

__OM uint32_t SCB_Type::STIR

Offset: 0x200 ( /W) Software Triggered Interrupt Register

T [1/2]

uint32_t xPSR_Type::T

bit: 24 Thumb bit (read 0)

[2/2]

uint32_t { ... } ::T

bit: 24 Thumb bit (read 0)

TCR

__IOM uint32_t ITM_Type::TCR

Offset: 0xE80 (R/W) ITM Trace Control Register

TER

__IOM uint32_t ITM_Type::TER

Offset: 0xE00 (R/W) ITM Trace Enable Register

TPR

__IOM uint32_t ITM_Type::TPR

Offset: 0xE40 (R/W) ITM Trace Privilege Register

TRIGGER

__IM uint32_t TPI_Type::TRIGGER

Offset: 0xEE8 (R/ ) TRIGGER

[1/2]

__OM uint16_t { ... } ::u16

Offset: 0x000 ( /W) ITM Stimulus Port 16-bit

u16 [2/2]

__OM uint16_t ITM_Type::u16

Offset: 0x000 ( /W) ITM Stimulus Port 16-bit

[1/2]

__OM uint32_t { ... } ::u32

Offset: 0x000 ( /W) ITM Stimulus Port 32-bit

u32 [2/2]

__OM uint32_t ITM_Type::u32

Offset: 0x000 ( /W) ITM Stimulus Port 32-bit

[1/2]

__OM uint8_t { ... } ::u8

Offset: 0x000 ( /W) ITM Stimulus Port 8-bit

u8 [2/2]

__OM uint8_t ITM_Type::u8

Offset: 0x000 ( /W) ITM Stimulus Port 8-bit

[1/4]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

V [2/4]

uint32_t APSR_Type::V

bit: 28 Overflow condition code flag

V [3/4]

uint32_t xPSR_Type::V

bit: 28 Overflow condition code flag

[4/4]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

VAL

__IOM uint32_t SysTick_Type::VAL

Offset: 0x008 (R/W) SysTick Current Value Register

VTOR

__IOM uint32_t SCB_Type::VTOR

Offset: 0x008 (R/W) Vector Table Offset Register

w [1/4]

uint32_t APSR_Type::w

Type used for word access

w [2/4]

uint32_t IPSR_Type::w

Type used for word access

w [3/4]

uint32_t xPSR_Type::w

Type used for word access

w [4/4]

uint32_t CONTROL_Type::w

Type used for word access

Z [1/4]

uint32_t APSR_Type::Z

bit: 30 Zero condition code flag

[2/4]

uint32_t { ... } ::Z

bit: 30 Zero condition code flag

Z [3/4]

uint32_t xPSR_Type::Z

bit: 30 Zero condition code flag

[4/4]

uint32_t { ... } ::Z

bit: 30 Zero condition code flag