RTEMS CPU Kit with SuperCore
4.11.2
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mnt
data0
chrisj
rtems
releases
rtems-release.git
4.11.2
ws-rtems
rtems-4.11.2
cpukit
score
include
rtems
score
isrlevel.h
Go to the documentation of this file.
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/*
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* COPYRIGHT (c) 1989-2011.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef _RTEMS_SCORE_ISR_LEVEL_h
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#define _RTEMS_SCORE_ISR_LEVEL_h
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#include <rtems/score/cpu.h>
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#include <
rtems/score/assert.h
>
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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typedef
uint32_t
ISR_Level
;
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#define _ISR_Disable( _level ) \
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do { \
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_CPU_ISR_Disable( _level ); \
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_Assert( _Debug_Is_owner_of_giant() ); \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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} while (0)
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#define _ISR_Enable( _level ) \
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do { \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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_Assert( _Debug_Is_owner_of_giant() ); \
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_CPU_ISR_Enable( _level ); \
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} while (0)
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#define _ISR_Flash( _level ) \
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do { \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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_Assert( _Debug_Is_owner_of_giant() ); \
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_CPU_ISR_Flash( _level ); \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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} while (0)
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#define _ISR_Get_level() \
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_CPU_ISR_Get_level()
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#define _ISR_Set_level( _new_level ) \
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do { \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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_CPU_ISR_Set_level( _new_level ); \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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} while (0)
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#define _ISR_Disable_without_giant( _level ) \
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do { \
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_CPU_ISR_Disable( _level ); \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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} while (0)
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#define _ISR_Enable_without_giant( _level ) \
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do { \
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RTEMS_COMPILER_MEMORY_BARRIER(); \
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_CPU_ISR_Enable( _level ); \
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} while (0)
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#ifdef __cplusplus
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}
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#endif
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#endif
assert.h
ISR_Level
uint32_t ISR_Level
The following type defines the control block used to manage the interrupt level portion of the status...
Definition:
isrlevel.h:42
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