RTEMS CPU Kit with SuperCore  4.11.2
isrlevel.h
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1 
10 /*
11  * COPYRIGHT (c) 1989-2011.
12  * On-Line Applications Research Corporation (OAR).
13  *
14  * The license and distribution terms for this file may be
15  * found in the file LICENSE in this distribution or at
16  * http://www.rtems.org/license/LICENSE.
17  */
18 
19 #ifndef _RTEMS_SCORE_ISR_LEVEL_h
20 #define _RTEMS_SCORE_ISR_LEVEL_h
21 
22 #include <rtems/score/cpu.h>
23 #include <rtems/score/assert.h>
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
42 typedef uint32_t ISR_Level;
43 
58 #define _ISR_Disable( _level ) \
59  do { \
60  _CPU_ISR_Disable( _level ); \
61  _Assert( _Debug_Is_owner_of_giant() ); \
62  RTEMS_COMPILER_MEMORY_BARRIER(); \
63  } while (0)
64 
76 #define _ISR_Enable( _level ) \
77  do { \
78  RTEMS_COMPILER_MEMORY_BARRIER(); \
79  _Assert( _Debug_Is_owner_of_giant() ); \
80  _CPU_ISR_Enable( _level ); \
81  } while (0)
82 
102 #define _ISR_Flash( _level ) \
103  do { \
104  RTEMS_COMPILER_MEMORY_BARRIER(); \
105  _Assert( _Debug_Is_owner_of_giant() ); \
106  _CPU_ISR_Flash( _level ); \
107  RTEMS_COMPILER_MEMORY_BARRIER(); \
108  } while (0)
109 
120 #define _ISR_Get_level() \
121  _CPU_ISR_Get_level()
122 
132 #define _ISR_Set_level( _new_level ) \
133  do { \
134  RTEMS_COMPILER_MEMORY_BARRIER(); \
135  _CPU_ISR_Set_level( _new_level ); \
136  RTEMS_COMPILER_MEMORY_BARRIER(); \
137  } while (0)
138 
139 #define _ISR_Disable_without_giant( _level ) \
140  do { \
141  _CPU_ISR_Disable( _level ); \
142  RTEMS_COMPILER_MEMORY_BARRIER(); \
143  } while (0)
144 
145 #define _ISR_Enable_without_giant( _level ) \
146  do { \
147  RTEMS_COMPILER_MEMORY_BARRIER(); \
148  _CPU_ISR_Enable( _level ); \
149  } while (0)
150 
153 #ifdef __cplusplus
154 }
155 #endif
156 #endif
uint32_t ISR_Level
The following type defines the control block used to manage the interrupt level portion of the status...
Definition: isrlevel.h:42