RTEMS  5.0.0
cpu.h
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1 
10 /*
11  * COPYRIGHT (c) 1989-2012.
12  * On-Line Applications Research Corporation (OAR).
13  *
14  * The license and distribution terms for this file may be
15  * found in the file LICENSE in this distribution or at
16  * http://www.rtems.org/license/LICENSE.
17  */
18 
19 #ifndef _RTEMS_SCORE_CPU_H
20 #define _RTEMS_SCORE_CPU_H
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
26 #include <rtems/score/basedefs.h>
27 #include <rtems/score/v850.h>
28 
29 /* conditional compilation parameters */
30 
42 #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
43 
84 #define CPU_HARDWARE_FP FALSE
85 #define CPU_SOFTWARE_FP FALSE
86 
115 #define CPU_ALL_TASKS_ARE_FP FALSE
116 
132 #define CPU_IDLE_TASK_IS_FP FALSE
133 
163 #define CPU_USE_DEFERRED_FP_SWITCH TRUE
164 
165 #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
166 
178 #define CPU_STACK_GROWS_UP FALSE
179 
180 /* FIXME: Is this the right value? */
181 #define CPU_CACHE_LINE_BYTES 32
182 
183 #define CPU_STRUCTURE_ALIGNMENT
184 
195 #define CPU_MODES_INTERRUPT_MASK 0x00000001
196 
197 #define CPU_MAXIMUM_PROCESSORS 32
198 
250 typedef struct {
251  uint32_t r1;
254  uint32_t r20;
255  uint32_t r21;
256  uint32_t r22;
257  uint32_t r23;
258  uint32_t r24;
259  uint32_t r25;
260  uint32_t r26;
261  uint32_t r27;
262  uint32_t r28;
263  uint32_t r29;
264  uint32_t r31;
265  uint32_t psw;
267 
275 #define _CPU_Context_Get_SP( _context ) \
276  (_context)->r3_stack_pointer
277 
282 typedef struct {
284  double some_float_register;
286 
292 typedef struct {
297  uint32_t special_interrupt_register;
299 
311 /* #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) */
312 #define CPU_CONTEXT_FP_SIZE 0
313 
333 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
334 
339 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
340 
352 #define CPU_STACK_MINIMUM_SIZE (1024*4)
353 
354 #define CPU_SIZEOF_POINTER 4
355 
364 #define CPU_ALIGNMENT 8
365 
389 #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
390 
405 #define CPU_STACK_ALIGNMENT 4
406 
407 #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
408 
409 /*
410  * ISR handler macros
411  */
412 
428 #define _CPU_ISR_Disable( _isr_cookie ) \
429  do { \
430  unsigned int _psw; \
431  \
432  v850_get_psw( _psw ); \
433  __asm__ __volatile__( "di" ); \
434  _isr_cookie = _psw; \
435  } while (0)
436 
448 #define _CPU_ISR_Enable( _isr_cookie ) \
449  do { \
450  unsigned int _psw = (_isr_cookie); \
451  \
452  v850_set_psw( _psw ); \
453  } while (0)
454 
467 #define _CPU_ISR_Flash( _isr_cookie ) \
468  do { \
469  unsigned int _psw = (_isr_cookie); \
470  v850_set_psw( _psw ); \
471  __asm__ __volatile__( "di" ); \
472  } while (0)
473 
475 {
476  return ( level & V850_PSW_INTERRUPT_DISABLE_MASK )
477  != V850_PSW_INTERRUPT_DISABLE;
478 }
479 
495 #define _CPU_ISR_Set_level( new_level ) \
496  do { \
497  if ( new_level ) \
498  __asm__ __volatile__( "di" ); \
499  else \
500  __asm__ __volatile__( "ei" ); \
501  } while (0)
502 
513 uint32_t _CPU_ISR_Get_level( void );
514 
515 /* end of ISR handler macros */
516 
519 /* Context handler macros */
520 
554  Context_Control *the_context,
555  uint32_t *stack_base,
556  uint32_t size,
557  uint32_t new_level,
558  void *entry_point,
559  bool is_fp,
560  void *tls_area
561 );
562 
578 #define _CPU_Context_Restart_self( _the_context ) \
579  _CPU_Context_restore( (_the_context) );
580 
581 /* XXX this should be possible to remove */
582 #if 0
583 
601 #define _CPU_Context_Initialize_fp( _destination ) \
602  { \
603  }
604 #endif
605 
606 /* end of Context handler macros */
607 
608 /* Fatal Error manager macros */
609 
619 #define _CPU_Fatal_halt( _source, _error ) \
620  do { \
621  __asm__ __volatile__ ( "di" ); \
622  __asm__ __volatile__ ( "mov %0, r10; " : "=r" ((_error)) ); \
623  __asm__ __volatile__ ( "halt" ); \
624  } while (0)
625 
626 /* end of Fatal Error manager macros */
627 
628 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
629 
630 /* functions */
631 
642 void _CPU_Initialize(void);
643 
644 void *_CPU_Thread_Idle_body( uintptr_t ignored );
645 
662  Context_Control *run,
663  Context_Control *heir
664 );
665 
679  Context_Control *new_context
681 
682 /* XXX this should be possible to remove */
683 #if 0
684 
698  Context_Control_fp **fp_context_ptr
699 );
700 #endif
701 
702 /* XXX this should be possible to remove */
703 #if 0
704 
718  Context_Control_fp **fp_context_ptr
719 );
720 #endif
721 
724 /* FIXME */
726 
727 void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
728 
765 static inline uint32_t CPU_swap_u32(
766  uint32_t value
767 )
768 {
769  unsigned int swapped;
770 
771  #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1)
772  unsigned int v;
773 
774  v = value;
775  __asm__ __volatile__ ("bsw %0, %1" : "=r" (v), "=&r" (swapped) );
776  #else
777  uint32_t byte1, byte2, byte3, byte4;
778 
779  byte4 = (value >> 24) & 0xff;
780  byte3 = (value >> 16) & 0xff;
781  byte2 = (value >> 8) & 0xff;
782  byte1 = value & 0xff;
783 
784  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
785  #endif
786  return swapped;
787 }
788 
799 static inline uint16_t CPU_swap_u16( uint16_t value )
800 {
801  unsigned int swapped;
802 
803  #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1)
804  unsigned int v;
805 
806  v = value;
807  __asm__ __volatile__ ("bsh %0, %1" : "=r" (v), "=&r" (swapped) );
808  #else
809  swapped = ((value & 0xff) << 8) | ((value >> 8) & 0xff);
810  #endif
811  return swapped;
812 }
813 
816 typedef uint32_t CPU_Counter_ticks;
817 
818 uint32_t _CPU_Counter_frequency( void );
819 
820 CPU_Counter_ticks _CPU_Counter_read( void );
821 
822 static inline CPU_Counter_ticks _CPU_Counter_difference(
823  CPU_Counter_ticks second,
824  CPU_Counter_ticks first
825 )
826 {
827  return second - first;
828 }
829 
831 typedef uintptr_t CPU_Uint32ptr;
832 
833 #ifdef __cplusplus
834 }
835 #endif
836 
837 #endif
void _CPU_Exception_frame_print(const CPU_Exception_frame *frame)
Prints the exception frame via printk().
Definition: vectorexceptions.c:45
uint32_t r3_stack_pointer
Definition: cpu.h:253
CPU_Counter_ticks _CPU_Counter_read(void)
Returns the current CPU counter value.
Definition: system-clocks.c:117
Thread register context.
Definition: cpu.h:196
void * _CPU_Thread_Idle_body(uintptr_t ignored)
Definition: idle-mcf5272.c:20
#define RTEMS_INLINE_ROUTINE
Definition: basedefs.h:65
void _CPU_Context_restore_fp(Context_Control_fp **fp_context_ptr)
Definition: cpu.c:207
Interrupt stack frame (ISF).
Definition: cpu.h:306
void _CPU_Context_Initialize(Context_Control *context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
Initializes the CPU context.
Definition: epiphany-context-initialize.c:40
void _CPU_Context_switch(Context_Control *run, Context_Control *heir)
CPU switch context.
Definition: cpu_asm.c:91
void _CPU_Initialize(void)
CPU initialization.
Definition: cpu.c:45
#define CPU_swap_u16(value)
Definition: cpu.h:817
SPARC basic context.
Definition: cpu.h:242
register struct Per_CPU_Control *_SPARC_Per_CPU_current __asm__("g6")
The pointer to the current per-CPU control is available via register g6.
uint32_t CPU_Counter_ticks
Unsigned integer type for CPU counter values.
Definition: cpu.h:1202
#define RTEMS_NO_RETURN
Definition: basedefs.h:101
uint32_t _CPU_ISR_Get_level(void)
Definition: cpu.c:88
V850 Set up Basic CPU Dependency Settings Based on Compiler Settings.
bool _CPU_ISR_Is_enabled(uint32_t level)
Returns true if interrupts are enabled in the specified ISR level, otherwise returns false...
Definition: cpu.h:381
void _CPU_Context_restore(Context_Control *new_context) RTEMS_NO_RETURN
Definition: cpu_asm.c:111
uintptr_t CPU_Uint32ptr
Definition: cpu.h:668
uint32_t _CPU_Counter_frequency(void)
Returns the current CPU counter frequency in Hz.
Definition: system-clocks.c:112
Basic Definitions.
unsigned size
Definition: tte.h:74
unsigned v
Definition: tte.h:73
void _CPU_Context_save_fp(Context_Control_fp **fp_context_ptr)
Definition: cpu.c:198
The set of registers that specifies the complete processor state.
Definition: cpu.h:635