Usbhs Struct Reference

Data Fields
__IO uint32_t	USBHS_DEVCTRL
	(Usbhs Offset: 0x0000) Device General Control Register
__I uint32_t	USBHS_DEVISR
	(Usbhs Offset: 0x0004) Device Global Interrupt Status Register
__O uint32_t	USBHS_DEVICR
	(Usbhs Offset: 0x0008) Device Global Interrupt Clear Register
__O uint32_t	USBHS_DEVIFR
	(Usbhs Offset: 0x000C) Device Global Interrupt Set Register
__I uint32_t	USBHS_DEVIMR
	(Usbhs Offset: 0x0010) Device Global Interrupt Mask Register
__O uint32_t	USBHS_DEVIDR
	(Usbhs Offset: 0x0014) Device Global Interrupt Disable Register
__O uint32_t	USBHS_DEVIER
	(Usbhs Offset: 0x0018) Device Global Interrupt Enable Register
__IO uint32_t	USBHS_DEVEPT
	(Usbhs Offset: 0x001C) Device Endpoint Register
__I uint32_t	USBHS_DEVFNUM
	(Usbhs Offset: 0x0020) Device Frame Number Register
__I uint32_t	Reserved1 [55]
__IO uint32_t	USBHS_DEVEPTCFG [10]
	(Usbhs Offset: 0x100) Device Endpoint Configuration Register (n = 0)
__I uint32_t	Reserved2 [2]
__I uint32_t	USBHS_DEVEPTISR [10]
	(Usbhs Offset: 0x130) Device Endpoint Status Register (n = 0)
__I uint32_t	Reserved3 [2]
__O uint32_t	USBHS_DEVEPTICR [10]
	(Usbhs Offset: 0x160) Device Endpoint Clear Register (n = 0)
__I uint32_t	Reserved4 [2]
__O uint32_t	USBHS_DEVEPTIFR [10]
	(Usbhs Offset: 0x190) Device Endpoint Set Register (n = 0)
__I uint32_t	Reserved5 [2]
__I uint32_t	USBHS_DEVEPTIMR [10]
	(Usbhs Offset: 0x1C0) Device Endpoint Mask Register (n = 0)
__I uint32_t	Reserved6 [2]
__O uint32_t	USBHS_DEVEPTIER [10]
	(Usbhs Offset: 0x1F0) Device Endpoint Enable Register (n = 0)
__I uint32_t	Reserved7 [2]
__O uint32_t	USBHS_DEVEPTIDR [10]
	(Usbhs Offset: 0x220) Device Endpoint Disable Register (n = 0)
__I uint32_t	Reserved8 [50]
UsbhsDevdma	USBHS_DEVDMA [USBHSDEVDMA_NUMBER]
	(Usbhs Offset: 0x310) n = 1 .. 7
__I uint32_t	Reserved9 [32]
__IO uint32_t	USBHS_HSTCTRL
	(Usbhs Offset: 0x0400) Host General Control Register
__I uint32_t	USBHS_HSTISR
	(Usbhs Offset: 0x0404) Host Global Interrupt Status Register
__O uint32_t	USBHS_HSTICR
	(Usbhs Offset: 0x0408) Host Global Interrupt Clear Register
__O uint32_t	USBHS_HSTIFR
	(Usbhs Offset: 0x040C) Host Global Interrupt Set Register
__I uint32_t	USBHS_HSTIMR
	(Usbhs Offset: 0x0410) Host Global Interrupt Mask Register
__O uint32_t	USBHS_HSTIDR
	(Usbhs Offset: 0x0414) Host Global Interrupt Disable Register
__O uint32_t	USBHS_HSTIER
	(Usbhs Offset: 0x0418) Host Global Interrupt Enable Register
__IO uint32_t	USBHS_HSTPIP
	(Usbhs Offset: 0x0041C) Host Pipe Register
__IO uint32_t	USBHS_HSTFNUM
	(Usbhs Offset: 0x0420) Host Frame Number Register
__IO uint32_t	USBHS_HSTADDR1
	(Usbhs Offset: 0x0424) Host Address 1 Register
__IO uint32_t	USBHS_HSTADDR2
	(Usbhs Offset: 0x0428) Host Address 2 Register
__IO uint32_t	USBHS_HSTADDR3
	(Usbhs Offset: 0x042C) Host Address 3 Register
__I uint32_t	Reserved10 [52]
__IO uint32_t	USBHS_HSTPIPCFG [10]
	(Usbhs Offset: 0x500) Host Pipe Configuration Register (n = 0)
__I uint32_t	Reserved11 [2]
__I uint32_t	USBHS_HSTPIPISR [10]
	(Usbhs Offset: 0x530) Host Pipe Status Register (n = 0)
__I uint32_t	Reserved12 [2]
__O uint32_t	USBHS_HSTPIPICR [10]
	(Usbhs Offset: 0x560) Host Pipe Clear Register (n = 0)
__I uint32_t	Reserved13 [2]
__O uint32_t	USBHS_HSTPIPIFR [10]
	(Usbhs Offset: 0x590) Host Pipe Set Register (n = 0)
__I uint32_t	Reserved14 [2]
__I uint32_t	USBHS_HSTPIPIMR [10]
	(Usbhs Offset: 0x5C0) Host Pipe Mask Register (n = 0)
__I uint32_t	Reserved15 [2]
__O uint32_t	USBHS_HSTPIPIER [10]
	(Usbhs Offset: 0x5F0) Host Pipe Enable Register (n = 0)
__I uint32_t	Reserved16 [2]
__O uint32_t	USBHS_HSTPIPIDR [10]
	(Usbhs Offset: 0x620) Host Pipe Disable Register (n = 0)
__I uint32_t	Reserved17 [2]
__IO uint32_t	USBHS_HSTPIPINRQ [10]
	(Usbhs Offset: 0x650) Host Pipe IN Request Register (n = 0)
__I uint32_t	Reserved18 [2]
__IO uint32_t	USBHS_HSTPIPERR [10]
	(Usbhs Offset: 0x680) Host Pipe Error Register (n = 0)
__I uint32_t	Reserved19 [26]
UsbhsHstdma	USBHS_HSTDMA [USBHSHSTDMA_NUMBER]
	(Usbhs Offset: 0x710) n = 1 .. 7
__I uint32_t	Reserved20 [32]
__IO uint32_t	USBHS_CTRL
	(Usbhs Offset: 0x0800) General Control Register
__I uint32_t	USBHS_SR
	(Usbhs Offset: 0x0804) General Status Register
__O uint32_t	USBHS_SCR
	(Usbhs Offset: 0x0808) General Status Clear Register
__O uint32_t	USBHS_SFR
	(Usbhs Offset: 0x080C) General Status Set Register
__IO uint32_t	USBHS_TSTA1
	(Usbhs Offset: 0x0810) General Test A1 Register
__IO uint32_t	USBHS_TSTA2
	(Usbhs Offset: 0x0814) General Test A2 Register
__I uint32_t	USBHS_VERSION
	(Usbhs Offset: 0x0818) General Version Register
__I uint32_t	Reserved21 [4]
__I uint32_t	USBHS_FSM
	(Usbhs Offset: 0x082C) General Finite State Machine Register

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The documentation for this struct was generated from the following file:

• bsps/arm/atsam/include/libchip/include/same70/component/component_usbhs.h