Data Structures
struct	UsbhsDevdma
	UsbhsDevdma hardware registers. More...

struct	UsbhsHstdma
	UsbhsHstdma hardware registers. More...

struct	Usbhs

Macros
#define	USBHSDEVDMA_NUMBER 7
	Usbhs hardware registers.

#define	USBHSHSTDMA_NUMBER 7

#define	USBHS_DEVCTRL_UADD_Pos 0

#define	USBHS_DEVCTRL_UADD_Msk (0x7fu << USBHS_DEVCTRL_UADD_Pos)
	(USBHS_DEVCTRL) USB Address

#define	USBHS_DEVCTRL_UADD(value) ((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos)))

#define	USBHS_DEVCTRL_ADDEN (0x1u << 7)
	(USBHS_DEVCTRL) Address Enable

#define	USBHS_DEVCTRL_DETACH (0x1u << 8)
	(USBHS_DEVCTRL) Detach

#define	USBHS_DEVCTRL_RMWKUP (0x1u << 9)
	(USBHS_DEVCTRL) Remote Wake-Up

#define	USBHS_DEVCTRL_SPDCONF_Pos 10

#define	USBHS_DEVCTRL_SPDCONF_Msk (0x3u << USBHS_DEVCTRL_SPDCONF_Pos)
	(USBHS_DEVCTRL) Mode Configuration

#define	USBHS_DEVCTRL_SPDCONF(value) ((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos)))

#define	USBHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10)
	(USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable.

#define	USBHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10)
	(USBHS_DEVCTRL) For a better consumption, if high speed is not needed.

#define	USBHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10)
	(USBHS_DEVCTRL) Forced high speed.

#define	USBHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10)
	(USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability.

#define	USBHS_DEVCTRL_LS (0x1u << 12)
	(USBHS_DEVCTRL) Low-Speed Mode Force

#define	USBHS_DEVCTRL_TSTJ (0x1u << 13)
	(USBHS_DEVCTRL) Test mode J

#define	USBHS_DEVCTRL_TSTK (0x1u << 14)
	(USBHS_DEVCTRL) Test mode K

#define	USBHS_DEVCTRL_TSTPCKT (0x1u << 15)
	(USBHS_DEVCTRL) Test packet mode

#define	USBHS_DEVCTRL_OPMODE2 (0x1u << 16)
	(USBHS_DEVCTRL) Specific Operational mode

#define	USBHS_DEVISR_SUSP (0x1u << 0)
	(USBHS_DEVISR) Suspend Interrupt

#define	USBHS_DEVISR_MSOF (0x1u << 1)
	(USBHS_DEVISR) Micro Start of Frame Interrupt

#define	USBHS_DEVISR_SOF (0x1u << 2)
	(USBHS_DEVISR) Start of Frame Interrupt

#define	USBHS_DEVISR_EORST (0x1u << 3)
	(USBHS_DEVISR) End of Reset Interrupt

#define	USBHS_DEVISR_WAKEUP (0x1u << 4)
	(USBHS_DEVISR) Wake-Up Interrupt

#define	USBHS_DEVISR_EORSM (0x1u << 5)
	(USBHS_DEVISR) End of Resume Interrupt

#define	USBHS_DEVISR_UPRSM (0x1u << 6)
	(USBHS_DEVISR) Upstream Resume Interrupt

#define	USBHS_DEVISR_PEP_0 (0x1u << 12)
	(USBHS_DEVISR) Endpoint 0 Interrupt

#define	USBHS_DEVISR_PEP_1 (0x1u << 13)
	(USBHS_DEVISR) Endpoint 1 Interrupt

#define	USBHS_DEVISR_PEP_2 (0x1u << 14)
	(USBHS_DEVISR) Endpoint 2 Interrupt

#define	USBHS_DEVISR_PEP_3 (0x1u << 15)
	(USBHS_DEVISR) Endpoint 3 Interrupt

#define	USBHS_DEVISR_PEP_4 (0x1u << 16)
	(USBHS_DEVISR) Endpoint 4 Interrupt

#define	USBHS_DEVISR_PEP_5 (0x1u << 17)
	(USBHS_DEVISR) Endpoint 5 Interrupt

#define	USBHS_DEVISR_PEP_6 (0x1u << 18)
	(USBHS_DEVISR) Endpoint 6 Interrupt

#define	USBHS_DEVISR_PEP_7 (0x1u << 19)
	(USBHS_DEVISR) Endpoint 7 Interrupt

#define	USBHS_DEVISR_PEP_8 (0x1u << 20)
	(USBHS_DEVISR) Endpoint 8 Interrupt

#define	USBHS_DEVISR_PEP_9 (0x1u << 21)
	(USBHS_DEVISR) Endpoint 9 Interrupt

#define	USBHS_DEVISR_PEP_10 (0x1u << 22)
	(USBHS_DEVISR) Endpoint 10 Interrupt

#define	USBHS_DEVISR_PEP_11 (0x1u << 23)
	(USBHS_DEVISR) Endpoint 11 Interrupt

#define	USBHS_DEVISR_DMA_1 (0x1u << 25)
	(USBHS_DEVISR) DMA Channel 1 Interrupt

#define	USBHS_DEVISR_DMA_2 (0x1u << 26)
	(USBHS_DEVISR) DMA Channel 2 Interrupt

#define	USBHS_DEVISR_DMA_3 (0x1u << 27)
	(USBHS_DEVISR) DMA Channel 3 Interrupt

#define	USBHS_DEVISR_DMA_4 (0x1u << 28)
	(USBHS_DEVISR) DMA Channel 4 Interrupt

#define	USBHS_DEVISR_DMA_5 (0x1u << 29)
	(USBHS_DEVISR) DMA Channel 5 Interrupt

#define	USBHS_DEVISR_DMA_6 (0x1u << 30)
	(USBHS_DEVISR) DMA Channel 6 Interrupt

#define	USBHS_DEVISR_DMA_7 (0x1u << 31)
	(USBHS_DEVISR) DMA Channel 7 Interrupt

#define	USBHS_DEVICR_SUSPC (0x1u << 0)
	(USBHS_DEVICR) Suspend Interrupt Clear

#define	USBHS_DEVICR_MSOFC (0x1u << 1)
	(USBHS_DEVICR) Micro Start of Frame Interrupt Clear

#define	USBHS_DEVICR_SOFC (0x1u << 2)
	(USBHS_DEVICR) Start of Frame Interrupt Clear

#define	USBHS_DEVICR_EORSTC (0x1u << 3)
	(USBHS_DEVICR) End of Reset Interrupt Clear

#define	USBHS_DEVICR_WAKEUPC (0x1u << 4)
	(USBHS_DEVICR) Wake-Up Interrupt Clear

#define	USBHS_DEVICR_EORSMC (0x1u << 5)
	(USBHS_DEVICR) End of Resume Interrupt Clear

#define	USBHS_DEVICR_UPRSMC (0x1u << 6)
	(USBHS_DEVICR) Upstream Resume Interrupt Clear

#define	USBHS_DEVIFR_SUSPS (0x1u << 0)
	(USBHS_DEVIFR) Suspend Interrupt Set

#define	USBHS_DEVIFR_MSOFS (0x1u << 1)
	(USBHS_DEVIFR) Micro Start of Frame Interrupt Set

#define	USBHS_DEVIFR_SOFS (0x1u << 2)
	(USBHS_DEVIFR) Start of Frame Interrupt Set

#define	USBHS_DEVIFR_EORSTS (0x1u << 3)
	(USBHS_DEVIFR) End of Reset Interrupt Set

#define	USBHS_DEVIFR_WAKEUPS (0x1u << 4)
	(USBHS_DEVIFR) Wake-Up Interrupt Set

#define	USBHS_DEVIFR_EORSMS (0x1u << 5)
	(USBHS_DEVIFR) End of Resume Interrupt Set

#define	USBHS_DEVIFR_UPRSMS (0x1u << 6)
	(USBHS_DEVIFR) Upstream Resume Interrupt Set

#define	USBHS_DEVIFR_DMA_1 (0x1u << 25)
	(USBHS_DEVIFR) DMA Channel 1 Interrupt Set

#define	USBHS_DEVIFR_DMA_2 (0x1u << 26)
	(USBHS_DEVIFR) DMA Channel 2 Interrupt Set

#define	USBHS_DEVIFR_DMA_3 (0x1u << 27)
	(USBHS_DEVIFR) DMA Channel 3 Interrupt Set

#define	USBHS_DEVIFR_DMA_4 (0x1u << 28)
	(USBHS_DEVIFR) DMA Channel 4 Interrupt Set

#define	USBHS_DEVIFR_DMA_5 (0x1u << 29)
	(USBHS_DEVIFR) DMA Channel 5 Interrupt Set

#define	USBHS_DEVIFR_DMA_6 (0x1u << 30)
	(USBHS_DEVIFR) DMA Channel 6 Interrupt Set

#define	USBHS_DEVIFR_DMA_7 (0x1u << 31)
	(USBHS_DEVIFR) DMA Channel 7 Interrupt Set

#define	USBHS_DEVIMR_SUSPE (0x1u << 0)
	(USBHS_DEVIMR) Suspend Interrupt Mask

#define	USBHS_DEVIMR_MSOFE (0x1u << 1)
	(USBHS_DEVIMR) Micro Start of Frame Interrupt Mask

#define	USBHS_DEVIMR_SOFE (0x1u << 2)
	(USBHS_DEVIMR) Start of Frame Interrupt Mask

#define	USBHS_DEVIMR_EORSTE (0x1u << 3)
	(USBHS_DEVIMR) End of Reset Interrupt Mask

#define	USBHS_DEVIMR_WAKEUPE (0x1u << 4)
	(USBHS_DEVIMR) Wake-Up Interrupt Mask

#define	USBHS_DEVIMR_EORSME (0x1u << 5)
	(USBHS_DEVIMR) End of Resume Interrupt Mask

#define	USBHS_DEVIMR_UPRSME (0x1u << 6)
	(USBHS_DEVIMR) Upstream Resume Interrupt Mask

#define	USBHS_DEVIMR_PEP_0 (0x1u << 12)
	(USBHS_DEVIMR) Endpoint 0 Interrupt Mask

#define	USBHS_DEVIMR_PEP_1 (0x1u << 13)
	(USBHS_DEVIMR) Endpoint 1 Interrupt Mask

#define	USBHS_DEVIMR_PEP_2 (0x1u << 14)
	(USBHS_DEVIMR) Endpoint 2 Interrupt Mask

#define	USBHS_DEVIMR_PEP_3 (0x1u << 15)
	(USBHS_DEVIMR) Endpoint 3 Interrupt Mask

#define	USBHS_DEVIMR_PEP_4 (0x1u << 16)
	(USBHS_DEVIMR) Endpoint 4 Interrupt Mask

#define	USBHS_DEVIMR_PEP_5 (0x1u << 17)
	(USBHS_DEVIMR) Endpoint 5 Interrupt Mask

#define	USBHS_DEVIMR_PEP_6 (0x1u << 18)
	(USBHS_DEVIMR) Endpoint 6 Interrupt Mask

#define	USBHS_DEVIMR_PEP_7 (0x1u << 19)
	(USBHS_DEVIMR) Endpoint 7 Interrupt Mask

#define	USBHS_DEVIMR_PEP_8 (0x1u << 20)
	(USBHS_DEVIMR) Endpoint 8 Interrupt Mask

#define	USBHS_DEVIMR_PEP_9 (0x1u << 21)
	(USBHS_DEVIMR) Endpoint 9 Interrupt Mask

#define	USBHS_DEVIMR_PEP_10 (0x1u << 22)
	(USBHS_DEVIMR) Endpoint 10 Interrupt Mask

#define	USBHS_DEVIMR_PEP_11 (0x1u << 23)
	(USBHS_DEVIMR) Endpoint 11 Interrupt Mask

#define	USBHS_DEVIMR_DMA_1 (0x1u << 25)
	(USBHS_DEVIMR) DMA Channel 1 Interrupt Mask

#define	USBHS_DEVIMR_DMA_2 (0x1u << 26)
	(USBHS_DEVIMR) DMA Channel 2 Interrupt Mask

#define	USBHS_DEVIMR_DMA_3 (0x1u << 27)
	(USBHS_DEVIMR) DMA Channel 3 Interrupt Mask

#define	USBHS_DEVIMR_DMA_4 (0x1u << 28)
	(USBHS_DEVIMR) DMA Channel 4 Interrupt Mask

#define	USBHS_DEVIMR_DMA_5 (0x1u << 29)
	(USBHS_DEVIMR) DMA Channel 5 Interrupt Mask

#define	USBHS_DEVIMR_DMA_6 (0x1u << 30)
	(USBHS_DEVIMR) DMA Channel 6 Interrupt Mask

#define	USBHS_DEVIMR_DMA_7 (0x1u << 31)
	(USBHS_DEVIMR) DMA Channel 7 Interrupt Mask

#define	USBHS_DEVIDR_SUSPEC (0x1u << 0)
	(USBHS_DEVIDR) Suspend Interrupt Disable

#define	USBHS_DEVIDR_MSOFEC (0x1u << 1)
	(USBHS_DEVIDR) Micro Start of Frame Interrupt Disable

#define	USBHS_DEVIDR_SOFEC (0x1u << 2)
	(USBHS_DEVIDR) Start of Frame Interrupt Disable

#define	USBHS_DEVIDR_EORSTEC (0x1u << 3)
	(USBHS_DEVIDR) End of Reset Interrupt Disable

#define	USBHS_DEVIDR_WAKEUPEC (0x1u << 4)
	(USBHS_DEVIDR) Wake-Up Interrupt Disable

#define	USBHS_DEVIDR_EORSMEC (0x1u << 5)
	(USBHS_DEVIDR) End of Resume Interrupt Disable

#define	USBHS_DEVIDR_UPRSMEC (0x1u << 6)
	(USBHS_DEVIDR) Upstream Resume Interrupt Disable

#define	USBHS_DEVIDR_PEP_0 (0x1u << 12)
	(USBHS_DEVIDR) Endpoint 0 Interrupt Disable

#define	USBHS_DEVIDR_PEP_1 (0x1u << 13)
	(USBHS_DEVIDR) Endpoint 1 Interrupt Disable

#define	USBHS_DEVIDR_PEP_2 (0x1u << 14)
	(USBHS_DEVIDR) Endpoint 2 Interrupt Disable

#define	USBHS_DEVIDR_PEP_3 (0x1u << 15)
	(USBHS_DEVIDR) Endpoint 3 Interrupt Disable

#define	USBHS_DEVIDR_PEP_4 (0x1u << 16)
	(USBHS_DEVIDR) Endpoint 4 Interrupt Disable

#define	USBHS_DEVIDR_PEP_5 (0x1u << 17)
	(USBHS_DEVIDR) Endpoint 5 Interrupt Disable

#define	USBHS_DEVIDR_PEP_6 (0x1u << 18)
	(USBHS_DEVIDR) Endpoint 6 Interrupt Disable

#define	USBHS_DEVIDR_PEP_7 (0x1u << 19)
	(USBHS_DEVIDR) Endpoint 7 Interrupt Disable

#define	USBHS_DEVIDR_PEP_8 (0x1u << 20)
	(USBHS_DEVIDR) Endpoint 8 Interrupt Disable

#define	USBHS_DEVIDR_PEP_9 (0x1u << 21)
	(USBHS_DEVIDR) Endpoint 9 Interrupt Disable

#define	USBHS_DEVIDR_PEP_10 (0x1u << 22)
	(USBHS_DEVIDR) Endpoint 10 Interrupt Disable

#define	USBHS_DEVIDR_PEP_11 (0x1u << 23)
	(USBHS_DEVIDR) Endpoint 11 Interrupt Disable

#define	USBHS_DEVIDR_DMA_1 (0x1u << 25)
	(USBHS_DEVIDR) DMA Channel 1 Interrupt Disable

#define	USBHS_DEVIDR_DMA_2 (0x1u << 26)
	(USBHS_DEVIDR) DMA Channel 2 Interrupt Disable

#define	USBHS_DEVIDR_DMA_3 (0x1u << 27)
	(USBHS_DEVIDR) DMA Channel 3 Interrupt Disable

#define	USBHS_DEVIDR_DMA_4 (0x1u << 28)
	(USBHS_DEVIDR) DMA Channel 4 Interrupt Disable

#define	USBHS_DEVIDR_DMA_5 (0x1u << 29)
	(USBHS_DEVIDR) DMA Channel 5 Interrupt Disable

#define	USBHS_DEVIDR_DMA_6 (0x1u << 30)
	(USBHS_DEVIDR) DMA Channel 6 Interrupt Disable

#define	USBHS_DEVIDR_DMA_7 (0x1u << 31)
	(USBHS_DEVIDR) DMA Channel 7 Interrupt Disable

#define	USBHS_DEVIER_SUSPES (0x1u << 0)
	(USBHS_DEVIER) Suspend Interrupt Enable

#define	USBHS_DEVIER_MSOFES (0x1u << 1)
	(USBHS_DEVIER) Micro Start of Frame Interrupt Enable

#define	USBHS_DEVIER_SOFES (0x1u << 2)
	(USBHS_DEVIER) Start of Frame Interrupt Enable

#define	USBHS_DEVIER_EORSTES (0x1u << 3)
	(USBHS_DEVIER) End of Reset Interrupt Enable

#define	USBHS_DEVIER_WAKEUPES (0x1u << 4)
	(USBHS_DEVIER) Wake-Up Interrupt Enable

#define	USBHS_DEVIER_EORSMES (0x1u << 5)
	(USBHS_DEVIER) End of Resume Interrupt Enable

#define	USBHS_DEVIER_UPRSMES (0x1u << 6)
	(USBHS_DEVIER) Upstream Resume Interrupt Enable

#define	USBHS_DEVIER_PEP_0 (0x1u << 12)
	(USBHS_DEVIER) Endpoint 0 Interrupt Enable

#define	USBHS_DEVIER_PEP_1 (0x1u << 13)
	(USBHS_DEVIER) Endpoint 1 Interrupt Enable

#define	USBHS_DEVIER_PEP_2 (0x1u << 14)
	(USBHS_DEVIER) Endpoint 2 Interrupt Enable

#define	USBHS_DEVIER_PEP_3 (0x1u << 15)
	(USBHS_DEVIER) Endpoint 3 Interrupt Enable

#define	USBHS_DEVIER_PEP_4 (0x1u << 16)
	(USBHS_DEVIER) Endpoint 4 Interrupt Enable

#define	USBHS_DEVIER_PEP_5 (0x1u << 17)
	(USBHS_DEVIER) Endpoint 5 Interrupt Enable

#define	USBHS_DEVIER_PEP_6 (0x1u << 18)
	(USBHS_DEVIER) Endpoint 6 Interrupt Enable

#define	USBHS_DEVIER_PEP_7 (0x1u << 19)
	(USBHS_DEVIER) Endpoint 7 Interrupt Enable

#define	USBHS_DEVIER_PEP_8 (0x1u << 20)
	(USBHS_DEVIER) Endpoint 8 Interrupt Enable

#define	USBHS_DEVIER_PEP_9 (0x1u << 21)
	(USBHS_DEVIER) Endpoint 9 Interrupt Enable

#define	USBHS_DEVIER_PEP_10 (0x1u << 22)
	(USBHS_DEVIER) Endpoint 10 Interrupt Enable

#define	USBHS_DEVIER_PEP_11 (0x1u << 23)
	(USBHS_DEVIER) Endpoint 11 Interrupt Enable

#define	USBHS_DEVIER_DMA_1 (0x1u << 25)
	(USBHS_DEVIER) DMA Channel 1 Interrupt Enable

#define	USBHS_DEVIER_DMA_2 (0x1u << 26)
	(USBHS_DEVIER) DMA Channel 2 Interrupt Enable

#define	USBHS_DEVIER_DMA_3 (0x1u << 27)
	(USBHS_DEVIER) DMA Channel 3 Interrupt Enable

#define	USBHS_DEVIER_DMA_4 (0x1u << 28)
	(USBHS_DEVIER) DMA Channel 4 Interrupt Enable

#define	USBHS_DEVIER_DMA_5 (0x1u << 29)
	(USBHS_DEVIER) DMA Channel 5 Interrupt Enable

#define	USBHS_DEVIER_DMA_6 (0x1u << 30)
	(USBHS_DEVIER) DMA Channel 6 Interrupt Enable

#define	USBHS_DEVIER_DMA_7 (0x1u << 31)
	(USBHS_DEVIER) DMA Channel 7 Interrupt Enable

#define	USBHS_DEVEPT_EPEN0 (0x1u << 0)
	(USBHS_DEVEPT) Endpoint 0 Enable

#define	USBHS_DEVEPT_EPEN1 (0x1u << 1)
	(USBHS_DEVEPT) Endpoint 1 Enable

#define	USBHS_DEVEPT_EPEN2 (0x1u << 2)
	(USBHS_DEVEPT) Endpoint 2 Enable

#define	USBHS_DEVEPT_EPEN3 (0x1u << 3)
	(USBHS_DEVEPT) Endpoint 3 Enable

#define	USBHS_DEVEPT_EPEN4 (0x1u << 4)
	(USBHS_DEVEPT) Endpoint 4 Enable

#define	USBHS_DEVEPT_EPEN5 (0x1u << 5)
	(USBHS_DEVEPT) Endpoint 5 Enable

#define	USBHS_DEVEPT_EPEN6 (0x1u << 6)
	(USBHS_DEVEPT) Endpoint 6 Enable

#define	USBHS_DEVEPT_EPEN7 (0x1u << 7)
	(USBHS_DEVEPT) Endpoint 7 Enable

#define	USBHS_DEVEPT_EPEN8 (0x1u << 8)
	(USBHS_DEVEPT) Endpoint 8 Enable

#define	USBHS_DEVEPT_EPRST0 (0x1u << 16)
	(USBHS_DEVEPT) Endpoint 0 Reset

#define	USBHS_DEVEPT_EPRST1 (0x1u << 17)
	(USBHS_DEVEPT) Endpoint 1 Reset

#define	USBHS_DEVEPT_EPRST2 (0x1u << 18)
	(USBHS_DEVEPT) Endpoint 2 Reset

#define	USBHS_DEVEPT_EPRST3 (0x1u << 19)
	(USBHS_DEVEPT) Endpoint 3 Reset

#define	USBHS_DEVEPT_EPRST4 (0x1u << 20)
	(USBHS_DEVEPT) Endpoint 4 Reset

#define	USBHS_DEVEPT_EPRST5 (0x1u << 21)
	(USBHS_DEVEPT) Endpoint 5 Reset

#define	USBHS_DEVEPT_EPRST6 (0x1u << 22)
	(USBHS_DEVEPT) Endpoint 6 Reset

#define	USBHS_DEVEPT_EPRST7 (0x1u << 23)
	(USBHS_DEVEPT) Endpoint 7 Reset

#define	USBHS_DEVEPT_EPRST8 (0x1u << 24)
	(USBHS_DEVEPT) Endpoint 8 Reset

#define	USBHS_DEVFNUM_MFNUM_Pos 0

#define	USBHS_DEVFNUM_MFNUM_Msk (0x7u << USBHS_DEVFNUM_MFNUM_Pos)
	(USBHS_DEVFNUM) Micro Frame Number

#define	USBHS_DEVFNUM_FNUM_Pos 3

#define	USBHS_DEVFNUM_FNUM_Msk (0x7ffu << USBHS_DEVFNUM_FNUM_Pos)
	(USBHS_DEVFNUM) Frame Number

#define	USBHS_DEVFNUM_FNCERR (0x1u << 15)
	(USBHS_DEVFNUM) Frame Number CRC Error

#define	USBHS_DEVEPTCFG_ALLOC (0x1u << 1)
	(USBHS_DEVEPTCFG[10]) Endpoint Memory Allocate

#define	USBHS_DEVEPTCFG_EPBK_Pos 2

#define	USBHS_DEVEPTCFG_EPBK_Msk (0x3u << USBHS_DEVEPTCFG_EPBK_Pos)
	(USBHS_DEVEPTCFG[10]) Endpoint Banks

#define	USBHS_DEVEPTCFG_EPBK(value) ((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos)))

#define	USBHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2)
	(USBHS_DEVEPTCFG[10]) Single-bank endpoint

#define	USBHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2)
	(USBHS_DEVEPTCFG[10]) Double-bank endpoint

#define	USBHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2)
	(USBHS_DEVEPTCFG[10]) Triple-bank endpoint

#define	USBHS_DEVEPTCFG_EPSIZE_Pos 4

#define	USBHS_DEVEPTCFG_EPSIZE_Msk (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos)
	(USBHS_DEVEPTCFG[10]) Endpoint Size

#define	USBHS_DEVEPTCFG_EPSIZE(value) ((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos)))

#define	USBHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4)
	(USBHS_DEVEPTCFG[10]) 8 bytes

#define	USBHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4)
	(USBHS_DEVEPTCFG[10]) 16 bytes

#define	USBHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4)
	(USBHS_DEVEPTCFG[10]) 32 bytes

#define	USBHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4)
	(USBHS_DEVEPTCFG[10]) 64 bytes

#define	USBHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4)
	(USBHS_DEVEPTCFG[10]) 128 bytes

#define	USBHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4)
	(USBHS_DEVEPTCFG[10]) 256 bytes

#define	USBHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4)
	(USBHS_DEVEPTCFG[10]) 512 bytes

#define	USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4)
	(USBHS_DEVEPTCFG[10]) 1024 bytes

#define	USBHS_DEVEPTCFG_EPDIR (0x1u << 8)
	(USBHS_DEVEPTCFG[10]) Endpoint Direction

#define	USBHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8)
	(USBHS_DEVEPTCFG[10]) The endpoint direction is OUT.

#define	USBHS_DEVEPTCFG_EPDIR_IN (0x1u << 8)
	(USBHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints).

#define	USBHS_DEVEPTCFG_AUTOSW (0x1u << 9)
	(USBHS_DEVEPTCFG[10]) Automatic Switch

#define	USBHS_DEVEPTCFG_EPTYPE_Pos 11

#define	USBHS_DEVEPTCFG_EPTYPE_Msk (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos)
	(USBHS_DEVEPTCFG[10]) Endpoint Type

#define	USBHS_DEVEPTCFG_EPTYPE(value) ((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos)))

#define	USBHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11)
	(USBHS_DEVEPTCFG[10]) Control

#define	USBHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11)
	(USBHS_DEVEPTCFG[10]) Isochronous

#define	USBHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11)
	(USBHS_DEVEPTCFG[10]) Bulk

#define	USBHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11)
	(USBHS_DEVEPTCFG[10]) Interrupt

#define	USBHS_DEVEPTCFG_NBTRANS_Pos 13

#define	USBHS_DEVEPTCFG_NBTRANS_Msk (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos)
	(USBHS_DEVEPTCFG[10]) Number of transactions per microframe for isochronous endpoint

#define	USBHS_DEVEPTCFG_NBTRANS(value) ((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos)))

#define	USBHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13)
	(USBHS_DEVEPTCFG[10]) Reserved to endpoint that does not have the high-bandwidth isochronous capability.

#define	USBHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13)
	(USBHS_DEVEPTCFG[10]) Default value: one transaction per microframe.

#define	USBHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13)
	(USBHS_DEVEPTCFG[10]) Two transactions per microframe. This endpoint should be configured as double-bank.

#define	USBHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13)
	(USBHS_DEVEPTCFG[10]) Three transactions per microframe. This endpoint should be configured as triple-bank.

#define	USBHS_DEVEPTISR_TXINI (0x1u << 0)
	(USBHS_DEVEPTISR[10]) Transmitted IN Data Interrupt

#define	USBHS_DEVEPTISR_RXOUTI (0x1u << 1)
	(USBHS_DEVEPTISR[10]) Received OUT Data Interrupt

#define	USBHS_DEVEPTISR_RXSTPI (0x1u << 2)
	(USBHS_DEVEPTISR[10]) Received SETUP Interrupt

#define	USBHS_DEVEPTISR_NAKOUTI (0x1u << 3)
	(USBHS_DEVEPTISR[10]) NAKed OUT Interrupt

#define	USBHS_DEVEPTISR_NAKINI (0x1u << 4)
	(USBHS_DEVEPTISR[10]) NAKed IN Interrupt

#define	USBHS_DEVEPTISR_OVERFI (0x1u << 5)
	(USBHS_DEVEPTISR[10]) Overflow Interrupt

#define	USBHS_DEVEPTISR_STALLEDI (0x1u << 6)
	(USBHS_DEVEPTISR[10]) STALLed Interrupt

#define	USBHS_DEVEPTISR_SHORTPACKET (0x1u << 7)
	(USBHS_DEVEPTISR[10]) Short Packet Interrupt

#define	USBHS_DEVEPTISR_DTSEQ_Pos 8

#define	USBHS_DEVEPTISR_DTSEQ_Msk (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos)
	(USBHS_DEVEPTISR[10]) Data Toggle Sequence

#define	USBHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8)
	(USBHS_DEVEPTISR[10]) Data0 toggle sequence

#define	USBHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8)
	(USBHS_DEVEPTISR[10]) Data1 toggle sequence

#define	USBHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8)
	(USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint

#define	USBHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8)
	(USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint

#define	USBHS_DEVEPTISR_NBUSYBK_Pos 12

#define	USBHS_DEVEPTISR_NBUSYBK_Msk (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos)
	(USBHS_DEVEPTISR[10]) Number of Busy Banks

#define	USBHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12)
	(USBHS_DEVEPTISR[10]) 0 busy bank (all banks free)

#define	USBHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12)
	(USBHS_DEVEPTISR[10]) 1 busy bank

#define	USBHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12)
	(USBHS_DEVEPTISR[10]) 2 busy banks

#define	USBHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12)
	(USBHS_DEVEPTISR[10]) 3 busy banks

#define	USBHS_DEVEPTISR_CURRBK_Pos 14

#define	USBHS_DEVEPTISR_CURRBK_Msk (0x3u << USBHS_DEVEPTISR_CURRBK_Pos)
	(USBHS_DEVEPTISR[10]) Current Bank

#define	USBHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14)
	(USBHS_DEVEPTISR[10]) Current bank is bank0

#define	USBHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14)
	(USBHS_DEVEPTISR[10]) Current bank is bank1

#define	USBHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14)
	(USBHS_DEVEPTISR[10]) Current bank is bank2

#define	USBHS_DEVEPTISR_RWALL (0x1u << 16)
	(USBHS_DEVEPTISR[10]) Read/Write Allowed

#define	USBHS_DEVEPTISR_CTRLDIR (0x1u << 17)
	(USBHS_DEVEPTISR[10]) Control Direction

#define	USBHS_DEVEPTISR_CFGOK (0x1u << 18)
	(USBHS_DEVEPTISR[10]) Configuration OK Status

#define	USBHS_DEVEPTISR_BYCT_Pos 20

#define	USBHS_DEVEPTISR_BYCT_Msk (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos)
	(USBHS_DEVEPTISR[10]) Byte Count

#define	USBHS_DEVEPTISR_UNDERFI (0x1u << 2)
	(USBHS_DEVEPTISR[10]) Underflow Interrupt

#define	USBHS_DEVEPTISR_HBISOINERRI (0x1u << 3)
	(USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt

#define	USBHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4)
	(USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt

#define	USBHS_DEVEPTISR_CRCERRI (0x1u << 6)
	(USBHS_DEVEPTISR[10]) CRC Error Interrupt

#define	USBHS_DEVEPTISR_ERRORTRANS (0x1u << 10)
	(USBHS_DEVEPTISR[10]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt

#define	USBHS_DEVEPTICR_TXINIC (0x1u << 0)
	(USBHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear

#define	USBHS_DEVEPTICR_RXOUTIC (0x1u << 1)
	(USBHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear

#define	USBHS_DEVEPTICR_RXSTPIC (0x1u << 2)
	(USBHS_DEVEPTICR[10]) Received SETUP Interrupt Clear

#define	USBHS_DEVEPTICR_NAKOUTIC (0x1u << 3)
	(USBHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear

#define	USBHS_DEVEPTICR_NAKINIC (0x1u << 4)
	(USBHS_DEVEPTICR[10]) NAKed IN Interrupt Clear

#define	USBHS_DEVEPTICR_OVERFIC (0x1u << 5)
	(USBHS_DEVEPTICR[10]) Overflow Interrupt Clear

#define	USBHS_DEVEPTICR_STALLEDIC (0x1u << 6)
	(USBHS_DEVEPTICR[10]) STALLed Interrupt Clear

#define	USBHS_DEVEPTICR_SHORTPACKETC (0x1u << 7)
	(USBHS_DEVEPTICR[10]) Short Packet Interrupt Clear

#define	USBHS_DEVEPTICR_UNDERFIC (0x1u << 2)
	(USBHS_DEVEPTICR[10]) Underflow Interrupt Clear

#define	USBHS_DEVEPTICR_HBISOINERRIC (0x1u << 3)
	(USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Clear

#define	USBHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4)
	(USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear

#define	USBHS_DEVEPTICR_CRCERRIC (0x1u << 6)
	(USBHS_DEVEPTICR[10]) CRC Error Interrupt Clear

#define	USBHS_DEVEPTIFR_TXINIS (0x1u << 0)
	(USBHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set

#define	USBHS_DEVEPTIFR_RXOUTIS (0x1u << 1)
	(USBHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set

#define	USBHS_DEVEPTIFR_RXSTPIS (0x1u << 2)
	(USBHS_DEVEPTIFR[10]) Received SETUP Interrupt Set

#define	USBHS_DEVEPTIFR_NAKOUTIS (0x1u << 3)
	(USBHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set

#define	USBHS_DEVEPTIFR_NAKINIS (0x1u << 4)
	(USBHS_DEVEPTIFR[10]) NAKed IN Interrupt Set

#define	USBHS_DEVEPTIFR_OVERFIS (0x1u << 5)
	(USBHS_DEVEPTIFR[10]) Overflow Interrupt Set

#define	USBHS_DEVEPTIFR_STALLEDIS (0x1u << 6)
	(USBHS_DEVEPTIFR[10]) STALLed Interrupt Set

#define	USBHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7)
	(USBHS_DEVEPTIFR[10]) Short Packet Interrupt Set

#define	USBHS_DEVEPTIFR_NBUSYBKS (0x1u << 12)
	(USBHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set

#define	USBHS_DEVEPTIFR_UNDERFIS (0x1u << 2)
	(USBHS_DEVEPTIFR[10]) Underflow Interrupt Set

#define	USBHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3)
	(USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Set

#define	USBHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4)
	(USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set

#define	USBHS_DEVEPTIFR_CRCERRIS (0x1u << 6)
	(USBHS_DEVEPTIFR[10]) CRC Error Interrupt Set

#define	USBHS_DEVEPTIMR_TXINE (0x1u << 0)
	(USBHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt

#define	USBHS_DEVEPTIMR_RXOUTE (0x1u << 1)
	(USBHS_DEVEPTIMR[10]) Received OUT Data Interrupt

#define	USBHS_DEVEPTIMR_RXSTPE (0x1u << 2)
	(USBHS_DEVEPTIMR[10]) Received SETUP Interrupt

#define	USBHS_DEVEPTIMR_NAKOUTE (0x1u << 3)
	(USBHS_DEVEPTIMR[10]) NAKed OUT Interrupt

#define	USBHS_DEVEPTIMR_NAKINE (0x1u << 4)
	(USBHS_DEVEPTIMR[10]) NAKed IN Interrupt

#define	USBHS_DEVEPTIMR_OVERFE (0x1u << 5)
	(USBHS_DEVEPTIMR[10]) Overflow Interrupt

#define	USBHS_DEVEPTIMR_STALLEDE (0x1u << 6)
	(USBHS_DEVEPTIMR[10]) STALLed Interrupt

#define	USBHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7)
	(USBHS_DEVEPTIMR[10]) Short Packet Interrupt

#define	USBHS_DEVEPTIMR_NBUSYBKE (0x1u << 12)
	(USBHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt

#define	USBHS_DEVEPTIMR_KILLBK (0x1u << 13)
	(USBHS_DEVEPTIMR[10]) Kill IN Bank

#define	USBHS_DEVEPTIMR_FIFOCON (0x1u << 14)
	(USBHS_DEVEPTIMR[10]) FIFO Control

#define	USBHS_DEVEPTIMR_EPDISHDMA (0x1u << 16)
	(USBHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request

#define	USBHS_DEVEPTIMR_NYETDIS (0x1u << 17)
	(USBHS_DEVEPTIMR[10]) NYET Token Disable

#define	USBHS_DEVEPTIMR_RSTDT (0x1u << 18)
	(USBHS_DEVEPTIMR[10]) Reset Data Toggle

#define	USBHS_DEVEPTIMR_STALLRQ (0x1u << 19)
	(USBHS_DEVEPTIMR[10]) STALL Request

#define	USBHS_DEVEPTIMR_UNDERFE (0x1u << 2)
	(USBHS_DEVEPTIMR[10]) Underflow Interrupt

#define	USBHS_DEVEPTIMR_HBISOINERRE (0x1u << 3)
	(USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt

#define	USBHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4)
	(USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt

#define	USBHS_DEVEPTIMR_CRCERRE (0x1u << 6)
	(USBHS_DEVEPTIMR[10]) CRC Error Interrupt

#define	USBHS_DEVEPTIMR_MDATAE (0x1u << 8)
	(USBHS_DEVEPTIMR[10]) MData Interrupt

#define	USBHS_DEVEPTIMR_DATAXE (0x1u << 9)
	(USBHS_DEVEPTIMR[10]) DataX Interrupt

#define	USBHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10)
	(USBHS_DEVEPTIMR[10]) Transaction Error Interrupt

#define	USBHS_DEVEPTIER_TXINES (0x1u << 0)
	(USBHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable

#define	USBHS_DEVEPTIER_RXOUTES (0x1u << 1)
	(USBHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable

#define	USBHS_DEVEPTIER_RXSTPES (0x1u << 2)
	(USBHS_DEVEPTIER[10]) Received SETUP Interrupt Enable

#define	USBHS_DEVEPTIER_NAKOUTES (0x1u << 3)
	(USBHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable

#define	USBHS_DEVEPTIER_NAKINES (0x1u << 4)
	(USBHS_DEVEPTIER[10]) NAKed IN Interrupt Enable

#define	USBHS_DEVEPTIER_OVERFES (0x1u << 5)
	(USBHS_DEVEPTIER[10]) Overflow Interrupt Enable

#define	USBHS_DEVEPTIER_STALLEDES (0x1u << 6)
	(USBHS_DEVEPTIER[10]) STALLed Interrupt Enable

#define	USBHS_DEVEPTIER_SHORTPACKETES (0x1u << 7)
	(USBHS_DEVEPTIER[10]) Short Packet Interrupt Enable

#define	USBHS_DEVEPTIER_NBUSYBKES (0x1u << 12)
	(USBHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable

#define	USBHS_DEVEPTIER_KILLBKS (0x1u << 13)
	(USBHS_DEVEPTIER[10]) Kill IN Bank

#define	USBHS_DEVEPTIER_FIFOCONS (0x1u << 14)
	(USBHS_DEVEPTIER[10]) FIFO Control

#define	USBHS_DEVEPTIER_EPDISHDMAS (0x1u << 16)
	(USBHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable

#define	USBHS_DEVEPTIER_NYETDISS (0x1u << 17)
	(USBHS_DEVEPTIER[10]) NYET Token Disable Enable

#define	USBHS_DEVEPTIER_RSTDTS (0x1u << 18)
	(USBHS_DEVEPTIER[10]) Reset Data Toggle Enable

#define	USBHS_DEVEPTIER_STALLRQS (0x1u << 19)
	(USBHS_DEVEPTIER[10]) STALL Request Enable

#define	USBHS_DEVEPTIER_UNDERFES (0x1u << 2)
	(USBHS_DEVEPTIER[10]) Underflow Interrupt Enable

#define	USBHS_DEVEPTIER_HBISOINERRES (0x1u << 3)
	(USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable

#define	USBHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4)
	(USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable

#define	USBHS_DEVEPTIER_CRCERRES (0x1u << 6)
	(USBHS_DEVEPTIER[10]) CRC Error Interrupt Enable

#define	USBHS_DEVEPTIER_MDATAES (0x1u << 8)
	(USBHS_DEVEPTIER[10]) MData Interrupt Enable

#define	USBHS_DEVEPTIER_DATAXES (0x1u << 9)
	(USBHS_DEVEPTIER[10]) DataX Interrupt Enable

#define	USBHS_DEVEPTIER_ERRORTRANSES (0x1u << 10)
	(USBHS_DEVEPTIER[10]) Transaction Error Interrupt Enable

#define	USBHS_DEVEPTIDR_TXINEC (0x1u << 0)
	(USBHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear

#define	USBHS_DEVEPTIDR_RXOUTEC (0x1u << 1)
	(USBHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear

#define	USBHS_DEVEPTIDR_RXSTPEC (0x1u << 2)
	(USBHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear

#define	USBHS_DEVEPTIDR_NAKOUTEC (0x1u << 3)
	(USBHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear

#define	USBHS_DEVEPTIDR_NAKINEC (0x1u << 4)
	(USBHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear

#define	USBHS_DEVEPTIDR_OVERFEC (0x1u << 5)
	(USBHS_DEVEPTIDR[10]) Overflow Interrupt Clear

#define	USBHS_DEVEPTIDR_STALLEDEC (0x1u << 6)
	(USBHS_DEVEPTIDR[10]) STALLed Interrupt Clear

#define	USBHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7)
	(USBHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear

#define	USBHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12)
	(USBHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear

#define	USBHS_DEVEPTIDR_FIFOCONC (0x1u << 14)
	(USBHS_DEVEPTIDR[10]) FIFO Control Clear

#define	USBHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16)
	(USBHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear

#define	USBHS_DEVEPTIDR_NYETDISC (0x1u << 17)
	(USBHS_DEVEPTIDR[10]) NYET Token Disable Clear

#define	USBHS_DEVEPTIDR_STALLRQC (0x1u << 19)
	(USBHS_DEVEPTIDR[10]) STALL Request Clear

#define	USBHS_DEVEPTIDR_UNDERFEC (0x1u << 2)
	(USBHS_DEVEPTIDR[10]) Underflow Interrupt Clear

#define	USBHS_DEVEPTIDR_HBISOINERREC (0x1u << 3)
	(USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear

#define	USBHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4)
	(USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear

#define	USBHS_DEVEPTIDR_CRCERREC (0x1u << 6)
	(USBHS_DEVEPTIDR[10]) CRC Error Interrupt Clear

#define	USBHS_DEVEPTIDR_MDATEC (0x1u << 8)
	(USBHS_DEVEPTIDR[10]) MData Interrupt Clear

#define	USBHS_DEVEPTIDR_DATAXEC (0x1u << 9)
	(USBHS_DEVEPTIDR[10]) DataX Interrupt Clear

#define	USBHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10)
	(USBHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear

#define	USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0

#define	USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)
	(USBHS_DEVDMANXTDSC) Next Descriptor Address

#define	USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)))

#define	USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0

#define	USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)
	(USBHS_DEVDMAADDRESS) Buffer Address

#define	USBHS_DEVDMAADDRESS_BUFF_ADD(value) ((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)))

#define	USBHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0)
	(USBHS_DEVDMACONTROL) Channel Enable Command

#define	USBHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1)
	(USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command

#define	USBHS_DEVDMACONTROL_END_TR_EN (0x1u << 2)
	(USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only)

#define	USBHS_DEVDMACONTROL_END_B_EN (0x1u << 3)
	(USBHS_DEVDMACONTROL) End of Buffer Enable Control

#define	USBHS_DEVDMACONTROL_END_TR_IT (0x1u << 4)
	(USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable

#define	USBHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5)
	(USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable

#define	USBHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6)
	(USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable

#define	USBHS_DEVDMACONTROL_BURST_LCK (0x1u << 7)
	(USBHS_DEVDMACONTROL) Burst Lock Enable

#define	USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16

#define	USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)
	(USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only)

#define	USBHS_DEVDMACONTROL_BUFF_LENGTH(value) ((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)))

#define	USBHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0)
	(USBHS_DEVDMASTATUS) Channel Enable Status

#define	USBHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1)
	(USBHS_DEVDMASTATUS) Channel Active Status

#define	USBHS_DEVDMASTATUS_END_TR_ST (0x1u << 4)
	(USBHS_DEVDMASTATUS) End of Channel Transfer Status

#define	USBHS_DEVDMASTATUS_END_BF_ST (0x1u << 5)
	(USBHS_DEVDMASTATUS) End of Channel Buffer Status

#define	USBHS_DEVDMASTATUS_DESC_LDST (0x1u << 6)
	(USBHS_DEVDMASTATUS) Descriptor Loaded Status

#define	USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16

#define	USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)
	(USBHS_DEVDMASTATUS) Buffer Byte Count

#define	USBHS_DEVDMASTATUS_BUFF_COUNT(value) ((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)))

#define	USBHS_HSTCTRL_SOFE (0x1u << 8)
	(USBHS_HSTCTRL) Start of Frame Generation Enable

#define	USBHS_HSTCTRL_RESET (0x1u << 9)
	(USBHS_HSTCTRL) Send USB Reset

#define	USBHS_HSTCTRL_RESUME (0x1u << 10)
	(USBHS_HSTCTRL) Send USB Resume

#define	USBHS_HSTCTRL_SPDCONF_Pos 12

#define	USBHS_HSTCTRL_SPDCONF_Msk (0x3u << USBHS_HSTCTRL_SPDCONF_Pos)
	(USBHS_HSTCTRL) Mode Configuration

#define	USBHS_HSTCTRL_SPDCONF(value) ((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos)))

#define	USBHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12)
	(USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable.

#define	USBHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12)
	(USBHS_HSTCTRL) For a better consumption, if high speed is not needed.

#define	USBHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12)
	(USBHS_HSTCTRL) Forced high speed.

#define	USBHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12)
	(USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability.

#define	USBHS_HSTISR_DCONNI (0x1u << 0)
	(USBHS_HSTISR) Device Connection Interrupt

#define	USBHS_HSTISR_DDISCI (0x1u << 1)
	(USBHS_HSTISR) Device Disconnection Interrupt

#define	USBHS_HSTISR_RSTI (0x1u << 2)
	(USBHS_HSTISR) USB Reset Sent Interrupt

#define	USBHS_HSTISR_RSMEDI (0x1u << 3)
	(USBHS_HSTISR) Downstream Resume Sent Interrupt

#define	USBHS_HSTISR_RXRSMI (0x1u << 4)
	(USBHS_HSTISR) Upstream Resume Received Interrupt

#define	USBHS_HSTISR_HSOFI (0x1u << 5)
	(USBHS_HSTISR) Host Start of Frame Interrupt

#define	USBHS_HSTISR_HWUPI (0x1u << 6)
	(USBHS_HSTISR) Host Wake-Up Interrupt

#define	USBHS_HSTISR_PEP_0 (0x1u << 8)
	(USBHS_HSTISR) Pipe 0 Interrupt

#define	USBHS_HSTISR_PEP_1 (0x1u << 9)
	(USBHS_HSTISR) Pipe 1 Interrupt

#define	USBHS_HSTISR_PEP_2 (0x1u << 10)
	(USBHS_HSTISR) Pipe 2 Interrupt

#define	USBHS_HSTISR_PEP_3 (0x1u << 11)
	(USBHS_HSTISR) Pipe 3 Interrupt

#define	USBHS_HSTISR_PEP_4 (0x1u << 12)
	(USBHS_HSTISR) Pipe 4 Interrupt

#define	USBHS_HSTISR_PEP_5 (0x1u << 13)
	(USBHS_HSTISR) Pipe 5 Interrupt

#define	USBHS_HSTISR_PEP_6 (0x1u << 14)
	(USBHS_HSTISR) Pipe 6 Interrupt

#define	USBHS_HSTISR_PEP_7 (0x1u << 15)
	(USBHS_HSTISR) Pipe 7 Interrupt

#define	USBHS_HSTISR_PEP_8 (0x1u << 16)
	(USBHS_HSTISR) Pipe 8 Interrupt

#define	USBHS_HSTISR_PEP_9 (0x1u << 17)
	(USBHS_HSTISR) Pipe 9 Interrupt

#define	USBHS_HSTISR_PEP_10 (0x1u << 18)
	(USBHS_HSTISR) Pipe 10 Interrupt

#define	USBHS_HSTISR_PEP_11 (0x1u << 19)
	(USBHS_HSTISR) Pipe 11 Interrupt

#define	USBHS_HSTISR_DMA_1 (0x1u << 25)
	(USBHS_HSTISR) DMA Channel 1 Interrupt

#define	USBHS_HSTISR_DMA_2 (0x1u << 26)
	(USBHS_HSTISR) DMA Channel 2 Interrupt

#define	USBHS_HSTISR_DMA_3 (0x1u << 27)
	(USBHS_HSTISR) DMA Channel 3 Interrupt

#define	USBHS_HSTISR_DMA_4 (0x1u << 28)
	(USBHS_HSTISR) DMA Channel 4 Interrupt

#define	USBHS_HSTISR_DMA_5 (0x1u << 29)
	(USBHS_HSTISR) DMA Channel 5 Interrupt

#define	USBHS_HSTISR_DMA_6 (0x1u << 30)
	(USBHS_HSTISR) DMA Channel 6 Interrupt

#define	USBHS_HSTISR_DMA_7 (0x1u << 31)
	(USBHS_HSTISR) DMA Channel 7 Interrupt

#define	USBHS_HSTICR_DCONNIC (0x1u << 0)
	(USBHS_HSTICR) Device Connection Interrupt Clear

#define	USBHS_HSTICR_DDISCIC (0x1u << 1)
	(USBHS_HSTICR) Device Disconnection Interrupt Clear

#define	USBHS_HSTICR_RSTIC (0x1u << 2)
	(USBHS_HSTICR) USB Reset Sent Interrupt Clear

#define	USBHS_HSTICR_RSMEDIC (0x1u << 3)
	(USBHS_HSTICR) Downstream Resume Sent Interrupt Clear

#define	USBHS_HSTICR_RXRSMIC (0x1u << 4)
	(USBHS_HSTICR) Upstream Resume Received Interrupt Clear

#define	USBHS_HSTICR_HSOFIC (0x1u << 5)
	(USBHS_HSTICR) Host Start of Frame Interrupt Clear

#define	USBHS_HSTICR_HWUPIC (0x1u << 6)
	(USBHS_HSTICR) Host Wake-Up Interrupt Clear

#define	USBHS_HSTIFR_DCONNIS (0x1u << 0)
	(USBHS_HSTIFR) Device Connection Interrupt Set

#define	USBHS_HSTIFR_DDISCIS (0x1u << 1)
	(USBHS_HSTIFR) Device Disconnection Interrupt Set

#define	USBHS_HSTIFR_RSTIS (0x1u << 2)
	(USBHS_HSTIFR) USB Reset Sent Interrupt Set

#define	USBHS_HSTIFR_RSMEDIS (0x1u << 3)
	(USBHS_HSTIFR) Downstream Resume Sent Interrupt Set

#define	USBHS_HSTIFR_RXRSMIS (0x1u << 4)
	(USBHS_HSTIFR) Upstream Resume Received Interrupt Set

#define	USBHS_HSTIFR_HSOFIS (0x1u << 5)
	(USBHS_HSTIFR) Host Start of Frame Interrupt Set

#define	USBHS_HSTIFR_HWUPIS (0x1u << 6)
	(USBHS_HSTIFR) Host Wake-Up Interrupt Set

#define	USBHS_HSTIFR_DMA_1 (0x1u << 25)
	(USBHS_HSTIFR) DMA Channel 1 Interrupt Set

#define	USBHS_HSTIFR_DMA_2 (0x1u << 26)
	(USBHS_HSTIFR) DMA Channel 2 Interrupt Set

#define	USBHS_HSTIFR_DMA_3 (0x1u << 27)
	(USBHS_HSTIFR) DMA Channel 3 Interrupt Set

#define	USBHS_HSTIFR_DMA_4 (0x1u << 28)
	(USBHS_HSTIFR) DMA Channel 4 Interrupt Set

#define	USBHS_HSTIFR_DMA_5 (0x1u << 29)
	(USBHS_HSTIFR) DMA Channel 5 Interrupt Set

#define	USBHS_HSTIFR_DMA_6 (0x1u << 30)
	(USBHS_HSTIFR) DMA Channel 6 Interrupt Set

#define	USBHS_HSTIFR_DMA_7 (0x1u << 31)
	(USBHS_HSTIFR) DMA Channel 7 Interrupt Set

#define	USBHS_HSTIMR_DCONNIE (0x1u << 0)
	(USBHS_HSTIMR) Device Connection Interrupt Enable

#define	USBHS_HSTIMR_DDISCIE (0x1u << 1)
	(USBHS_HSTIMR) Device Disconnection Interrupt Enable

#define	USBHS_HSTIMR_RSTIE (0x1u << 2)
	(USBHS_HSTIMR) USB Reset Sent Interrupt Enable

#define	USBHS_HSTIMR_RSMEDIE (0x1u << 3)
	(USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable

#define	USBHS_HSTIMR_RXRSMIE (0x1u << 4)
	(USBHS_HSTIMR) Upstream Resume Received Interrupt Enable

#define	USBHS_HSTIMR_HSOFIE (0x1u << 5)
	(USBHS_HSTIMR) Host Start of Frame Interrupt Enable

#define	USBHS_HSTIMR_HWUPIE (0x1u << 6)
	(USBHS_HSTIMR) Host Wake-Up Interrupt Enable

#define	USBHS_HSTIMR_PEP_0 (0x1u << 8)
	(USBHS_HSTIMR) Pipe 0 Interrupt Enable

#define	USBHS_HSTIMR_PEP_1 (0x1u << 9)
	(USBHS_HSTIMR) Pipe 1 Interrupt Enable

#define	USBHS_HSTIMR_PEP_2 (0x1u << 10)
	(USBHS_HSTIMR) Pipe 2 Interrupt Enable

#define	USBHS_HSTIMR_PEP_3 (0x1u << 11)
	(USBHS_HSTIMR) Pipe 3 Interrupt Enable

#define	USBHS_HSTIMR_PEP_4 (0x1u << 12)
	(USBHS_HSTIMR) Pipe 4 Interrupt Enable

#define	USBHS_HSTIMR_PEP_5 (0x1u << 13)
	(USBHS_HSTIMR) Pipe 5 Interrupt Enable

#define	USBHS_HSTIMR_PEP_6 (0x1u << 14)
	(USBHS_HSTIMR) Pipe 6 Interrupt Enable

#define	USBHS_HSTIMR_PEP_7 (0x1u << 15)
	(USBHS_HSTIMR) Pipe 7 Interrupt Enable

#define	USBHS_HSTIMR_PEP_8 (0x1u << 16)
	(USBHS_HSTIMR) Pipe 8 Interrupt Enable

#define	USBHS_HSTIMR_PEP_9 (0x1u << 17)
	(USBHS_HSTIMR) Pipe 9 Interrupt Enable

#define	USBHS_HSTIMR_PEP_10 (0x1u << 18)
	(USBHS_HSTIMR) Pipe 10 Interrupt Enable

#define	USBHS_HSTIMR_PEP_11 (0x1u << 19)
	(USBHS_HSTIMR) Pipe 11 Interrupt Enable

#define	USBHS_HSTIMR_DMA_1 (0x1u << 25)
	(USBHS_HSTIMR) DMA Channel 1 Interrupt Enable

#define	USBHS_HSTIMR_DMA_2 (0x1u << 26)
	(USBHS_HSTIMR) DMA Channel 2 Interrupt Enable

#define	USBHS_HSTIMR_DMA_3 (0x1u << 27)
	(USBHS_HSTIMR) DMA Channel 3 Interrupt Enable

#define	USBHS_HSTIMR_DMA_4 (0x1u << 28)
	(USBHS_HSTIMR) DMA Channel 4 Interrupt Enable

#define	USBHS_HSTIMR_DMA_5 (0x1u << 29)
	(USBHS_HSTIMR) DMA Channel 5 Interrupt Enable

#define	USBHS_HSTIMR_DMA_6 (0x1u << 30)
	(USBHS_HSTIMR) DMA Channel 6 Interrupt Enable

#define	USBHS_HSTIMR_DMA_7 (0x1u << 31)
	(USBHS_HSTIMR) DMA Channel 7 Interrupt Enable

#define	USBHS_HSTIDR_DCONNIEC (0x1u << 0)
	(USBHS_HSTIDR) Device Connection Interrupt Disable

#define	USBHS_HSTIDR_DDISCIEC (0x1u << 1)
	(USBHS_HSTIDR) Device Disconnection Interrupt Disable

#define	USBHS_HSTIDR_RSTIEC (0x1u << 2)
	(USBHS_HSTIDR) USB Reset Sent Interrupt Disable

#define	USBHS_HSTIDR_RSMEDIEC (0x1u << 3)
	(USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable

#define	USBHS_HSTIDR_RXRSMIEC (0x1u << 4)
	(USBHS_HSTIDR) Upstream Resume Received Interrupt Disable

#define	USBHS_HSTIDR_HSOFIEC (0x1u << 5)
	(USBHS_HSTIDR) Host Start of Frame Interrupt Disable

#define	USBHS_HSTIDR_HWUPIEC (0x1u << 6)
	(USBHS_HSTIDR) Host Wake-Up Interrupt Disable

#define	USBHS_HSTIDR_PEP_0 (0x1u << 8)
	(USBHS_HSTIDR) Pipe 0 Interrupt Disable

#define	USBHS_HSTIDR_PEP_1 (0x1u << 9)
	(USBHS_HSTIDR) Pipe 1 Interrupt Disable

#define	USBHS_HSTIDR_PEP_2 (0x1u << 10)
	(USBHS_HSTIDR) Pipe 2 Interrupt Disable

#define	USBHS_HSTIDR_PEP_3 (0x1u << 11)
	(USBHS_HSTIDR) Pipe 3 Interrupt Disable

#define	USBHS_HSTIDR_PEP_4 (0x1u << 12)
	(USBHS_HSTIDR) Pipe 4 Interrupt Disable

#define	USBHS_HSTIDR_PEP_5 (0x1u << 13)
	(USBHS_HSTIDR) Pipe 5 Interrupt Disable

#define	USBHS_HSTIDR_PEP_6 (0x1u << 14)
	(USBHS_HSTIDR) Pipe 6 Interrupt Disable

#define	USBHS_HSTIDR_PEP_7 (0x1u << 15)
	(USBHS_HSTIDR) Pipe 7 Interrupt Disable

#define	USBHS_HSTIDR_PEP_8 (0x1u << 16)
	(USBHS_HSTIDR) Pipe 8 Interrupt Disable

#define	USBHS_HSTIDR_PEP_9 (0x1u << 17)
	(USBHS_HSTIDR) Pipe 9 Interrupt Disable

#define	USBHS_HSTIDR_PEP_10 (0x1u << 18)
	(USBHS_HSTIDR) Pipe 10 Interrupt Disable

#define	USBHS_HSTIDR_PEP_11 (0x1u << 19)
	(USBHS_HSTIDR) Pipe 11 Interrupt Disable

#define	USBHS_HSTIDR_DMA_1 (0x1u << 25)
	(USBHS_HSTIDR) DMA Channel 1 Interrupt Disable

#define	USBHS_HSTIDR_DMA_2 (0x1u << 26)
	(USBHS_HSTIDR) DMA Channel 2 Interrupt Disable

#define	USBHS_HSTIDR_DMA_3 (0x1u << 27)
	(USBHS_HSTIDR) DMA Channel 3 Interrupt Disable

#define	USBHS_HSTIDR_DMA_4 (0x1u << 28)
	(USBHS_HSTIDR) DMA Channel 4 Interrupt Disable

#define	USBHS_HSTIDR_DMA_5 (0x1u << 29)
	(USBHS_HSTIDR) DMA Channel 5 Interrupt Disable

#define	USBHS_HSTIDR_DMA_6 (0x1u << 30)
	(USBHS_HSTIDR) DMA Channel 6 Interrupt Disable

#define	USBHS_HSTIDR_DMA_7 (0x1u << 31)
	(USBHS_HSTIDR) DMA Channel 7 Interrupt Disable

#define	USBHS_HSTIER_DCONNIES (0x1u << 0)
	(USBHS_HSTIER) Device Connection Interrupt Enable

#define	USBHS_HSTIER_DDISCIES (0x1u << 1)
	(USBHS_HSTIER) Device Disconnection Interrupt Enable

#define	USBHS_HSTIER_RSTIES (0x1u << 2)
	(USBHS_HSTIER) USB Reset Sent Interrupt Enable

#define	USBHS_HSTIER_RSMEDIES (0x1u << 3)
	(USBHS_HSTIER) Downstream Resume Sent Interrupt Enable

#define	USBHS_HSTIER_RXRSMIES (0x1u << 4)
	(USBHS_HSTIER) Upstream Resume Received Interrupt Enable

#define	USBHS_HSTIER_HSOFIES (0x1u << 5)
	(USBHS_HSTIER) Host Start of Frame Interrupt Enable

#define	USBHS_HSTIER_HWUPIES (0x1u << 6)
	(USBHS_HSTIER) Host Wake-Up Interrupt Enable

#define	USBHS_HSTIER_PEP_0 (0x1u << 8)
	(USBHS_HSTIER) Pipe 0 Interrupt Enable

#define	USBHS_HSTIER_PEP_1 (0x1u << 9)
	(USBHS_HSTIER) Pipe 1 Interrupt Enable

#define	USBHS_HSTIER_PEP_2 (0x1u << 10)
	(USBHS_HSTIER) Pipe 2 Interrupt Enable

#define	USBHS_HSTIER_PEP_3 (0x1u << 11)
	(USBHS_HSTIER) Pipe 3 Interrupt Enable

#define	USBHS_HSTIER_PEP_4 (0x1u << 12)
	(USBHS_HSTIER) Pipe 4 Interrupt Enable

#define	USBHS_HSTIER_PEP_5 (0x1u << 13)
	(USBHS_HSTIER) Pipe 5 Interrupt Enable

#define	USBHS_HSTIER_PEP_6 (0x1u << 14)
	(USBHS_HSTIER) Pipe 6 Interrupt Enable

#define	USBHS_HSTIER_PEP_7 (0x1u << 15)
	(USBHS_HSTIER) Pipe 7 Interrupt Enable

#define	USBHS_HSTIER_PEP_8 (0x1u << 16)
	(USBHS_HSTIER) Pipe 8 Interrupt Enable

#define	USBHS_HSTIER_PEP_9 (0x1u << 17)
	(USBHS_HSTIER) Pipe 9 Interrupt Enable

#define	USBHS_HSTIER_PEP_10 (0x1u << 18)
	(USBHS_HSTIER) Pipe 10 Interrupt Enable

#define	USBHS_HSTIER_PEP_11 (0x1u << 19)
	(USBHS_HSTIER) Pipe 11 Interrupt Enable

#define	USBHS_HSTIER_DMA_1 (0x1u << 25)
	(USBHS_HSTIER) DMA Channel 1 Interrupt Enable

#define	USBHS_HSTIER_DMA_2 (0x1u << 26)
	(USBHS_HSTIER) DMA Channel 2 Interrupt Enable

#define	USBHS_HSTIER_DMA_3 (0x1u << 27)
	(USBHS_HSTIER) DMA Channel 3 Interrupt Enable

#define	USBHS_HSTIER_DMA_4 (0x1u << 28)
	(USBHS_HSTIER) DMA Channel 4 Interrupt Enable

#define	USBHS_HSTIER_DMA_5 (0x1u << 29)
	(USBHS_HSTIER) DMA Channel 5 Interrupt Enable

#define	USBHS_HSTIER_DMA_6 (0x1u << 30)
	(USBHS_HSTIER) DMA Channel 6 Interrupt Enable

#define	USBHS_HSTIER_DMA_7 (0x1u << 31)
	(USBHS_HSTIER) DMA Channel 7 Interrupt Enable

#define	USBHS_HSTPIP_PEN0 (0x1u << 0)
	(USBHS_HSTPIP) Pipe 0 Enable

#define	USBHS_HSTPIP_PEN1 (0x1u << 1)
	(USBHS_HSTPIP) Pipe 1 Enable

#define	USBHS_HSTPIP_PEN2 (0x1u << 2)
	(USBHS_HSTPIP) Pipe 2 Enable

#define	USBHS_HSTPIP_PEN3 (0x1u << 3)
	(USBHS_HSTPIP) Pipe 3 Enable

#define	USBHS_HSTPIP_PEN4 (0x1u << 4)
	(USBHS_HSTPIP) Pipe 4 Enable

#define	USBHS_HSTPIP_PEN5 (0x1u << 5)
	(USBHS_HSTPIP) Pipe 5 Enable

#define	USBHS_HSTPIP_PEN6 (0x1u << 6)
	(USBHS_HSTPIP) Pipe 6 Enable

#define	USBHS_HSTPIP_PEN7 (0x1u << 7)
	(USBHS_HSTPIP) Pipe 7 Enable

#define	USBHS_HSTPIP_PEN8 (0x1u << 8)
	(USBHS_HSTPIP) Pipe 8 Enable

#define	USBHS_HSTPIP_PRST0 (0x1u << 16)
	(USBHS_HSTPIP) Pipe 0 Reset

#define	USBHS_HSTPIP_PRST1 (0x1u << 17)
	(USBHS_HSTPIP) Pipe 1 Reset

#define	USBHS_HSTPIP_PRST2 (0x1u << 18)
	(USBHS_HSTPIP) Pipe 2 Reset

#define	USBHS_HSTPIP_PRST3 (0x1u << 19)
	(USBHS_HSTPIP) Pipe 3 Reset

#define	USBHS_HSTPIP_PRST4 (0x1u << 20)
	(USBHS_HSTPIP) Pipe 4 Reset

#define	USBHS_HSTPIP_PRST5 (0x1u << 21)
	(USBHS_HSTPIP) Pipe 5 Reset

#define	USBHS_HSTPIP_PRST6 (0x1u << 22)
	(USBHS_HSTPIP) Pipe 6 Reset

#define	USBHS_HSTPIP_PRST7 (0x1u << 23)
	(USBHS_HSTPIP) Pipe 7 Reset

#define	USBHS_HSTPIP_PRST8 (0x1u << 24)
	(USBHS_HSTPIP) Pipe 8 Reset

#define	USBHS_HSTFNUM_MFNUM_Pos 0

#define	USBHS_HSTFNUM_MFNUM_Msk (0x7u << USBHS_HSTFNUM_MFNUM_Pos)
	(USBHS_HSTFNUM) Micro Frame Number

#define	USBHS_HSTFNUM_MFNUM(value) ((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos)))

#define	USBHS_HSTFNUM_FNUM_Pos 3

#define	USBHS_HSTFNUM_FNUM_Msk (0x7ffu << USBHS_HSTFNUM_FNUM_Pos)
	(USBHS_HSTFNUM) Frame Number

#define	USBHS_HSTFNUM_FNUM(value) ((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos)))

#define	USBHS_HSTFNUM_FLENHIGH_Pos 16

#define	USBHS_HSTFNUM_FLENHIGH_Msk (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos)
	(USBHS_HSTFNUM) Frame Length

#define	USBHS_HSTFNUM_FLENHIGH(value) ((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos)))

#define	USBHS_HSTADDR1_HSTADDRP0_Pos 0

#define	USBHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos)
	(USBHS_HSTADDR1) USB Host Address

#define	USBHS_HSTADDR1_HSTADDRP0(value) ((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos)))

#define	USBHS_HSTADDR1_HSTADDRP1_Pos 8

#define	USBHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos)
	(USBHS_HSTADDR1) USB Host Address

#define	USBHS_HSTADDR1_HSTADDRP1(value) ((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos)))

#define	USBHS_HSTADDR1_HSTADDRP2_Pos 16

#define	USBHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos)
	(USBHS_HSTADDR1) USB Host Address

#define	USBHS_HSTADDR1_HSTADDRP2(value) ((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos)))

#define	USBHS_HSTADDR1_HSTADDRP3_Pos 24

#define	USBHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos)
	(USBHS_HSTADDR1) USB Host Address

#define	USBHS_HSTADDR1_HSTADDRP3(value) ((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos)))

#define	USBHS_HSTADDR2_HSTADDRP4_Pos 0

#define	USBHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos)
	(USBHS_HSTADDR2) USB Host Address

#define	USBHS_HSTADDR2_HSTADDRP4(value) ((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos)))

#define	USBHS_HSTADDR2_HSTADDRP5_Pos 8

#define	USBHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos)
	(USBHS_HSTADDR2) USB Host Address

#define	USBHS_HSTADDR2_HSTADDRP5(value) ((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos)))

#define	USBHS_HSTADDR2_HSTADDRP6_Pos 16

#define	USBHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos)
	(USBHS_HSTADDR2) USB Host Address

#define	USBHS_HSTADDR2_HSTADDRP6(value) ((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos)))

#define	USBHS_HSTADDR2_HSTADDRP7_Pos 24

#define	USBHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos)
	(USBHS_HSTADDR2) USB Host Address

#define	USBHS_HSTADDR2_HSTADDRP7(value) ((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos)))

#define	USBHS_HSTADDR3_HSTADDRP8_Pos 0

#define	USBHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos)
	(USBHS_HSTADDR3) USB Host Address

#define	USBHS_HSTADDR3_HSTADDRP8(value) ((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos)))

#define	USBHS_HSTADDR3_HSTADDRP9_Pos 8

#define	USBHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos)
	(USBHS_HSTADDR3) USB Host Address

#define	USBHS_HSTADDR3_HSTADDRP9(value) ((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos)))

#define	USBHS_HSTPIPCFG_ALLOC (0x1u << 1)
	(USBHS_HSTPIPCFG[10]) Pipe Memory Allocate

#define	USBHS_HSTPIPCFG_PBK_Pos 2

#define	USBHS_HSTPIPCFG_PBK_Msk (0x3u << USBHS_HSTPIPCFG_PBK_Pos)
	(USBHS_HSTPIPCFG[10]) Pipe Banks

#define	USBHS_HSTPIPCFG_PBK(value) ((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos)))

#define	USBHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2)
	(USBHS_HSTPIPCFG[10]) Single-bank pipe

#define	USBHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2)
	(USBHS_HSTPIPCFG[10]) Double-bank pipe

#define	USBHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2)
	(USBHS_HSTPIPCFG[10]) Triple-bank pipe

#define	USBHS_HSTPIPCFG_PSIZE_Pos 4

#define	USBHS_HSTPIPCFG_PSIZE_Msk (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos)
	(USBHS_HSTPIPCFG[10]) Pipe Size

#define	USBHS_HSTPIPCFG_PSIZE(value) ((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos)))

#define	USBHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4)
	(USBHS_HSTPIPCFG[10]) 8 bytes

#define	USBHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4)
	(USBHS_HSTPIPCFG[10]) 16 bytes

#define	USBHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4)
	(USBHS_HSTPIPCFG[10]) 32 bytes

#define	USBHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4)
	(USBHS_HSTPIPCFG[10]) 64 bytes

#define	USBHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4)
	(USBHS_HSTPIPCFG[10]) 128 bytes

#define	USBHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4)
	(USBHS_HSTPIPCFG[10]) 256 bytes

#define	USBHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4)
	(USBHS_HSTPIPCFG[10]) 512 bytes

#define	USBHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4)
	(USBHS_HSTPIPCFG[10]) 1024 bytes

#define	USBHS_HSTPIPCFG_PTOKEN_Pos 8

#define	USBHS_HSTPIPCFG_PTOKEN_Msk (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos)
	(USBHS_HSTPIPCFG[10]) Pipe Token

#define	USBHS_HSTPIPCFG_PTOKEN(value) ((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos)))

#define	USBHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8)
	(USBHS_HSTPIPCFG[10]) SETUP

#define	USBHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8)
	(USBHS_HSTPIPCFG[10]) IN

#define	USBHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8)
	(USBHS_HSTPIPCFG[10]) OUT

#define	USBHS_HSTPIPCFG_AUTOSW (0x1u << 10)
	(USBHS_HSTPIPCFG[10]) Automatic Switch

#define	USBHS_HSTPIPCFG_PTYPE_Pos 12

#define	USBHS_HSTPIPCFG_PTYPE_Msk (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos)
	(USBHS_HSTPIPCFG[10]) Pipe Type

#define	USBHS_HSTPIPCFG_PTYPE(value) ((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos)))

#define	USBHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12)
	(USBHS_HSTPIPCFG[10]) Control

#define	USBHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12)
	(USBHS_HSTPIPCFG[10]) Isochronous

#define	USBHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12)
	(USBHS_HSTPIPCFG[10]) Bulk

#define	USBHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12)
	(USBHS_HSTPIPCFG[10]) Interrupt

#define	USBHS_HSTPIPCFG_PEPNUM_Pos 16

#define	USBHS_HSTPIPCFG_PEPNUM_Msk (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos)
	(USBHS_HSTPIPCFG[10]) Pipe Endpoint Number

#define	USBHS_HSTPIPCFG_PEPNUM(value) ((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos)))

#define	USBHS_HSTPIPCFG_INTFRQ_Pos 24

#define	USBHS_HSTPIPCFG_INTFRQ_Msk (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos)
	(USBHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency

#define	USBHS_HSTPIPCFG_INTFRQ(value) ((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos)))

#define	USBHS_HSTPIPCFG_PINGEN (0x1u << 20)
	(USBHS_HSTPIPCFG[10]) Ping Enable

#define	USBHS_HSTPIPCFG_BINTERVAL_Pos 24

#define	USBHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos)
	(USBHS_HSTPIPCFG[10]) Binterval Parameter for the Bulk-Out/Ping Transaction

#define	USBHS_HSTPIPCFG_BINTERVAL(value) ((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos)))

#define	USBHS_HSTPIPISR_RXINI (0x1u << 0)
	(USBHS_HSTPIPISR[10]) Received IN Data Interrupt

#define	USBHS_HSTPIPISR_TXOUTI (0x1u << 1)
	(USBHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt

#define	USBHS_HSTPIPISR_TXSTPI (0x1u << 2)
	(USBHS_HSTPIPISR[10]) Transmitted SETUP Interrupt

#define	USBHS_HSTPIPISR_PERRI (0x1u << 3)
	(USBHS_HSTPIPISR[10]) Pipe Error Interrupt

#define	USBHS_HSTPIPISR_NAKEDI (0x1u << 4)
	(USBHS_HSTPIPISR[10]) NAKed Interrupt

#define	USBHS_HSTPIPISR_OVERFI (0x1u << 5)
	(USBHS_HSTPIPISR[10]) Overflow Interrupt

#define	USBHS_HSTPIPISR_RXSTALLDI (0x1u << 6)
	(USBHS_HSTPIPISR[10]) Received STALLed Interrupt

#define	USBHS_HSTPIPISR_SHORTPACKETI (0x1u << 7)
	(USBHS_HSTPIPISR[10]) Short Packet Interrupt

#define	USBHS_HSTPIPISR_DTSEQ_Pos 8

#define	USBHS_HSTPIPISR_DTSEQ_Msk (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos)
	(USBHS_HSTPIPISR[10]) Data Toggle Sequence

#define	USBHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8)
	(USBHS_HSTPIPISR[10]) Data0 toggle sequence

#define	USBHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8)
	(USBHS_HSTPIPISR[10]) Data1 toggle sequence

#define	USBHS_HSTPIPISR_NBUSYBK_Pos 12

#define	USBHS_HSTPIPISR_NBUSYBK_Msk (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos)
	(USBHS_HSTPIPISR[10]) Number of Busy Banks

#define	USBHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12)
	(USBHS_HSTPIPISR[10]) 0 busy bank (all banks free)

#define	USBHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12)
	(USBHS_HSTPIPISR[10]) 1 busy bank

#define	USBHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12)
	(USBHS_HSTPIPISR[10]) 2 busy banks

#define	USBHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12)
	(USBHS_HSTPIPISR[10]) 3 busy banks

#define	USBHS_HSTPIPISR_CURRBK_Pos 14

#define	USBHS_HSTPIPISR_CURRBK_Msk (0x3u << USBHS_HSTPIPISR_CURRBK_Pos)
	(USBHS_HSTPIPISR[10]) Current Bank

#define	USBHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14)
	(USBHS_HSTPIPISR[10]) Current bank is bank0

#define	USBHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14)
	(USBHS_HSTPIPISR[10]) Current bank is bank1

#define	USBHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14)
	(USBHS_HSTPIPISR[10]) Current bank is bank2

#define	USBHS_HSTPIPISR_RWALL (0x1u << 16)
	(USBHS_HSTPIPISR[10]) Read/Write Allowed

#define	USBHS_HSTPIPISR_CFGOK (0x1u << 18)
	(USBHS_HSTPIPISR[10]) Configuration OK Status

#define	USBHS_HSTPIPISR_PBYCT_Pos 20

#define	USBHS_HSTPIPISR_PBYCT_Msk (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos)
	(USBHS_HSTPIPISR[10]) Pipe Byte Count

#define	USBHS_HSTPIPISR_UNDERFI (0x1u << 2)
	(USBHS_HSTPIPISR[10]) Underflow Interrupt

#define	USBHS_HSTPIPISR_CRCERRI (0x1u << 6)
	(USBHS_HSTPIPISR[10]) CRC Error Interrupt

#define	USBHS_HSTPIPICR_RXINIC (0x1u << 0)
	(USBHS_HSTPIPICR[10]) Received IN Data Interrupt Clear

#define	USBHS_HSTPIPICR_TXOUTIC (0x1u << 1)
	(USBHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear

#define	USBHS_HSTPIPICR_TXSTPIC (0x1u << 2)
	(USBHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear

#define	USBHS_HSTPIPICR_NAKEDIC (0x1u << 4)
	(USBHS_HSTPIPICR[10]) NAKed Interrupt Clear

#define	USBHS_HSTPIPICR_OVERFIC (0x1u << 5)
	(USBHS_HSTPIPICR[10]) Overflow Interrupt Clear

#define	USBHS_HSTPIPICR_RXSTALLDIC (0x1u << 6)
	(USBHS_HSTPIPICR[10]) Received STALLed Interrupt Clear

#define	USBHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7)
	(USBHS_HSTPIPICR[10]) Short Packet Interrupt Clear

#define	USBHS_HSTPIPICR_UNDERFIC (0x1u << 2)
	(USBHS_HSTPIPICR[10]) Underflow Interrupt Clear

#define	USBHS_HSTPIPICR_CRCERRIC (0x1u << 6)
	(USBHS_HSTPIPICR[10]) CRC Error Interrupt Clear

#define	USBHS_HSTPIPIFR_RXINIS (0x1u << 0)
	(USBHS_HSTPIPIFR[10]) Received IN Data Interrupt Set

#define	USBHS_HSTPIPIFR_TXOUTIS (0x1u << 1)
	(USBHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set

#define	USBHS_HSTPIPIFR_TXSTPIS (0x1u << 2)
	(USBHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set

#define	USBHS_HSTPIPIFR_PERRIS (0x1u << 3)
	(USBHS_HSTPIPIFR[10]) Pipe Error Interrupt Set

#define	USBHS_HSTPIPIFR_NAKEDIS (0x1u << 4)
	(USBHS_HSTPIPIFR[10]) NAKed Interrupt Set

#define	USBHS_HSTPIPIFR_OVERFIS (0x1u << 5)
	(USBHS_HSTPIPIFR[10]) Overflow Interrupt Set

#define	USBHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6)
	(USBHS_HSTPIPIFR[10]) Received STALLed Interrupt Set

#define	USBHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7)
	(USBHS_HSTPIPIFR[10]) Short Packet Interrupt Set

#define	USBHS_HSTPIPIFR_NBUSYBKS (0x1u << 12)
	(USBHS_HSTPIPIFR[10]) Number of Busy Banks Set

#define	USBHS_HSTPIPIFR_UNDERFIS (0x1u << 2)
	(USBHS_HSTPIPIFR[10]) Underflow Interrupt Set

#define	USBHS_HSTPIPIFR_CRCERRIS (0x1u << 6)
	(USBHS_HSTPIPIFR[10]) CRC Error Interrupt Set

#define	USBHS_HSTPIPIMR_RXINE (0x1u << 0)
	(USBHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable

#define	USBHS_HSTPIPIMR_TXOUTE (0x1u << 1)
	(USBHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable

#define	USBHS_HSTPIPIMR_TXSTPE (0x1u << 2)
	(USBHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable

#define	USBHS_HSTPIPIMR_PERRE (0x1u << 3)
	(USBHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable

#define	USBHS_HSTPIPIMR_NAKEDE (0x1u << 4)
	(USBHS_HSTPIPIMR[10]) NAKed Interrupt Enable

#define	USBHS_HSTPIPIMR_OVERFIE (0x1u << 5)
	(USBHS_HSTPIPIMR[10]) Overflow Interrupt Enable

#define	USBHS_HSTPIPIMR_RXSTALLDE (0x1u << 6)
	(USBHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable

#define	USBHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7)
	(USBHS_HSTPIPIMR[10]) Short Packet Interrupt Enable

#define	USBHS_HSTPIPIMR_NBUSYBKE (0x1u << 12)
	(USBHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable

#define	USBHS_HSTPIPIMR_FIFOCON (0x1u << 14)
	(USBHS_HSTPIPIMR[10]) FIFO Control

#define	USBHS_HSTPIPIMR_PDISHDMA (0x1u << 16)
	(USBHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable

#define	USBHS_HSTPIPIMR_PFREEZE (0x1u << 17)
	(USBHS_HSTPIPIMR[10]) Pipe Freeze

#define	USBHS_HSTPIPIMR_RSTDT (0x1u << 18)
	(USBHS_HSTPIPIMR[10]) Reset Data Toggle

#define	USBHS_HSTPIPIMR_UNDERFIE (0x1u << 2)
	(USBHS_HSTPIPIMR[10]) Underflow Interrupt Enable

#define	USBHS_HSTPIPIMR_CRCERRE (0x1u << 6)
	(USBHS_HSTPIPIMR[10]) CRC Error Interrupt Enable

#define	USBHS_HSTPIPIER_RXINES (0x1u << 0)
	(USBHS_HSTPIPIER[10]) Received IN Data Interrupt Enable

#define	USBHS_HSTPIPIER_TXOUTES (0x1u << 1)
	(USBHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable

#define	USBHS_HSTPIPIER_TXSTPES (0x1u << 2)
	(USBHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable

#define	USBHS_HSTPIPIER_PERRES (0x1u << 3)
	(USBHS_HSTPIPIER[10]) Pipe Error Interrupt Enable

#define	USBHS_HSTPIPIER_NAKEDES (0x1u << 4)
	(USBHS_HSTPIPIER[10]) NAKed Interrupt Enable

#define	USBHS_HSTPIPIER_OVERFIES (0x1u << 5)
	(USBHS_HSTPIPIER[10]) Overflow Interrupt Enable

#define	USBHS_HSTPIPIER_RXSTALLDES (0x1u << 6)
	(USBHS_HSTPIPIER[10]) Received STALLed Interrupt Enable

#define	USBHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7)
	(USBHS_HSTPIPIER[10]) Short Packet Interrupt Enable

#define	USBHS_HSTPIPIER_NBUSYBKES (0x1u << 12)
	(USBHS_HSTPIPIER[10]) Number of Busy Banks Enable

#define	USBHS_HSTPIPIER_PDISHDMAS (0x1u << 16)
	(USBHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable

#define	USBHS_HSTPIPIER_PFREEZES (0x1u << 17)
	(USBHS_HSTPIPIER[10]) Pipe Freeze Enable

#define	USBHS_HSTPIPIER_RSTDTS (0x1u << 18)
	(USBHS_HSTPIPIER[10]) Reset Data Toggle Enable

#define	USBHS_HSTPIPIER_UNDERFIES (0x1u << 2)
	(USBHS_HSTPIPIER[10]) Underflow Interrupt Enable

#define	USBHS_HSTPIPIER_CRCERRES (0x1u << 6)
	(USBHS_HSTPIPIER[10]) CRC Error Interrupt Enable

#define	USBHS_HSTPIPIDR_RXINEC (0x1u << 0)
	(USBHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable

#define	USBHS_HSTPIPIDR_TXOUTEC (0x1u << 1)
	(USBHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable

#define	USBHS_HSTPIPIDR_TXSTPEC (0x1u << 2)
	(USBHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable

#define	USBHS_HSTPIPIDR_PERREC (0x1u << 3)
	(USBHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable

#define	USBHS_HSTPIPIDR_NAKEDEC (0x1u << 4)
	(USBHS_HSTPIPIDR[10]) NAKed Interrupt Disable

#define	USBHS_HSTPIPIDR_OVERFIEC (0x1u << 5)
	(USBHS_HSTPIPIDR[10]) Overflow Interrupt Disable

#define	USBHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6)
	(USBHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable

#define	USBHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7)
	(USBHS_HSTPIPIDR[10]) Short Packet Interrupt Disable

#define	USBHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12)
	(USBHS_HSTPIPIDR[10]) Number of Busy Banks Disable

#define	USBHS_HSTPIPIDR_FIFOCONC (0x1u << 14)
	(USBHS_HSTPIPIDR[10]) FIFO Control Disable

#define	USBHS_HSTPIPIDR_PDISHDMAC (0x1u << 16)
	(USBHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable

#define	USBHS_HSTPIPIDR_PFREEZEC (0x1u << 17)
	(USBHS_HSTPIPIDR[10]) Pipe Freeze Disable

#define	USBHS_HSTPIPIDR_UNDERFIEC (0x1u << 2)
	(USBHS_HSTPIPIDR[10]) Underflow Interrupt Disable

#define	USBHS_HSTPIPIDR_CRCERREC (0x1u << 6)
	(USBHS_HSTPIPIDR[10]) CRC Error Interrupt Disable

#define	USBHS_HSTPIPINRQ_INRQ_Pos 0

#define	USBHS_HSTPIPINRQ_INRQ_Msk (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos)
	(USBHS_HSTPIPINRQ[10]) IN Request Number before Freeze

#define	USBHS_HSTPIPINRQ_INRQ(value) ((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos)))

#define	USBHS_HSTPIPINRQ_INMODE (0x1u << 8)
	(USBHS_HSTPIPINRQ[10]) IN Request Mode

#define	USBHS_HSTPIPERR_DATATGL (0x1u << 0)
	(USBHS_HSTPIPERR[10]) Data Toggle Error

#define	USBHS_HSTPIPERR_DATAPID (0x1u << 1)
	(USBHS_HSTPIPERR[10]) Data PID Error

#define	USBHS_HSTPIPERR_PID (0x1u << 2)
	(USBHS_HSTPIPERR[10]) Data PID Error

#define	USBHS_HSTPIPERR_TIMEOUT (0x1u << 3)
	(USBHS_HSTPIPERR[10]) Time-Out Error

#define	USBHS_HSTPIPERR_CRC16 (0x1u << 4)
	(USBHS_HSTPIPERR[10]) CRC16 Error

#define	USBHS_HSTPIPERR_COUNTER_Pos 5

#define	USBHS_HSTPIPERR_COUNTER_Msk (0x3u << USBHS_HSTPIPERR_COUNTER_Pos)
	(USBHS_HSTPIPERR[10]) Error Counter

#define	USBHS_HSTPIPERR_COUNTER(value) ((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos)))

#define	USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0

#define	USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)
	(USBHS_HSTDMANXTDSC) Next Descriptor Address

#define	USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)))

#define	USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0

#define	USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)
	(USBHS_HSTDMAADDRESS) Buffer Address

#define	USBHS_HSTDMAADDRESS_BUFF_ADD(value) ((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)))

#define	USBHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0)
	(USBHS_HSTDMACONTROL) Channel Enable Command

#define	USBHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1)
	(USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command

#define	USBHS_HSTDMACONTROL_END_TR_EN (0x1u << 2)
	(USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only)

#define	USBHS_HSTDMACONTROL_END_B_EN (0x1u << 3)
	(USBHS_HSTDMACONTROL) End of Buffer Enable Control

#define	USBHS_HSTDMACONTROL_END_TR_IT (0x1u << 4)
	(USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable

#define	USBHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5)
	(USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable

#define	USBHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6)
	(USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable

#define	USBHS_HSTDMACONTROL_BURST_LCK (0x1u << 7)
	(USBHS_HSTDMACONTROL) Burst Lock Enable

#define	USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16

#define	USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)
	(USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only)

#define	USBHS_HSTDMACONTROL_BUFF_LENGTH(value) ((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)))

#define	USBHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0)
	(USBHS_HSTDMASTATUS) Channel Enable Status

#define	USBHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1)
	(USBHS_HSTDMASTATUS) Channel Active Status

#define	USBHS_HSTDMASTATUS_END_TR_ST (0x1u << 4)
	(USBHS_HSTDMASTATUS) End of Channel Transfer Status

#define	USBHS_HSTDMASTATUS_END_BF_ST (0x1u << 5)
	(USBHS_HSTDMASTATUS) End of Channel Buffer Status

#define	USBHS_HSTDMASTATUS_DESC_LDST (0x1u << 6)
	(USBHS_HSTDMASTATUS) Descriptor Loaded Status

#define	USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16

#define	USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)
	(USBHS_HSTDMASTATUS) Buffer Byte Count

#define	USBHS_HSTDMASTATUS_BUFF_COUNT(value) ((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)))

#define	USBHS_CTRL_RDERRE (0x1u << 4)
	(USBHS_CTRL) Remote Device Connection Error Interrupt Enable

#define	USBHS_CTRL_VBUSHWC (0x1u << 8)
	(USBHS_CTRL) VBUS Hardware Control

#define	USBHS_CTRL_FRZCLK (0x1u << 14)
	(USBHS_CTRL) Freeze USB Clock

#define	USBHS_CTRL_USBE (0x1u << 15)
	(USBHS_CTRL) USBHS Enable

#define	USBHS_CTRL_UIMOD (0x1u << 25)
	(USBHS_CTRL) USBHS Mode

#define	USBHS_CTRL_UIMOD_HOST (0x0u << 25)
	(USBHS_CTRL) The module is in USB Host mode.

#define	USBHS_CTRL_UIMOD_DEVICE (0x1u << 25)
	(USBHS_CTRL) The module is in USB Device mode.

#define	USBHS_SR_RDERRI (0x1u << 4)
	(USBHS_SR) Remote Device Connection Error Interrupt (Host mode only)

#define	USBHS_SR_VBUSRQ (0x1u << 9)
	(USBHS_SR) VBUS Request (Host mode only)

#define	USBHS_SR_SPEED_Pos 12

#define	USBHS_SR_SPEED_Msk (0x3u << USBHS_SR_SPEED_Pos)
	(USBHS_SR) Speed Status (Device mode only)

#define	USBHS_SR_SPEED_FULL_SPEED (0x0u << 12)
	(USBHS_SR) Full-Speed mode

#define	USBHS_SR_SPEED_HIGH_SPEED (0x1u << 12)
	(USBHS_SR) High-Speed mode

#define	USBHS_SR_SPEED_LOW_SPEED (0x2u << 12)
	(USBHS_SR) Low-Speed mode

#define	USBHS_SR_CLKUSABLE (0x1u << 14)
	(USBHS_SR) UTMI Clock Usable

#define	USBHS_SCR_RDERRIC (0x1u << 4)
	(USBHS_SCR) Remote Device Connection Error Interrupt Clear

#define	USBHS_SCR_VBUSRQC (0x1u << 9)
	(USBHS_SCR) VBUS Request Clear

#define	USBHS_SFR_RDERRIS (0x1u << 4)
	(USBHS_SFR) Remote Device Connection Error Interrupt Set

#define	USBHS_SFR_VBUSRQS (0x1u << 9)
	(USBHS_SFR) VBUS Request Set

Detailed Description

SOFTWARE API DEFINITION FOR USB High-Speed Interface

Data Structures

Macros

Detailed Description