RTEMS  5.0.0
Data Fields

Ssc hardware registers. More...

#include <component_ssc.h>

Data Fields

__O uint32_t SSC_CR
 (Ssc Offset: 0x0) Control Register
 
__IO uint32_t SSC_CMR
 (Ssc Offset: 0x4) Clock Mode Register
 
__I uint32_t Reserved1 [2]
 
__IO uint32_t SSC_RCMR
 (Ssc Offset: 0x10) Receive Clock Mode Register
 
__IO uint32_t SSC_RFMR
 (Ssc Offset: 0x14) Receive Frame Mode Register
 
__IO uint32_t SSC_TCMR
 (Ssc Offset: 0x18) Transmit Clock Mode Register
 
__IO uint32_t SSC_TFMR
 (Ssc Offset: 0x1C) Transmit Frame Mode Register
 
__I uint32_t SSC_RHR
 (Ssc Offset: 0x20) Receive Holding Register
 
__O uint32_t SSC_THR
 (Ssc Offset: 0x24) Transmit Holding Register
 
__I uint32_t Reserved2 [2]
 
__I uint32_t SSC_RSHR
 (Ssc Offset: 0x30) Receive Sync. Holding Register
 
__IO uint32_t SSC_TSHR
 (Ssc Offset: 0x34) Transmit Sync. Holding Register
 
__IO uint32_t SSC_RC0R
 (Ssc Offset: 0x38) Receive Compare 0 Register
 
__IO uint32_t SSC_RC1R
 (Ssc Offset: 0x3C) Receive Compare 1 Register
 
__I uint32_t SSC_SR
 (Ssc Offset: 0x40) Status Register
 
__O uint32_t SSC_IER
 (Ssc Offset: 0x44) Interrupt Enable Register
 
__O uint32_t SSC_IDR
 (Ssc Offset: 0x48) Interrupt Disable Register
 
__I uint32_t SSC_IMR
 (Ssc Offset: 0x4C) Interrupt Mask Register
 
__I uint32_t Reserved3 [37]
 
__IO uint32_t SSC_WPMR
 (Ssc Offset: 0xE4) Write Protection Mode Register
 
__I uint32_t SSC_WPSR
 (Ssc Offset: 0xE8) Write Protection Status Register
 
__I uint32_t Reserved4 [4]
 
__I uint32_t SSC_VERSION
 (Ssc Offset: 0xFC) Version Register
 

Detailed Description

Ssc hardware registers.


The documentation for this struct was generated from the following file: