RTEMS  5.0.0
Data Structures | Macros
Synchronous Serial Controller
Board Support Packages » ARM » Atmel/Microchip SAM E70, S70, V70 and V71 » Contributed Code » SAME70

Data Structures

struct  Ssc
 Ssc hardware registers. More...
 

Macros

#define SSC_CR_RXEN   (0x1u << 0)
 (SSC_CR) Receive Enable
 
#define SSC_CR_RXDIS   (0x1u << 1)
 (SSC_CR) Receive Disable
 
#define SSC_CR_TXEN   (0x1u << 8)
 (SSC_CR) Transmit Enable
 
#define SSC_CR_TXDIS   (0x1u << 9)
 (SSC_CR) Transmit Disable
 
#define SSC_CR_SWRST   (0x1u << 15)
 (SSC_CR) Software Reset
 
#define SSC_CMR_DIV_Pos   0
 
#define SSC_CMR_DIV_Msk   (0xfffu << SSC_CMR_DIV_Pos)
 (SSC_CMR) Clock Divider
 
#define SSC_CMR_DIV(value)   ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)))
 
#define SSC_RCMR_CKS_Pos   0
 
#define SSC_RCMR_CKS_Msk   (0x3u << SSC_RCMR_CKS_Pos)
 (SSC_RCMR) Receive Clock Selection
 
#define SSC_RCMR_CKS(value)   ((SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos)))
 
#define SSC_RCMR_CKS_MCK   (0x0u << 0)
 (SSC_RCMR) Divided Clock
 
#define SSC_RCMR_CKS_TK   (0x1u << 0)
 (SSC_RCMR) TK Clock signal
 
#define SSC_RCMR_CKS_RK   (0x2u << 0)
 (SSC_RCMR) RK pin
 
#define SSC_RCMR_CKO_Pos   2
 
#define SSC_RCMR_CKO_Msk   (0x7u << SSC_RCMR_CKO_Pos)
 (SSC_RCMR) Receive Clock Output Mode Selection
 
#define SSC_RCMR_CKO(value)   ((SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos)))
 
#define SSC_RCMR_CKO_NONE   (0x0u << 2)
 (SSC_RCMR) None, RK pin is an input
 
#define SSC_RCMR_CKO_CONTINUOUS   (0x1u << 2)
 (SSC_RCMR) Continuous Receive Clock, RK pin is an output
 
#define SSC_RCMR_CKO_TRANSFER   (0x2u << 2)
 (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output
 
#define SSC_RCMR_CKI   (0x1u << 5)
 (SSC_RCMR) Receive Clock Inversion
 
#define SSC_RCMR_CKG_Pos   6
 
#define SSC_RCMR_CKG_Msk   (0x3u << SSC_RCMR_CKG_Pos)
 (SSC_RCMR) Receive Clock Gating Selection
 
#define SSC_RCMR_CKG(value)   ((SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos)))
 
#define SSC_RCMR_CKG_CONTINUOUS   (0x0u << 6)
 (SSC_RCMR) None
 
#define SSC_RCMR_CKG_EN_RF_LOW   (0x1u << 6)
 (SSC_RCMR) Receive Clock enabled only if RF Low
 
#define SSC_RCMR_CKG_EN_RF_HIGH   (0x2u << 6)
 (SSC_RCMR) Receive Clock enabled only if RF High
 
#define SSC_RCMR_START_Pos   8
 
#define SSC_RCMR_START_Msk   (0xfu << SSC_RCMR_START_Pos)
 (SSC_RCMR) Receive Start Selection
 
#define SSC_RCMR_START(value)   ((SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos)))
 
#define SSC_RCMR_START_CONTINUOUS   (0x0u << 8)
 (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
 
#define SSC_RCMR_START_TRANSMIT   (0x1u << 8)
 (SSC_RCMR) Transmit start
 
#define SSC_RCMR_START_RF_LOW   (0x2u << 8)
 (SSC_RCMR) Detection of a low level on RF signal
 
#define SSC_RCMR_START_RF_HIGH   (0x3u << 8)
 (SSC_RCMR) Detection of a high level on RF signal
 
#define SSC_RCMR_START_RF_FALLING   (0x4u << 8)
 (SSC_RCMR) Detection of a falling edge on RF signal
 
#define SSC_RCMR_START_RF_RISING   (0x5u << 8)
 (SSC_RCMR) Detection of a rising edge on RF signal
 
#define SSC_RCMR_START_RF_LEVEL   (0x6u << 8)
 (SSC_RCMR) Detection of any level change on RF signal
 
#define SSC_RCMR_START_RF_EDGE   (0x7u << 8)
 (SSC_RCMR) Detection of any edge on RF signal
 
#define SSC_RCMR_START_CMP_0   (0x8u << 8)
 (SSC_RCMR) Compare 0
 
#define SSC_RCMR_STOP   (0x1u << 12)
 (SSC_RCMR) Receive Stop Selection
 
#define SSC_RCMR_STTDLY_Pos   16
 
#define SSC_RCMR_STTDLY_Msk   (0xffu << SSC_RCMR_STTDLY_Pos)
 (SSC_RCMR) Receive Start Delay
 
#define SSC_RCMR_STTDLY(value)   ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)))
 
#define SSC_RCMR_PERIOD_Pos   24
 
#define SSC_RCMR_PERIOD_Msk   (0xffu << SSC_RCMR_PERIOD_Pos)
 (SSC_RCMR) Receive Period Divider Selection
 
#define SSC_RCMR_PERIOD(value)   ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)))
 
#define SSC_RFMR_DATLEN_Pos   0
 
#define SSC_RFMR_DATLEN_Msk   (0x1fu << SSC_RFMR_DATLEN_Pos)
 (SSC_RFMR) Data Length
 
#define SSC_RFMR_DATLEN(value)   ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)))
 
#define SSC_RFMR_LOOP   (0x1u << 5)
 (SSC_RFMR) Loop Mode
 
#define SSC_RFMR_MSBF   (0x1u << 7)
 (SSC_RFMR) Most Significant Bit First
 
#define SSC_RFMR_DATNB_Pos   8
 
#define SSC_RFMR_DATNB_Msk   (0xfu << SSC_RFMR_DATNB_Pos)
 (SSC_RFMR) Data Number per Frame
 
#define SSC_RFMR_DATNB(value)   ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)))
 
#define SSC_RFMR_FSLEN_Pos   16
 
#define SSC_RFMR_FSLEN_Msk   (0xfu << SSC_RFMR_FSLEN_Pos)
 (SSC_RFMR) Receive Frame Sync Length
 
#define SSC_RFMR_FSLEN(value)   ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)))
 
#define SSC_RFMR_FSOS_Pos   20
 
#define SSC_RFMR_FSOS_Msk   (0x7u << SSC_RFMR_FSOS_Pos)
 (SSC_RFMR) Receive Frame Sync Output Selection
 
#define SSC_RFMR_FSOS(value)   ((SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos)))
 
#define SSC_RFMR_FSOS_NONE   (0x0u << 20)
 (SSC_RFMR) None, RF pin is an input
 
#define SSC_RFMR_FSOS_NEGATIVE   (0x1u << 20)
 (SSC_RFMR) Negative Pulse, RF pin is an output
 
#define SSC_RFMR_FSOS_POSITIVE   (0x2u << 20)
 (SSC_RFMR) Positive Pulse, RF pin is an output
 
#define SSC_RFMR_FSOS_LOW   (0x3u << 20)
 (SSC_RFMR) Driven Low during data transfer, RF pin is an output
 
#define SSC_RFMR_FSOS_HIGH   (0x4u << 20)
 (SSC_RFMR) Driven High during data transfer, RF pin is an output
 
#define SSC_RFMR_FSOS_TOGGLING   (0x5u << 20)
 (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output
 
#define SSC_RFMR_FSEDGE   (0x1u << 24)
 (SSC_RFMR) Frame Sync Edge Detection
 
#define SSC_RFMR_FSEDGE_POSITIVE   (0x0u << 24)
 (SSC_RFMR) Positive Edge Detection
 
#define SSC_RFMR_FSEDGE_NEGATIVE   (0x1u << 24)
 (SSC_RFMR) Negative Edge Detection
 
#define SSC_RFMR_FSLEN_EXT_Pos   28
 
#define SSC_RFMR_FSLEN_EXT_Msk   (0xfu << SSC_RFMR_FSLEN_EXT_Pos)
 (SSC_RFMR) FSLEN Field Extension
 
#define SSC_RFMR_FSLEN_EXT(value)   ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)))
 
#define SSC_TCMR_CKS_Pos   0
 
#define SSC_TCMR_CKS_Msk   (0x3u << SSC_TCMR_CKS_Pos)
 (SSC_TCMR) Transmit Clock Selection
 
#define SSC_TCMR_CKS(value)   ((SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos)))
 
#define SSC_TCMR_CKS_MCK   (0x0u << 0)
 (SSC_TCMR) Divided Clock
 
#define SSC_TCMR_CKS_RK   (0x1u << 0)
 (SSC_TCMR) RK Clock signal
 
#define SSC_TCMR_CKS_TK   (0x2u << 0)
 (SSC_TCMR) TK pin
 
#define SSC_TCMR_CKO_Pos   2
 
#define SSC_TCMR_CKO_Msk   (0x7u << SSC_TCMR_CKO_Pos)
 (SSC_TCMR) Transmit Clock Output Mode Selection
 
#define SSC_TCMR_CKO(value)   ((SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos)))
 
#define SSC_TCMR_CKO_NONE   (0x0u << 2)
 (SSC_TCMR) None, TK pin is an input
 
#define SSC_TCMR_CKO_CONTINUOUS   (0x1u << 2)
 (SSC_TCMR) Continuous Transmit Clock, TK pin is an output
 
#define SSC_TCMR_CKO_TRANSFER   (0x2u << 2)
 (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output
 
#define SSC_TCMR_CKI   (0x1u << 5)
 (SSC_TCMR) Transmit Clock Inversion
 
#define SSC_TCMR_CKG_Pos   6
 
#define SSC_TCMR_CKG_Msk   (0x3u << SSC_TCMR_CKG_Pos)
 (SSC_TCMR) Transmit Clock Gating Selection
 
#define SSC_TCMR_CKG(value)   ((SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos)))
 
#define SSC_TCMR_CKG_CONTINUOUS   (0x0u << 6)
 (SSC_TCMR) None
 
#define SSC_TCMR_CKG_EN_TF_LOW   (0x1u << 6)
 (SSC_TCMR) Transmit Clock enabled only if TF Low
 
#define SSC_TCMR_CKG_EN_TF_HIGH   (0x2u << 6)
 (SSC_TCMR) Transmit Clock enabled only if TF High
 
#define SSC_TCMR_START_Pos   8
 
#define SSC_TCMR_START_Msk   (0xfu << SSC_TCMR_START_Pos)
 (SSC_TCMR) Transmit Start Selection
 
#define SSC_TCMR_START(value)   ((SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos)))
 
#define SSC_TCMR_START_CONTINUOUS   (0x0u << 8)
 (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data
 
#define SSC_TCMR_START_RECEIVE   (0x1u << 8)
 (SSC_TCMR) Receive start
 
#define SSC_TCMR_START_TF_LOW   (0x2u << 8)
 (SSC_TCMR) Detection of a low level on TF signal
 
#define SSC_TCMR_START_TF_HIGH   (0x3u << 8)
 (SSC_TCMR) Detection of a high level on TF signal
 
#define SSC_TCMR_START_TF_FALLING   (0x4u << 8)
 (SSC_TCMR) Detection of a falling edge on TF signal
 
#define SSC_TCMR_START_TF_RISING   (0x5u << 8)
 (SSC_TCMR) Detection of a rising edge on TF signal
 
#define SSC_TCMR_START_TF_LEVEL   (0x6u << 8)
 (SSC_TCMR) Detection of any level change on TF signal
 
#define SSC_TCMR_START_TF_EDGE   (0x7u << 8)
 (SSC_TCMR) Detection of any edge on TF signal
 
#define SSC_TCMR_STTDLY_Pos   16
 
#define SSC_TCMR_STTDLY_Msk   (0xffu << SSC_TCMR_STTDLY_Pos)
 (SSC_TCMR) Transmit Start Delay
 
#define SSC_TCMR_STTDLY(value)   ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)))
 
#define SSC_TCMR_PERIOD_Pos   24
 
#define SSC_TCMR_PERIOD_Msk   (0xffu << SSC_TCMR_PERIOD_Pos)
 (SSC_TCMR) Transmit Period Divider Selection
 
#define SSC_TCMR_PERIOD(value)   ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)))
 
#define SSC_TFMR_DATLEN_Pos   0
 
#define SSC_TFMR_DATLEN_Msk   (0x1fu << SSC_TFMR_DATLEN_Pos)
 (SSC_TFMR) Data Length
 
#define SSC_TFMR_DATLEN(value)   ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)))
 
#define SSC_TFMR_DATDEF   (0x1u << 5)
 (SSC_TFMR) Data Default Value
 
#define SSC_TFMR_MSBF   (0x1u << 7)
 (SSC_TFMR) Most Significant Bit First
 
#define SSC_TFMR_DATNB_Pos   8
 
#define SSC_TFMR_DATNB_Msk   (0xfu << SSC_TFMR_DATNB_Pos)
 (SSC_TFMR) Data Number per Frame
 
#define SSC_TFMR_DATNB(value)   ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)))
 
#define SSC_TFMR_FSLEN_Pos   16
 
#define SSC_TFMR_FSLEN_Msk   (0xfu << SSC_TFMR_FSLEN_Pos)
 (SSC_TFMR) Transmit Frame Sync Length
 
#define SSC_TFMR_FSLEN(value)   ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)))
 
#define SSC_TFMR_FSOS_Pos   20
 
#define SSC_TFMR_FSOS_Msk   (0x7u << SSC_TFMR_FSOS_Pos)
 (SSC_TFMR) Transmit Frame Sync Output Selection
 
#define SSC_TFMR_FSOS(value)   ((SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos)))
 
#define SSC_TFMR_FSOS_NONE   (0x0u << 20)
 (SSC_TFMR) None, TF pin is an input
 
#define SSC_TFMR_FSOS_NEGATIVE   (0x1u << 20)
 (SSC_TFMR) Negative Pulse, TF pin is an output
 
#define SSC_TFMR_FSOS_POSITIVE   (0x2u << 20)
 (SSC_TFMR) Positive Pulse, TF pin is an output
 
#define SSC_TFMR_FSOS_LOW   (0x3u << 20)
 (SSC_TFMR) Driven Low during data transfer
 
#define SSC_TFMR_FSOS_HIGH   (0x4u << 20)
 (SSC_TFMR) Driven High during data transfer
 
#define SSC_TFMR_FSOS_TOGGLING   (0x5u << 20)
 (SSC_TFMR) Toggling at each start of data transfer
 
#define SSC_TFMR_FSDEN   (0x1u << 23)
 (SSC_TFMR) Frame Sync Data Enable
 
#define SSC_TFMR_FSEDGE   (0x1u << 24)
 (SSC_TFMR) Frame Sync Edge Detection
 
#define SSC_TFMR_FSEDGE_POSITIVE   (0x0u << 24)
 (SSC_TFMR) Positive Edge Detection
 
#define SSC_TFMR_FSEDGE_NEGATIVE   (0x1u << 24)
 (SSC_TFMR) Negative Edge Detection
 
#define SSC_TFMR_FSLEN_EXT_Pos   28
 
#define SSC_TFMR_FSLEN_EXT_Msk   (0xfu << SSC_TFMR_FSLEN_EXT_Pos)
 (SSC_TFMR) FSLEN Field Extension
 
#define SSC_TFMR_FSLEN_EXT(value)   ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)))
 
#define SSC_RHR_RDAT_Pos   0
 
#define SSC_RHR_RDAT_Msk   (0xffffffffu << SSC_RHR_RDAT_Pos)
 (SSC_RHR) Receive Data
 
#define SSC_THR_TDAT_Pos   0
 
#define SSC_THR_TDAT_Msk   (0xffffffffu << SSC_THR_TDAT_Pos)
 (SSC_THR) Transmit Data
 
#define SSC_THR_TDAT(value)   ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)))
 
#define SSC_RSHR_RSDAT_Pos   0
 
#define SSC_RSHR_RSDAT_Msk   (0xffffu << SSC_RSHR_RSDAT_Pos)
 (SSC_RSHR) Receive Synchronization Data
 
#define SSC_TSHR_TSDAT_Pos   0
 
#define SSC_TSHR_TSDAT_Msk   (0xffffu << SSC_TSHR_TSDAT_Pos)
 (SSC_TSHR) Transmit Synchronization Data
 
#define SSC_TSHR_TSDAT(value)   ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)))
 
#define SSC_RC0R_CP0_Pos   0
 
#define SSC_RC0R_CP0_Msk   (0xffffu << SSC_RC0R_CP0_Pos)
 (SSC_RC0R) Receive Compare Data 0
 
#define SSC_RC0R_CP0(value)   ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)))
 
#define SSC_RC1R_CP1_Pos   0
 
#define SSC_RC1R_CP1_Msk   (0xffffu << SSC_RC1R_CP1_Pos)
 (SSC_RC1R) Receive Compare Data 1
 
#define SSC_RC1R_CP1(value)   ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)))
 
#define SSC_SR_TXRDY   (0x1u << 0)
 (SSC_SR) Transmit Ready
 
#define SSC_SR_TXEMPTY   (0x1u << 1)
 (SSC_SR) Transmit Empty
 
#define SSC_SR_RXRDY   (0x1u << 4)
 (SSC_SR) Receive Ready
 
#define SSC_SR_OVRUN   (0x1u << 5)
 (SSC_SR) Receive Overrun
 
#define SSC_SR_CP0   (0x1u << 8)
 (SSC_SR) Compare 0
 
#define SSC_SR_CP1   (0x1u << 9)
 (SSC_SR) Compare 1
 
#define SSC_SR_TXSYN   (0x1u << 10)
 (SSC_SR) Transmit Sync
 
#define SSC_SR_RXSYN   (0x1u << 11)
 (SSC_SR) Receive Sync
 
#define SSC_SR_TXEN   (0x1u << 16)
 (SSC_SR) Transmit Enable
 
#define SSC_SR_RXEN   (0x1u << 17)
 (SSC_SR) Receive Enable
 
#define SSC_IER_TXRDY   (0x1u << 0)
 (SSC_IER) Transmit Ready Interrupt Enable
 
#define SSC_IER_TXEMPTY   (0x1u << 1)
 (SSC_IER) Transmit Empty Interrupt Enable
 
#define SSC_IER_RXRDY   (0x1u << 4)
 (SSC_IER) Receive Ready Interrupt Enable
 
#define SSC_IER_OVRUN   (0x1u << 5)
 (SSC_IER) Receive Overrun Interrupt Enable
 
#define SSC_IER_CP0   (0x1u << 8)
 (SSC_IER) Compare 0 Interrupt Enable
 
#define SSC_IER_CP1   (0x1u << 9)
 (SSC_IER) Compare 1 Interrupt Enable
 
#define SSC_IER_TXSYN   (0x1u << 10)
 (SSC_IER) Tx Sync Interrupt Enable
 
#define SSC_IER_RXSYN   (0x1u << 11)
 (SSC_IER) Rx Sync Interrupt Enable
 
#define SSC_IDR_TXRDY   (0x1u << 0)
 (SSC_IDR) Transmit Ready Interrupt Disable
 
#define SSC_IDR_TXEMPTY   (0x1u << 1)
 (SSC_IDR) Transmit Empty Interrupt Disable
 
#define SSC_IDR_RXRDY   (0x1u << 4)
 (SSC_IDR) Receive Ready Interrupt Disable
 
#define SSC_IDR_OVRUN   (0x1u << 5)
 (SSC_IDR) Receive Overrun Interrupt Disable
 
#define SSC_IDR_CP0   (0x1u << 8)
 (SSC_IDR) Compare 0 Interrupt Disable
 
#define SSC_IDR_CP1   (0x1u << 9)
 (SSC_IDR) Compare 1 Interrupt Disable
 
#define SSC_IDR_TXSYN   (0x1u << 10)
 (SSC_IDR) Tx Sync Interrupt Enable
 
#define SSC_IDR_RXSYN   (0x1u << 11)
 (SSC_IDR) Rx Sync Interrupt Enable
 
#define SSC_IMR_TXRDY   (0x1u << 0)
 (SSC_IMR) Transmit Ready Interrupt Mask
 
#define SSC_IMR_TXEMPTY   (0x1u << 1)
 (SSC_IMR) Transmit Empty Interrupt Mask
 
#define SSC_IMR_RXRDY   (0x1u << 4)
 (SSC_IMR) Receive Ready Interrupt Mask
 
#define SSC_IMR_OVRUN   (0x1u << 5)
 (SSC_IMR) Receive Overrun Interrupt Mask
 
#define SSC_IMR_CP0   (0x1u << 8)
 (SSC_IMR) Compare 0 Interrupt Mask
 
#define SSC_IMR_CP1   (0x1u << 9)
 (SSC_IMR) Compare 1 Interrupt Mask
 
#define SSC_IMR_TXSYN   (0x1u << 10)
 (SSC_IMR) Tx Sync Interrupt Mask
 
#define SSC_IMR_RXSYN   (0x1u << 11)
 (SSC_IMR) Rx Sync Interrupt Mask
 
#define SSC_WPMR_WPEN   (0x1u << 0)
 (SSC_WPMR) Write Protection Enable
 
#define SSC_WPMR_WPKEY_Pos   8
 
#define SSC_WPMR_WPKEY_Msk   (0xffffffu << SSC_WPMR_WPKEY_Pos)
 (SSC_WPMR) Write Protection Key
 
#define SSC_WPMR_WPKEY(value)   ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)))
 
#define SSC_WPMR_WPKEY_PASSWD   (0x535343u << 8)
 (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
 
#define SSC_WPSR_WPVS   (0x1u << 0)
 (SSC_WPSR) Write Protection Violation Status
 
#define SSC_WPSR_WPVSRC_Pos   8
 
#define SSC_WPSR_WPVSRC_Msk   (0xffffu << SSC_WPSR_WPVSRC_Pos)
 (SSC_WPSR) Write Protect Violation Source
 

Detailed Description

SOFTWARE API DEFINITION FOR Synchronous Serial Controller

Generated by   doxygen 1.8.13