RTEMS
5.0.0
|
Mcan hardware registers. More...
#include <component_mcan.h>
Data Fields | |
__I uint32_t | Reserved1 [2] |
__IO uint32_t | MCAN_CUST |
(Mcan Offset: 0x08) Customer Register | |
__IO uint32_t | MCAN_FBTP |
(Mcan Offset: 0x0C) Fast Bit Timing and Prescaler Register | |
__IO uint32_t | MCAN_TEST |
(Mcan Offset: 0x10) Test Register | |
__IO uint32_t | MCAN_RWD |
(Mcan Offset: 0x14) RAM Watchdog Register | |
__IO uint32_t | MCAN_CCCR |
(Mcan Offset: 0x18) CC Control Register | |
__IO uint32_t | MCAN_BTP |
(Mcan Offset: 0x1C) Bit Timing and Prescaler Register | |
__IO uint32_t | MCAN_TSCC |
(Mcan Offset: 0x20) Timestamp Counter Configuration Register | |
__IO uint32_t | MCAN_TSCV |
(Mcan Offset: 0x24) Timestamp Counter Value Register | |
__IO uint32_t | MCAN_TOCC |
(Mcan Offset: 0x28) Timeout Counter Configuration Register | |
__IO uint32_t | MCAN_TOCV |
(Mcan Offset: 0x2C) Timeout Counter Value Register | |
__I uint32_t | Reserved2 [4] |
__I uint32_t | MCAN_ECR |
(Mcan Offset: 0x40) Error Counter Register | |
__I uint32_t | MCAN_PSR |
(Mcan Offset: 0x44) Protocol Status Register | |
__I uint32_t | Reserved3 [2] |
__IO uint32_t | MCAN_IR |
(Mcan Offset: 0x50) Interrupt Register | |
__IO uint32_t | MCAN_IE |
(Mcan Offset: 0x54) Interrupt Enable Register | |
__IO uint32_t | MCAN_ILS |
(Mcan Offset: 0x58) Interrupt Line Select Register | |
__IO uint32_t | MCAN_ILE |
(Mcan Offset: 0x5C) Interrupt Line Enable Register | |
__I uint32_t | Reserved4 [8] |
__IO uint32_t | MCAN_GFC |
(Mcan Offset: 0x80) Global Filter Configuration Register | |
__IO uint32_t | MCAN_SIDFC |
(Mcan Offset: 0x84) Standard ID Filter Configuration Register | |
__IO uint32_t | MCAN_XIDFC |
(Mcan Offset: 0x88) Extended ID Filter Configuration Register | |
__I uint32_t | Reserved5 [1] |
__IO uint32_t | MCAN_XIDAM |
(Mcan Offset: 0x90) Extended ID AND Mask Register | |
__I uint32_t | MCAN_HPMS |
(Mcan Offset: 0x94) High Priority Message Status Register | |
__IO uint32_t | MCAN_NDAT1 |
(Mcan Offset: 0x98) New Data 1 Register | |
__IO uint32_t | MCAN_NDAT2 |
(Mcan Offset: 0x9C) New Data 2 Register | |
__IO uint32_t | MCAN_RXF0C |
(Mcan Offset: 0xA0) Receive FIFO 0 Configuration Register | |
__I uint32_t | MCAN_RXF0S |
(Mcan Offset: 0xA4) Receive FIFO 0 Status Register | |
__IO uint32_t | MCAN_RXF0A |
(Mcan Offset: 0xA8) Receive FIFO 0 Acknowledge Register | |
__IO uint32_t | MCAN_RXBC |
(Mcan Offset: 0xAC) Receive Rx Buffer Configuration Register | |
__IO uint32_t | MCAN_RXF1C |
(Mcan Offset: 0xB0) Receive FIFO 1 Configuration Register | |
__I uint32_t | MCAN_RXF1S |
(Mcan Offset: 0xB4) Receive FIFO 1 Status Register | |
__IO uint32_t | MCAN_RXF1A |
(Mcan Offset: 0xB8) Receive FIFO 1 Acknowledge Register | |
__IO uint32_t | MCAN_RXESC |
(Mcan Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register | |
__IO uint32_t | MCAN_TXBC |
(Mcan Offset: 0xC0) Transmit Buffer Configuration Register | |
__I uint32_t | MCAN_TXFQS |
(Mcan Offset: 0xC4) Transmit FIFO/Queue Status Register | |
__IO uint32_t | MCAN_TXESC |
(Mcan Offset: 0xC8) Transmit Buffer Element Size Configuration Register | |
__I uint32_t | MCAN_TXBRP |
(Mcan Offset: 0xCC) Transmit Buffer Request Pending Register | |
__IO uint32_t | MCAN_TXBAR |
(Mcan Offset: 0xD0) Transmit Buffer Add Request Register | |
__IO uint32_t | MCAN_TXBCR |
(Mcan Offset: 0xD4) Transmit Buffer Cancellation Request Register | |
__I uint32_t | MCAN_TXBTO |
(Mcan Offset: 0xD8) Transmit Buffer Transmission Occurred Register | |
__I uint32_t | MCAN_TXBCF |
(Mcan Offset: 0xDC) Transmit Buffer Cancellation Finished Register | |
__IO uint32_t | MCAN_TXBTIE |
(Mcan Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register | |
__IO uint32_t | MCAN_TXBCIE |
(Mcan Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register | |
__I uint32_t | Reserved6 [2] |
__IO uint32_t | MCAN_TXEFC |
(Mcan Offset: 0xF0) Transmit Event FIFO Configuration Register | |
__I uint32_t | MCAN_TXEFS |
(Mcan Offset: 0xF4) Transmit Event FIFO Status Register | |
__IO uint32_t | MCAN_TXEFA |
(Mcan Offset: 0xF8) Transmit Event FIFO Acknowledge Register | |
__I uint32_t | MCAN_CREL |
(Mcan Offset: 0x00) Core Release Register | |
__I uint32_t | MCAN_ENDN |
(Mcan Offset: 0x04) Endian Register | |
Mcan hardware registers.