RTEMS  5.0.0
Data Structures | Macros | Typedefs | Enumerations | Functions | Variables
cpu.h File Reference

Intel I386 CPU Dependent Source. More...

#include <string.h>
#include <rtems/score/basedefs.h>
#include <rtems/score/i386.h>

Go to the source code of this file.

Data Structures

struct  Context_Control
 Thread register context. More...
 
struct  Context_Control_fp
 SPARC basic context. More...
 
struct  CPU_Exception_frame
 The set of registers that specifies the complete processor state. More...
 
struct  CPU_Interrupt_frame
 Interrupt stack frame (ISF). More...
 

Macros

#define CPU_SIMPLE_VECTORED_INTERRUPTS   FALSE
 
#define CPU_ISR_PASSES_FRAME_POINTER   FALSE
 
#define CPU_HARDWARE_FP   FALSE
 
#define CPU_SOFTWARE_FP   FALSE
 
#define CPU_ALL_TASKS_ARE_FP   FALSE
 
#define CPU_IDLE_TASK_IS_FP   FALSE
 
#define CPU_USE_DEFERRED_FP_SWITCH   TRUE
 
#define CPU_ENABLE_ROBUST_THREAD_DISPATCH   FALSE
 
#define CPU_STACK_GROWS_UP   FALSE
 
#define CPU_CACHE_LINE_BYTES   64
 
#define CPU_STRUCTURE_ALIGNMENT
 
#define CPU_MAXIMUM_PROCESSORS   32
 
#define I386_CONTEXT_CONTROL_EFLAGS_OFFSET   0
 
#define I386_CONTEXT_CONTROL_ESP_OFFSET   4
 
#define I386_CONTEXT_CONTROL_EBP_OFFSET   8
 
#define I386_CONTEXT_CONTROL_EBX_OFFSET   12
 
#define I386_CONTEXT_CONTROL_ESI_OFFSET   16
 
#define I386_CONTEXT_CONTROL_EDI_OFFSET   20
 
#define I386_CONTEXT_CONTROL_GS_0_OFFSET   24
 
#define I386_CONTEXT_CONTROL_GS_1_OFFSET   28
 
#define _CPU_Context_Get_SP(_context)   (_context)->esp
 
#define CPU_CONTEXT_FP_SIZE   sizeof( Context_Control_fp )
 
#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
 
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK   1024
 
#define CPU_PROVIDES_ISR_IS_IN_PROGRESS   FALSE
 
#define CPU_STACK_MINIMUM_SIZE   4096
 
#define CPU_SIZEOF_POINTER   4
 
#define CPU_ALIGNMENT   4
 
#define CPU_HEAP_ALIGNMENT   CPU_ALIGNMENT
 
#define CPU_STACK_ALIGNMENT   16
 
#define CPU_INTERRUPT_STACK_ALIGNMENT   CPU_CACHE_LINE_BYTES
 
#define _CPU_ISR_Disable(_level)   i386_disable_interrupts( _level )
 
#define _CPU_ISR_Enable(_level)   i386_enable_interrupts( _level )
 
#define _CPU_ISR_Flash(_level)   i386_flash_interrupts( _level )
 
#define _CPU_ISR_Set_level(_new_level)
 
#define _CPU_Interrupt_stack_setup(_lo, _hi)
 
#define CPU_EFLAGS_INTERRUPTS_ON   0x00003202
 
#define CPU_EFLAGS_INTERRUPTS_OFF   0x00003002
 
#define _CPU_Context_Restart_self(_the_context)   _CPU_Context_restore( (_the_context) );
 
#define _CPU_Context_Initialize_fp(_fp_area)
 
#define CPU_USE_GENERIC_BITFIELD_CODE   FALSE
 
#define _CPU_Bitfield_Find_first_bit(_value, _output)
 
#define _CPU_Priority_Mask(_bit_number)   ( 1 << (_bit_number) )
 
#define _CPU_Priority_bits_index(_priority)   (_priority)
 

Typedefs

typedef void(* cpuExcHandlerType) (CPU_Exception_frame *)
 
typedef void(* CPU_ISR_handler) (void)
 
typedef uint32_t CPU_Counter_ticks
 
typedef uintptr_t CPU_Uint32ptr
 

Enumerations

enum  Intel_symbolic_exception_name {
  I386_EXCEPTION_DIVIDE_BY_ZERO = 0, I386_EXCEPTION_DEBUG = 1, I386_EXCEPTION_NMI = 2, I386_EXCEPTION_BREAKPOINT = 3,
  I386_EXCEPTION_OVERFLOW = 4, I386_EXCEPTION_BOUND = 5, I386_EXCEPTION_ILLEGAL_INSTR = 6, I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7,
  I386_EXCEPTION_DOUBLE_FAULT = 8, I386_EXCEPTION_I386_COPROC_SEG_ERR = 9, I386_EXCEPTION_INVALID_TSS = 10, I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11,
  I386_EXCEPTION_STACK_SEGMENT_FAULT = 12, I386_EXCEPTION_GENERAL_PROT_ERR = 13, I386_EXCEPTION_PAGE_FAULT = 14, I386_EXCEPTION_INTEL_RES15 = 15,
  I386_EXCEPTION_FLOAT_ERROR = 16, I386_EXCEPTION_ALIGN_CHECK = 17, I386_EXCEPTION_MACHINE_CHECK = 18, I386_EXCEPTION_ENTER_RDBG = 50
}
 

Functions

void rtems_exception_init_mngt (void)
 
RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled (uint32_t level)
 
uint32_t _CPU_ISR_Get_level (void)
 
void _CPU_Context_Initialize (Context_Control *the_context, void *stack_area_begin, size_t stack_area_size, uint32_t new_level, void(*entry_point)(void), bool is_fp, void *tls_area)
 Initializes the CPU context. More...
 
void _CPU_Fatal_halt (uint32_t source, uint32_t error) RTEMS_NO_RETURN
 
void _CPU_Initialize (void)
 CPU initialization. More...
 
void _CPU_ISR_install_vector (uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)
 
void * _CPU_Thread_Idle_body (uintptr_t ignored)
 
void _CPU_Context_switch (Context_Control *run, Context_Control *heir)
 CPU switch context. More...
 
void _CPU_Context_restore (Context_Control *new_context) RTEMS_NO_RETURN
 
void _CPU_Context_save_fp (Context_Control_fp **fp_context_ptr)
 
void _CPU_Context_restore_fp (Context_Control_fp **fp_context_ptr)
 
void _CPU_Exception_frame_print (const CPU_Exception_frame *frame)
 Prints the exception frame via printk(). More...
 
uint32_t _CPU_Counter_frequency (void)
 
CPU_Counter_ticks _CPU_Counter_read (void)
 

Variables

cpuExcHandlerType _currentExcHandler
 
Context_Control_fp _CPU_Null_fp_context
 

Detailed Description

Intel I386 CPU Dependent Source.

This include file contains information pertaining to the Intel i386 processor.

Typedef Documentation

◆ CPU_Uint32ptr

typedef uintptr_t CPU_Uint32ptr

Type that can store a 32-bit integer or a pointer.