RTEMS  5.0.0
fsl-mpc5668.h
1 /*
2  * Modifications of the original file provided by Freescale are:
3  *
4  * Copyright (c) 2013 embedded brains GmbH. All rights reserved.
5  *
6  * embedded brains GmbH
7  * Dornierstr. 4
8  * 82178 Puchheim
9  * Germany
10  * <info@embedded-brains.de>
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  * notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  * notice, this list of conditions and the following disclaimer in the
19  * documentation and/or other materials provided with the distribution.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 /**************************************************************************
35  * FILE NAME: mpc5668.h COPYRIGHT (c) Freescale 2009 *
36  * REVISION: 1.1 All Rights Reserved *
37  * *
38  * DESCRIPTION: *
39  * This file contain all of the register and bit field definitions for *
40  * MPC5668. *
41  **************************************************************************/
42 /*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/
43 
44 /**************************************************************************
45  * Example register & bit field write: *
46  * *
47  * <MODULE>.<REGISTER>.B.<BIT> = 1; *
48  * <MODULE>.<REGISTER>.R = 0x10000000; *
49  * *
50  **************************************************************************/
51 
52 #ifndef _MPC5668_H_
53 #define _MPC5668_H_
54 
55 #ifndef ASM
56 
57 #include <stdint.h>
58 
59 #include <mpc55xx/regs-edma.h>
60 
61 #ifdef __cplusplus
62 extern "C" {
63 #endif
64 
65 #ifdef __MWERKS__
66 #pragma push
67 #pragma ANSI_strict off
68 #endif
69 
70 /*************************************************************************/
71 /* MODULE : ADC */
72 /*************************************************************************/
73  struct ADC_tag {
74 
75  union {
76  uint32_t R;
77  struct {
78  uint32_t OWREN:1;
79  uint32_t WLSIDE:1;
80  uint32_t MODE:1;
81  uint32_t EDGLEV:1;
82  uint32_t TRGEN:1;
83  uint32_t EDGE:1;
84  uint32_t XSTRTEN:1;
85  uint32_t NSTART:1;
86  uint32_t:1;
87  uint32_t JTRGEN:1;
88  uint32_t JEDGE:1;
89  uint32_t JSTART:1;
90  uint32_t:2;
91  uint32_t CTUEN:1;
92  uint32_t:8;
93  uint32_t ADCLKSEL:1;
94  uint32_t ABORTCHAIN:1;
95  uint32_t ABORT:1;
96  uint32_t ACKO:1;
97  uint32_t OFFREFRESH:1;
98  uint32_t OFFCANC:1;
99  uint32_t:2;
100  uint32_t PWDN:1;
101  } B;
102  } MCR; /* MAIN CONFIGURATION REGISTER */
103 
104  union {
105  uint32_t R;
106  struct {
107  uint32_t:7;
108  uint32_t NSTART:1;
109  uint32_t JABORT:1;
110  uint32_t:2;
111  uint32_t JSTART:1;
112  uint32_t:3;
113  uint32_t CTUSTART:1;
114  uint32_t CHADDR:7;
115  uint32_t:3;
116  uint32_t ACKO:1;
117  uint32_t OFFREFRESH:1;
118  uint32_t OFFCANC:1;
119  uint32_t ADCSTATUS:3;
120  } B;
121  } MSR; /* MAIN STATUS REGISTER */
122 
123  uint32_t adc_reserved1[2];
124 
125  union {
126  uint32_t R;
127  struct {
128  uint32_t:25;
129  uint32_t OFFCANCOVR:1;
130  uint32_t EOFFSET:1;
131  uint32_t EOCTU:1;
132  uint32_t JEOC:1;
133  uint32_t JECH:1;
134  uint32_t EOC:1;
135  uint32_t ECH:1;
136  } B;
137  } ISR; /* INTERRUPT STATUS REGISTER */
138 
139  union {
140  uint32_t R;
141  struct {
142  uint32_t EOCCH31:1;
143  uint32_t EOCCH30:1;
144  uint32_t EOCCH29:1;
145  uint32_t EOCCH28:1;
146  uint32_t EOCCH27:1;
147  uint32_t EOCCH26:1;
148  uint32_t EOCCH25:1;
149  uint32_t EOCCH24:1;
150  uint32_t EOCCH23:1;
151  uint32_t EOCCH22:1;
152  uint32_t EOCCH21:1;
153  uint32_t EOCCH20:1;
154  uint32_t EOCCH19:1;
155  uint32_t EOCCH18:1;
156  uint32_t EOCCH17:1;
157  uint32_t EOCCH16:1;
158  uint32_t EOCCH15:1;
159  uint32_t EOCCH14:1;
160  uint32_t EOCCH13:1;
161  uint32_t EOCCH12:1;
162  uint32_t EOCCH11:1;
163  uint32_t EOCCH10:1;
164  uint32_t EOCCH9:1;
165  uint32_t EOCCH8:1;
166  uint32_t EOCCH7:1;
167  uint32_t EOCCH6:1;
168  uint32_t EOCCH5:1;
169  uint32_t EOCCH4:1;
170  uint32_t EOCCH3:1;
171  uint32_t EOCCH2:1;
172  uint32_t EOCCH1:1;
173  uint32_t EOCCH0:1;
174  } B;
175  } CEOCFR0; /* CHANNEL PENDING REGISTER 0 */
176 
177  union {
178  uint32_t R;
179  struct {
180  uint32_t EOCCH63:1;
181  uint32_t EOCCH62:1;
182  uint32_t EOCCH61:1;
183  uint32_t EOCCH60:1;
184  uint32_t EOCCH59:1;
185  uint32_t EOCCH58:1;
186  uint32_t EOCCH57:1;
187  uint32_t EOCCH56:1;
188  uint32_t EOCCH55:1;
189  uint32_t EOCCH54:1;
190  uint32_t EOCCH53:1;
191  uint32_t EOCCH52:1;
192  uint32_t EOCCH51:1;
193  uint32_t EOCCH50:1;
194  uint32_t EOCCH49:1;
195  uint32_t EOCCH48:1;
196  uint32_t EOCCH47:1;
197  uint32_t EOCCH46:1;
198  uint32_t EOCCH45:1;
199  uint32_t EOCCH44:1;
200  uint32_t EOCCH43:1;
201  uint32_t EOCCH42:1;
202  uint32_t EOCCH41:1;
203  uint32_t EOCCH40:1;
204  uint32_t EOCCH39:1;
205  uint32_t EOCCH38:1;
206  uint32_t EOCCH37:1;
207  uint32_t EOCCH36:1;
208  uint32_t EOCCH35:1;
209  uint32_t EOCCH34:1;
210  uint32_t EOCCH33:1;
211  uint32_t EOCCH32:1;
212  } B;
213  } CEOCFR1; /* CHANNEL PENDING REGISTER 1 */
214 
215  union {
216  uint32_t R;
217  struct {
218  uint32_t EOCCH95:1;
219  uint32_t EOCCH94:1;
220  uint32_t EOCCH93:1;
221  uint32_t EOCCH92:1;
222  uint32_t EOCCH91:1;
223  uint32_t EOCCH90:1;
224  uint32_t EOCCH89:1;
225  uint32_t EOCCH88:1;
226  uint32_t EOCCH87:1;
227  uint32_t EOCCH86:1;
228  uint32_t EOCCH85:1;
229  uint32_t EOCCH84:1;
230  uint32_t EOCCH83:1;
231  uint32_t EOCCH82:1;
232  uint32_t EOCCH81:1;
233  uint32_t EOCCH80:1;
234  uint32_t EOCCH79:1;
235  uint32_t EOCCH78:1;
236  uint32_t EOCCH77:1;
237  uint32_t EOCCH76:1;
238  uint32_t EOCCH75:1;
239  uint32_t EOCCH74:1;
240  uint32_t EOCCH73:1;
241  uint32_t EOCCH72:1;
242  uint32_t EOCCH71:1;
243  uint32_t EOCCH70:1;
244  uint32_t EOCCH69:1;
245  uint32_t EOCCH68:1;
246  uint32_t EOCCH67:1;
247  uint32_t EOCCH66:1;
248  uint32_t EOCCH65:1;
249  uint32_t EOCCH64:1;
250  } B;
251  } CEOCFR2; /* CHANNEL PENDING REGISTER 2 */
252 
253  union {
254  uint32_t R;
255  struct {
256  uint32_t:25;
257  uint32_t MSKOFFCANCOVR:1;
258  uint32_t MSKEOFFSET:1;
259  uint32_t MSKEOCTU:1;
260  uint32_t MSKJEOC:1;
261  uint32_t MSKJECH:1;
262  uint32_t MSKEOC:1;
263  uint32_t MSKECH:1;
264  } B;
265  } IMR; /* INTERRUPT MASK REGISTER */
266 
267  union {
268  uint32_t R;
269  struct {
270  uint32_t CIM31:1;
271  uint32_t CIM30:1;
272  uint32_t CIM29:1;
273  uint32_t CIM28:1;
274  uint32_t CIM27:1;
275  uint32_t CIM26:1;
276  uint32_t CIM25:1;
277  uint32_t CIM24:1;
278  uint32_t CIM23:1;
279  uint32_t CIM22:1;
280  uint32_t CIM21:1;
281  uint32_t CIM20:1;
282  uint32_t CIM19:1;
283  uint32_t CIM18:1;
284  uint32_t CIM17:1;
285  uint32_t CIM16:1;
286  uint32_t CIM15:1;
287  uint32_t CIM14:1;
288  uint32_t CIM13:1;
289  uint32_t CIM12:1;
290  uint32_t CIM11:1;
291  uint32_t CIM10:1;
292  uint32_t CIM9:1;
293  uint32_t CIM8:1;
294  uint32_t CIM7:1;
295  uint32_t CIM6:1;
296  uint32_t CIM5:1;
297  uint32_t CIM4:1;
298  uint32_t CIM3:1;
299  uint32_t CIM2:1;
300  uint32_t CIM1:1;
301  uint32_t CIM0:1;
302  } B;
303  } CIMR0; /* CHANNEL INTERRUPT MASK REGISTER 0 */
304 
305  union {
306  uint32_t R;
307  struct {
308  uint32_t CIM63:1;
309  uint32_t CIM62:1;
310  uint32_t CIM61:1;
311  uint32_t CIM60:1;
312  uint32_t CIM59:1;
313  uint32_t CIM58:1;
314  uint32_t CIM57:1;
315  uint32_t CIM56:1;
316  uint32_t CIM55:1;
317  uint32_t CIM54:1;
318  uint32_t CIM53:1;
319  uint32_t CIM52:1;
320  uint32_t CIM51:1;
321  uint32_t CIM50:1;
322  uint32_t CIM49:1;
323  uint32_t CIM48:1;
324  uint32_t CIM47:1;
325  uint32_t CIM46:1;
326  uint32_t CIM45:1;
327  uint32_t CIM44:1;
328  uint32_t CIM43:1;
329  uint32_t CIM42:1;
330  uint32_t CIM41:1;
331  uint32_t CIM40:1;
332  uint32_t CIM39:1;
333  uint32_t CIM38:1;
334  uint32_t CIM37:1;
335  uint32_t CIM36:1;
336  uint32_t CIM35:1;
337  uint32_t CIM34:1;
338  uint32_t CIM33:1;
339  uint32_t CIM32:1;
340  } B;
341  } CIMR1; /* CHANNEL INTERRUPT MASK REGISTER 1 */
342 
343  union {
344  uint32_t R;
345  struct {
346  uint32_t CIM63:1;
347  uint32_t CIM62:1;
348  uint32_t CIM61:1;
349  uint32_t CIM60:1;
350  uint32_t CIM59:1;
351  uint32_t CIM58:1;
352  uint32_t CIM57:1;
353  uint32_t CIM56:1;
354  uint32_t CIM55:1;
355  uint32_t CIM54:1;
356  uint32_t CIM53:1;
357  uint32_t CIM52:1;
358  uint32_t CIM51:1;
359  uint32_t CIM50:1;
360  uint32_t CIM49:1;
361  uint32_t CIM48:1;
362  uint32_t CIM47:1;
363  uint32_t CIM46:1;
364  uint32_t CIM45:1;
365  uint32_t CIM44:1;
366  uint32_t CIM43:1;
367  uint32_t CIM42:1;
368  uint32_t CIM41:1;
369  uint32_t CIM40:1;
370  uint32_t CIM39:1;
371  uint32_t CIM38:1;
372  uint32_t CIM37:1;
373  uint32_t CIM36:1;
374  uint32_t CIM35:1;
375  uint32_t CIM34:1;
376  uint32_t CIM33:1;
377  uint32_t CIM32:1;
378  } B;
379  } CIMR2; /* CHANNEL INTERRUPT MASK REGISTER 2 */
380 
381  union {
382  uint32_t R;
383  struct {
384  uint32_t:24;
385  uint32_t WDG3H:1;
386  uint32_t WDG2H:1;
387  uint32_t WDG1H:1;
388  uint32_t WDG0H:1;
389  uint32_t WDG3L:1;
390  uint32_t WDG2L:1;
391  uint32_t WDG1L:1;
392  uint32_t WDG0L:1;
393  } B;
394  } WTISR; /* WATCHDOG INTERRUPT THRESHOLD REGISTER */
395 
396  union {
397  uint32_t R;
398  struct {
399  uint32_t:24;
400  uint32_t MSKWDG3H:1;
401  uint32_t MSKWDG2H:1;
402  uint32_t MSKWDG1H:1;
403  uint32_t MSKWDG0H:1;
404  uint32_t MSKWDG3L:1;
405  uint32_t MSKWDG2L:1;
406  uint32_t MSKWDG1L:1;
407  uint32_t MSKWDG0L:1;
408  } B;
409  } WTIMR; /* WATCHDOG INTERRUPT THRESHOLD MASK REGISTER */
410 
411  uint32_t adc_reserved2[2];
412 
413  union {
414  uint32_t R;
415  struct {
416  uint32_t:30;
417  uint32_t DCLR:1;
418  uint32_t DMAEN:1;
419  } B;
420  } DMAE; /* DMA ENABLE REGISTER */
421 
422  union {
423  uint32_t R;
424  struct {
425  uint32_t DMA31:1;
426  uint32_t DMA30:1;
427  uint32_t DMA29:1;
428  uint32_t DMA28:1;
429  uint32_t DMA27:1;
430  uint32_t DMA26:1;
431  uint32_t DMA25:1;
432  uint32_t DMA24:1;
433  uint32_t DMA23:1;
434  uint32_t DMA22:1;
435  uint32_t DMA21:1;
436  uint32_t DMA20:1;
437  uint32_t DMA19:1;
438  uint32_t DMA18:1;
439  uint32_t DMA17:1;
440  uint32_t DMA16:1;
441  uint32_t DMA15:1;
442  uint32_t DMA14:1;
443  uint32_t DMA13:1;
444  uint32_t DMA12:1;
445  uint32_t DMA11:1;
446  uint32_t DMA10:1;
447  uint32_t DMA9:1;
448  uint32_t DMA8:1;
449  uint32_t DMA7:1;
450  uint32_t DMA6:1;
451  uint32_t DMA5:1;
452  uint32_t DMA4:1;
453  uint32_t DMA3:1;
454  uint32_t DMA2:1;
455  uint32_t DMA1:1;
456  uint32_t DMA0:1;
457  } B;
458  } DMAR0; /* DMA CHANNEL SELECT REGISTER 0 */
459 
460  union {
461  uint32_t R;
462  struct {
463  uint32_t DMA63:1;
464  uint32_t DMA62:1;
465  uint32_t DMA61:1;
466  uint32_t DMA60:1;
467  uint32_t DMA59:1;
468  uint32_t DMA58:1;
469  uint32_t DMA57:1;
470  uint32_t DMA56:1;
471  uint32_t DMA55:1;
472  uint32_t DMA54:1;
473  uint32_t DMA53:1;
474  uint32_t DMA52:1;
475  uint32_t DMA51:1;
476  uint32_t DMA50:1;
477  uint32_t DMA49:1;
478  uint32_t DMA48:1;
479  uint32_t DMA47:1;
480  uint32_t DMA46:1;
481  uint32_t DMA45:1;
482  uint32_t DMA44:1;
483  uint32_t DMA43:1;
484  uint32_t DMA42:1;
485  uint32_t DMA41:1;
486  uint32_t DMA40:1;
487  uint32_t DMA39:1;
488  uint32_t DMA38:1;
489  uint32_t DMA37:1;
490  uint32_t DMA36:1;
491  uint32_t DMA35:1;
492  uint32_t DMA34:1;
493  uint32_t DMA33:1;
494  uint32_t DMA32:1;
495  } B;
496  } DMAR1; /* DMA CHANNEL SELECT REGISTER 1 */
497 
498  union {
499  uint32_t R;
500  struct {
501  uint32_t DMA95:1;
502  uint32_t DMA94:1;
503  uint32_t DMA93:1;
504  uint32_t DMA92:1;
505  uint32_t DMA91:1;
506  uint32_t DMA90:1;
507  uint32_t DMA89:1;
508  uint32_t DMA88:1;
509  uint32_t DMA87:1;
510  uint32_t DMA86:1;
511  uint32_t DMA85:1;
512  uint32_t DMA84:1;
513  uint32_t DMA83:1;
514  uint32_t DMA82:1;
515  uint32_t DMA81:1;
516  uint32_t DMA80:1;
517  uint32_t DMA79:1;
518  uint32_t DMA78:1;
519  uint32_t DMA77:1;
520  uint32_t DMA76:1;
521  uint32_t DMA75:1;
522  uint32_t DMA74:1;
523  uint32_t DMA73:1;
524  uint32_t DMA72:1;
525  uint32_t DMA71:1;
526  uint32_t DMA70:1;
527  uint32_t DMA69:1;
528  uint32_t DMA68:1;
529  uint32_t DMA67:1;
530  uint32_t DMA66:1;
531  uint32_t DMA65:1;
532  uint32_t DMA64:1;
533  } B;
534  } DMAR2; /* DMA CHANNEL SELECT REGISTER 2 */
535 
536  union {
537  uint32_t R;
538  struct {
539  uint32_t:16;
540  uint32_t THREN:1;
541  uint32_t THRINV:1;
542  uint32_t THROP:1;
543  uint32_t:6;
544  uint32_t THRCH:7;
545  } B;
546  } TRC[4]; /* THRESHOLD CONTROL REGISTER */
547 
548  union {
549  uint32_t R;
550  struct {
551  uint32_t:6;
552  uint32_t THRH:10;
553  uint32_t:6;
554  uint32_t THRL:10;
555  } B;
556  } THRHLR[4]; /* THRESHOLD REGISTER */
557 
558  union {
559  uint32_t R;
560  struct {
561  uint32_t:6;
562  uint32_t THRH:10;
563  uint32_t:6;
564  uint32_t THRL:10;
565  } B;
566  } THRALT[4]; /* ALTERNATE THRESHOLD REGISTER */
567 
568  union {
569  uint32_t R;
570  struct {
571  uint32_t:25;
572  uint32_t PREVAL2:2;
573  uint32_t PREVAL1:2;
574  uint32_t PREVAL0:2;
575  uint32_t PRECONV:1;
576  } B;
577  } PSCR; /* PRESAMPLING CONTROL REGISTER */
578 
579  union {
580  uint32_t R;
581  struct {
582  uint32_t PSR31:1;
583  uint32_t PSR30:1;
584  uint32_t PSR29:1;
585  uint32_t PSR28:1;
586  uint32_t PSR27:1;
587  uint32_t PSR26:1;
588  uint32_t PSR25:1;
589  uint32_t PSR24:1;
590  uint32_t PSR23:1;
591  uint32_t PSR22:1;
592  uint32_t PSR21:1;
593  uint32_t PSR20:1;
594  uint32_t PSR19:1;
595  uint32_t PSR18:1;
596  uint32_t PSR17:1;
597  uint32_t PSR16:1;
598  uint32_t PSR15:1;
599  uint32_t PSR14:1;
600  uint32_t PSR13:1;
601  uint32_t PSR12:1;
602  uint32_t PSR11:1;
603  uint32_t PSR10:1;
604  uint32_t PSR9:1;
605  uint32_t PSR8:1;
606  uint32_t PSR7:1;
607  uint32_t PSR6:1;
608  uint32_t PSR5:1;
609  uint32_t PSR4:1;
610  uint32_t PSR3:1;
611  uint32_t PSR2:1;
612  uint32_t PSR1:1;
613  uint32_t PSR0:1;
614  } B;
615  } PSR0; /* PRESAMPLING REGISTER 0 */
616 
617  union {
618  uint32_t R;
619  struct {
620  uint32_t PSR63:1;
621  uint32_t PSR62:1;
622  uint32_t PSR61:1;
623  uint32_t PSR60:1;
624  uint32_t PSR59:1;
625  uint32_t PSR58:1;
626  uint32_t PSR57:1;
627  uint32_t PSR56:1;
628  uint32_t PSR55:1;
629  uint32_t PSR54:1;
630  uint32_t PSR53:1;
631  uint32_t PSR52:1;
632  uint32_t PSR51:1;
633  uint32_t PSR50:1;
634  uint32_t PSR49:1;
635  uint32_t PSR48:1;
636  uint32_t PSR47:1;
637  uint32_t PSR46:1;
638  uint32_t PSR45:1;
639  uint32_t PSR44:1;
640  uint32_t PSR43:1;
641  uint32_t PSR42:1;
642  uint32_t PSR41:1;
643  uint32_t PSR40:1;
644  uint32_t PSR39:1;
645  uint32_t PSR38:1;
646  uint32_t PSR37:1;
647  uint32_t PSR36:1;
648  uint32_t PSR35:1;
649  uint32_t PSR34:1;
650  uint32_t PSR33:1;
651  uint32_t PSR32:1;
652  } B;
653  } PSR1; /* PRESAMPLING REGISTER 1 */
654 
655  union {
656  uint32_t R;
657  struct {
658  uint32_t PSR95:1;
659  uint32_t PSR94:1;
660  uint32_t PSR93:1;
661  uint32_t PSR92:1;
662  uint32_t PSR91:1;
663  uint32_t PSR90:1;
664  uint32_t PSR89:1;
665  uint32_t PSR88:1;
666  uint32_t PSR87:1;
667  uint32_t PSR86:1;
668  uint32_t PSR85:1;
669  uint32_t PSR84:1;
670  uint32_t PSR83:1;
671  uint32_t PSR82:1;
672  uint32_t PSR81:1;
673  uint32_t PSR80:1;
674  uint32_t PSR79:1;
675  uint32_t PSR78:1;
676  uint32_t PSR77:1;
677  uint32_t PSR76:1;
678  uint32_t PSR75:1;
679  uint32_t PSR74:1;
680  uint32_t PSR73:1;
681  uint32_t PSR72:1;
682  uint32_t PSR71:1;
683  uint32_t PSR70:1;
684  uint32_t PSR69:1;
685  uint32_t PSR68:1;
686  uint32_t PSR67:1;
687  uint32_t PSR66:1;
688  uint32_t PSR65:1;
689  uint32_t PSR64:1;
690  } B;
691  } PSR2; /* PRESAMPLING REGISTER 2 */
692 
693  uint32_t adc_reserved3;
694 
695  union {
696  uint32_t R;
697  struct {
698  uint32_t:16;
699  uint32_t INPLATCH:1;
700  uint32_t:1;
701  uint32_t OFFSHIFT:2;
702  uint32_t:1;
703  uint32_t INPCMP:2;
704  uint32_t:1;
705  uint32_t INPSAMP:8;
706  } B;
707  } CTR0; /* CONVERSION TIMING REGISTER 0 */
708 
709  union {
710  uint32_t R;
711  struct {
712  uint32_t:16;
713  uint32_t INPLATCH:1;
714  uint32_t:4;
715  uint32_t INPCMP:2;
716  uint32_t:1;
717  uint32_t INPSAMP:8;
718  } B;
719  } CTR1; /* CONVERSION TIMING REGISTER 1 */
720 
721  union {
722  uint32_t R;
723  struct {
724  uint32_t:16;
725  uint32_t INPLATCH:1;
726  uint32_t:4;
727  uint32_t INPCMP:2;
728  uint32_t:1;
729  uint32_t INPSAMP:8;
730  } B;
731  } CTR2; /* CONVERSION TIMING REGISTER 2 */
732 
733  uint32_t adc_reserved4;
734 
735  union {
736  uint32_t R;
737  struct {
738  uint32_t CH31:1;
739  uint32_t CH30:1;
740  uint32_t CH29:1;
741  uint32_t CH28:1;
742  uint32_t CH27:1;
743  uint32_t CH26:1;
744  uint32_t CH25:1;
745  uint32_t CH24:1;
746  uint32_t CH23:1;
747  uint32_t CH22:1;
748  uint32_t CH21:1;
749  uint32_t CH20:1;
750  uint32_t CH19:1;
751  uint32_t CH18:1;
752  uint32_t CH17:1;
753  uint32_t CH16:1;
754  uint32_t CH15:1;
755  uint32_t CH14:1;
756  uint32_t CH13:1;
757  uint32_t CH12:1;
758  uint32_t CH11:1;
759  uint32_t CH10:1;
760  uint32_t CH9:1;
761  uint32_t CH8:1;
762  uint32_t CH7:1;
763  uint32_t CH6:1;
764  uint32_t CH5:1;
765  uint32_t CH4:1;
766  uint32_t CH3:1;
767  uint32_t CH2:1;
768  uint32_t CH1:1;
769  uint32_t CH0:1;
770  } B;
771  } NCMR0; /* NORMAL CONVERSION MASK REGISTER 0 */
772 
773  union {
774  uint32_t R;
775  struct {
776  uint32_t CH63:1;
777  uint32_t CH62:1;
778  uint32_t CH61:1;
779  uint32_t CH60:1;
780  uint32_t CH59:1;
781  uint32_t CH58:1;
782  uint32_t CH57:1;
783  uint32_t CH56:1;
784  uint32_t CH55:1;
785  uint32_t CH54:1;
786  uint32_t CH53:1;
787  uint32_t CH52:1;
788  uint32_t CH51:1;
789  uint32_t CH50:1;
790  uint32_t CH49:1;
791  uint32_t CH48:1;
792  uint32_t CH47:1;
793  uint32_t CH46:1;
794  uint32_t CH45:1;
795  uint32_t CH44:1;
796  uint32_t CH43:1;
797  uint32_t CH42:1;
798  uint32_t CH41:1;
799  uint32_t CH40:1;
800  uint32_t CH39:1;
801  uint32_t CH38:1;
802  uint32_t CH37:1;
803  uint32_t CH36:1;
804  uint32_t CH35:1;
805  uint32_t CH34:1;
806  uint32_t CH33:1;
807  uint32_t CH32:1;
808  } B;
809  } NCMR1; /* NORMAL CONVERSION MASK REGISTER 1 */
810 
811  union {
812  uint32_t R;
813  struct {
814  uint32_t PSR95:1;
815  uint32_t PSR94:1;
816  uint32_t PSR93:1;
817  uint32_t PSR92:1;
818  uint32_t PSR91:1;
819  uint32_t PSR90:1;
820  uint32_t PSR89:1;
821  uint32_t PSR88:1;
822  uint32_t PSR87:1;
823  uint32_t PSR86:1;
824  uint32_t PSR85:1;
825  uint32_t PSR84:1;
826  uint32_t PSR83:1;
827  uint32_t PSR82:1;
828  uint32_t PSR81:1;
829  uint32_t PSR80:1;
830  uint32_t PSR79:1;
831  uint32_t PSR78:1;
832  uint32_t PSR77:1;
833  uint32_t PSR76:1;
834  uint32_t PSR75:1;
835  uint32_t PSR74:1;
836  uint32_t PSR73:1;
837  uint32_t PSR72:1;
838  uint32_t PSR71:1;
839  uint32_t PSR70:1;
840  uint32_t PSR69:1;
841  uint32_t PSR68:1;
842  uint32_t PSR67:1;
843  uint32_t PSR66:1;
844  uint32_t PSR65:1;
845  uint32_t PSR64:1;
846  } B;
847  } NCMR2; /* NORMAL CONVERSION MASK REGISTER 2 */
848 
849  uint32_t adc_reserved5;
850 
851  union {
852  uint32_t R;
853  struct {
854  uint32_t CH31:1;
855  uint32_t CH30:1;
856  uint32_t CH29:1;
857  uint32_t CH28:1;
858  uint32_t CH27:1;
859  uint32_t CH26:1;
860  uint32_t CH25:1;
861  uint32_t CH24:1;
862  uint32_t CH23:1;
863  uint32_t CH22:1;
864  uint32_t CH21:1;
865  uint32_t CH20:1;
866  uint32_t CH19:1;
867  uint32_t CH18:1;
868  uint32_t CH17:1;
869  uint32_t CH16:1;
870  uint32_t CH15:1;
871  uint32_t CH14:1;
872  uint32_t CH13:1;
873  uint32_t CH12:1;
874  uint32_t CH11:1;
875  uint32_t CH10:1;
876  uint32_t CH9:1;
877  uint32_t CH8:1;
878  uint32_t CH7:1;
879  uint32_t CH6:1;
880  uint32_t CH5:1;
881  uint32_t CH4:1;
882  uint32_t CH3:1;
883  uint32_t CH2:1;
884  uint32_t CH1:1;
885  uint32_t CH0:1;
886  } B;
887  } JCMR0; /* INJECTED CONVERSION MASK REGISTER 0 */
888 
889  union {
890  uint32_t R;
891  struct {
892  uint32_t CH63:1;
893  uint32_t CH62:1;
894  uint32_t CH61:1;
895  uint32_t CH60:1;
896  uint32_t CH59:1;
897  uint32_t CH58:1;
898  uint32_t CH57:1;
899  uint32_t CH56:1;
900  uint32_t CH55:1;
901  uint32_t CH54:1;
902  uint32_t CH53:1;
903  uint32_t CH52:1;
904  uint32_t CH51:1;
905  uint32_t CH50:1;
906  uint32_t CH49:1;
907  uint32_t CH48:1;
908  uint32_t CH47:1;
909  uint32_t CH46:1;
910  uint32_t CH45:1;
911  uint32_t CH44:1;
912  uint32_t CH43:1;
913  uint32_t CH42:1;
914  uint32_t CH41:1;
915  uint32_t CH40:1;
916  uint32_t CH39:1;
917  uint32_t CH38:1;
918  uint32_t CH37:1;
919  uint32_t CH36:1;
920  uint32_t CH35:1;
921  uint32_t CH34:1;
922  uint32_t CH33:1;
923  uint32_t CH32:1;
924  } B;
925  } JCMR1; /* INJECTED CONVERSION MASK REGISTER 1 */
926 
927  union {
928  uint32_t R;
929  struct {
930  uint32_t PSR95:1;
931  uint32_t PSR94:1;
932  uint32_t PSR93:1;
933  uint32_t PSR92:1;
934  uint32_t PSR91:1;
935  uint32_t PSR90:1;
936  uint32_t PSR89:1;
937  uint32_t PSR88:1;
938  uint32_t PSR87:1;
939  uint32_t PSR86:1;
940  uint32_t PSR85:1;
941  uint32_t PSR84:1;
942  uint32_t PSR83:1;
943  uint32_t PSR82:1;
944  uint32_t PSR81:1;
945  uint32_t PSR80:1;
946  uint32_t PSR79:1;
947  uint32_t PSR78:1;
948  uint32_t PSR77:1;
949  uint32_t PSR76:1;
950  uint32_t PSR75:1;
951  uint32_t PSR74:1;
952  uint32_t PSR73:1;
953  uint32_t PSR72:1;
954  uint32_t PSR71:1;
955  uint32_t PSR70:1;
956  uint32_t PSR69:1;
957  uint32_t PSR68:1;
958  uint32_t PSR67:1;
959  uint32_t PSR66:1;
960  uint32_t PSR65:1;
961  uint32_t PSR64:1;
962  } B;
963  } JCMR2; /* INJECTED CONVERSION MASK REGISTER 2 */
964 
965  union {
966  uint32_t R;
967  struct {
968  uint32_t:15;
969  uint32_t OFFSETLOAD:1;
970  uint32_t:8;
971  uint32_t OFFSET_WORD:8;
972  } B;
973  } OFFWR; /* OFFSET WORD REGISTER */
974 
975  union {
976  uint32_t R;
977  struct {
978  uint32_t:24;
979  uint32_t DSD:8;
980  } B;
981  } DSDR; /* DECODE SIGNALS DELAY REGISTER */
982 
983  union {
984  uint32_t R;
985  struct {
986  uint32_t:24;
987  uint32_t PDED:8;
988  } B;
989  } PDEDR; /* DECODE SIGNALS DELAY REGISTER */
990 
991  uint32_t adc_reserved6[9];
992 
993  union {
994  uint32_t R;
995  struct {
996  uint32_t:16;
997  uint32_t TEST_CTL:16;
998  } B;
999  } TCTLR; /* TEST CONTROL REGISTER */
1000 
1001  uint32_t adc_reserved7[3];
1002 
1003  union {
1004  uint32_t R;
1005  struct {
1006  uint32_t:12;
1007  uint32_t VALID:1;
1008  uint32_t OVERW:1;
1009  uint32_t RESULT:2;
1010  uint32_t:6;
1011  uint32_t CDATA:10;
1012  } B;
1013  } PRECDATAREG[32]; /* PRESISION DATA REGISTER */
1014 
1015  union {
1016  uint32_t R;
1017  struct {
1018  uint32_t:12;
1019  uint32_t VALID:1;
1020  uint32_t OVERW:1;
1021  uint32_t RESULT:2;
1022  uint32_t:6;
1023  uint32_t CDATA:10;
1024  } B;
1025  } INTDATAREG[32]; /* PRESISION DATA REGISTER */
1026 
1027  union {
1028  uint32_t R;
1029  struct {
1030  uint32_t:12;
1031  uint32_t VALID:1;
1032  uint32_t OVERW:1;
1033  uint32_t RESULT:2;
1034  uint32_t:6;
1035  uint32_t CDATA:10;
1036  } B;
1037  } EXTDATAREG[32]; /* PRESISION DATA REGISTER */
1038 
1039  }; /* end of ADC_tag */
1040 /**************************************************************************/
1041 /* MODULE : AXBS Crossbar Switch (XBAR) */
1042 /**************************************************************************/
1043  struct XBAR_tag {
1044 
1045  union {
1046  uint32_t R;
1047  struct {
1048  uint32_t:1;
1049  uint32_t MSTR7:3;
1050  uint32_t:1;
1051  uint32_t MSTR6:3;
1052  uint32_t:9;
1053  uint32_t MSTR5:3;
1054  uint32_t:1;
1055  uint32_t MSTR3:3;
1056  uint32_t:1;
1057  uint32_t MSTR2:3;
1058  uint32_t:1;
1059  uint32_t MSTR1:3;
1060  uint32_t:1;
1061  uint32_t MSTR0:1;
1062  } B;
1063  } MPR0; /* Master Priority Register 0 */
1064 
1065  uint32_t xbar_reserved1[3];
1066 
1067  union {
1068  uint32_t R;
1069  struct {
1070  uint32_t R0:1;
1071  uint32_t:21;
1072  uint32_t ARB:2;
1073  uint32_t:2;
1074  uint32_t PCTL:2;
1075  uint32_t:1;
1076  uint32_t PARK:3;
1077  } B;
1078  } SGPCR0; /* Master Priority Register 0 */
1079 
1080  uint32_t xbar_reserved2[58];
1081 
1082  union {
1083  uint32_t R;
1084  struct {
1085  uint32_t:1;
1086  uint32_t MSTR7:3;
1087  uint32_t:1;
1088  uint32_t MSTR6:3;
1089  uint32_t:9;
1090  uint32_t MSTR5:3;
1091  uint32_t:1;
1092  uint32_t MSTR3:3;
1093  uint32_t:1;
1094  uint32_t MSTR2:3;
1095  uint32_t:1;
1096  uint32_t MSTR1:3;
1097  uint32_t:1;
1098  uint32_t MSTR0:1;
1099  } B;
1100  } MPR1; /* Master Priority Register 1 */
1101 
1102  uint32_t xbar_reserved3[3];
1103 
1104  union {
1105  uint32_t R;
1106  struct {
1107  uint32_t R0:1;
1108  uint32_t:21;
1109  uint32_t ARB:2;
1110  uint32_t:2;
1111  uint32_t PCTL:2;
1112  uint32_t:1;
1113  uint32_t PARK:3;
1114  } B;
1115  } SGPCR1; /* Master Priority Register 1 */
1116 
1117  uint32_t xbar_reserved4[58];
1118 
1119  union {
1120  uint32_t R;
1121  struct {
1122  uint32_t:1;
1123  uint32_t MSTR7:3;
1124  uint32_t:1;
1125  uint32_t MSTR6:3;
1126  uint32_t:9;
1127  uint32_t MSTR5:3;
1128  uint32_t:1;
1129  uint32_t MSTR3:3;
1130  uint32_t:1;
1131  uint32_t MSTR2:3;
1132  uint32_t:1;
1133  uint32_t MSTR1:3;
1134  uint32_t:1;
1135  uint32_t MSTR0:1;
1136  } B;
1137  } MPR2; /* Master Priority Register 2 */
1138 
1139  uint32_t xbar_reserved5[3];
1140 
1141  union {
1142  uint32_t R;
1143  struct {
1144  uint32_t R0:1;
1145  uint32_t:21;
1146  uint32_t ARB:2;
1147  uint32_t:2;
1148  uint32_t PCTL:2;
1149  uint32_t:1;
1150  uint32_t PARK:3;
1151  } B;
1152  } SGPCR2; /* Master Priority Register 2 */
1153 
1154  uint32_t xbar_reserved6[58];
1155 
1156  union {
1157  uint32_t R;
1158  struct {
1159  uint32_t:1;
1160  uint32_t MSTR7:3;
1161  uint32_t:1;
1162  uint32_t MSTR6:3;
1163  uint32_t:9;
1164  uint32_t MSTR5:3;
1165  uint32_t:1;
1166  uint32_t MSTR3:3;
1167  uint32_t:1;
1168  uint32_t MSTR2:3;
1169  uint32_t:1;
1170  uint32_t MSTR1:3;
1171  uint32_t:1;
1172  uint32_t MSTR0:1;
1173  } B;
1174  } MPR3; /* Master Priority Register 3 */
1175 
1176  uint32_t xbar_reserved7[3];
1177 
1178  union {
1179  uint32_t R;
1180  struct {
1181  uint32_t R0:1;
1182  uint32_t:21;
1183  uint32_t ARB:2;
1184  uint32_t:2;
1185  uint32_t PCTL:2;
1186  uint32_t:1;
1187  uint32_t PARK:3;
1188  } B;
1189  } SGPCR3; /* Master Priority Register 3 */
1190 
1191  uint32_t xbar_reserved8[186];
1192 
1193  union {
1194  uint32_t R;
1195  struct {
1196  uint32_t:1;
1197  uint32_t MSTR7:3;
1198  uint32_t:1;
1199  uint32_t MSTR6:3;
1200  uint32_t:9;
1201  uint32_t MSTR5:3;
1202  uint32_t:1;
1203  uint32_t MSTR3:3;
1204  uint32_t:1;
1205  uint32_t MSTR2:3;
1206  uint32_t:1;
1207  uint32_t MSTR1:3;
1208  uint32_t:1;
1209  uint32_t MSTR0:1;
1210  } B;
1211  } MPR6; /* Master Priority Register 6 */
1212 
1213  uint32_t xbar_reserved9[3];
1214 
1215  union {
1216  uint32_t R;
1217  struct {
1218  uint32_t R0:1;
1219  uint32_t:21;
1220  uint32_t ARB:2;
1221  uint32_t:2;
1222  uint32_t PCTL:2;
1223  uint32_t:1;
1224  uint32_t PARK:3;
1225  } B;
1226  } SGPCR6; /* Master Priority Register 6 */
1227 
1228  uint32_t xbar_reserved10[58];
1229 
1230  union {
1231  uint32_t R;
1232  struct {
1233  uint32_t:1;
1234  uint32_t MSTR7:3;
1235  uint32_t:1;
1236  uint32_t MSTR6:3;
1237  uint32_t:9;
1238  uint32_t MSTR5:3;
1239  uint32_t:1;
1240  uint32_t MSTR3:3;
1241  uint32_t:1;
1242  uint32_t MSTR2:3;
1243  uint32_t:1;
1244  uint32_t MSTR1:3;
1245  uint32_t:1;
1246  uint32_t MSTR0:1;
1247  } B;
1248  } MPR7; /* Master Priority Register 7 */
1249 
1250  uint32_t xbar_reserved11[3];
1251 
1252  union {
1253  uint32_t R;
1254  struct {
1255  uint32_t R0:1;
1256  uint32_t:21;
1257  uint32_t ARB:2;
1258  uint32_t:2;
1259  uint32_t PCTL:2;
1260  uint32_t:1;
1261  uint32_t PARK:3;
1262  } B;
1263  } SGPCR7; /* Master Priority Register 7 */
1264 
1265  uint32_t xbar_reserved12[506];
1266 
1267  union {
1268  uint32_t R;
1269  struct {
1270  uint32_t R0:1;
1271  uint32_t:21;
1272  uint32_t ARB:2;
1273  uint32_t:2;
1274  uint32_t PCTL:2;
1275  uint32_t:1;
1276  uint32_t PARK:3;
1277  } B;
1278  } MGPCR7; /* Master General Purpose Register 7 */
1279 
1280  };
1281 /*************************************************************************/
1282 /* MODULE : CRP */
1283 /*************************************************************************/
1284  struct CRP_tag {
1285 
1286  union {
1287  uint32_t R;
1288  struct {
1289  uint32_t IRCTRIMEN:1;
1290  uint32_t:4;
1291  uint32_t PREDIV:3;
1292  uint32_t:4;
1293  uint32_t EN128KIRC:1;
1294  uint32_t EN32KOSC:1;
1295  uint32_t ENLPOSC:1;
1296  uint32_t EN40MOSC:1;
1297  uint32_t:3;
1298  uint32_t TRIM128IRC:5;
1299  uint32_t:2;
1300  uint32_t TRIM16IRC:6;
1301  } B;
1302  } CLKSRC; /* CLOCK SOURCE REGISTER */
1303 
1304  uint32_t crp_reserved1[3];
1305 
1306  union {
1307  uint32_t R;
1308  struct {
1309  uint32_t CNTEN:1;
1310  uint32_t RTCIE:1;
1311  uint32_t FRZEN:1;
1312  uint32_t ROVREN:1;
1313  uint32_t RTCVAL:12;
1314  uint32_t APIEN:1;
1315  uint32_t APIIE:1;
1316  uint32_t CLKSEL:2;
1317  uint32_t DIV512EN:1;
1318  uint32_t DIV32EN:1;
1319  uint32_t APIVAL:10;
1320  } B;
1321  } RTCC; /* RTC CONTROL REGISTER */
1322 
1323  union {
1324  uint32_t R;
1325  struct {
1326  uint32_t:2;
1327  uint32_t RTCF:1;
1328  uint32_t:15;
1329  uint32_t APIF:1;
1330  uint32_t:2;
1331  uint32_t ROVRF:1;
1332  uint32_t:10;
1333  } B;
1334  } RTSC; /* RTC STATUS REGISTER */
1335 
1336  union {
1337  uint32_t R;
1338  struct {
1339  uint32_t RTCCNT:32;
1340  } B;
1341  } RTCCNT; /* RTC Counter Register */
1342 
1343  uint32_t crp_reserved2[9];
1344 
1345  union {
1346  uint32_t R;
1347  struct {
1348  uint32_t PWK31:2;
1349  uint32_t PWK30:2;
1350  uint32_t PWK29:2;
1351  uint32_t PWK28:2;
1352  uint32_t PWK27:2;
1353  uint32_t PWK26:2;
1354  uint32_t PWK25:2;
1355  uint32_t PWK24:2;
1356  uint32_t PWK23:2;
1357  uint32_t PWK22:2;
1358  uint32_t PWK21:2;
1359  uint32_t PWK20:2;
1360  uint32_t PWK19:2;
1361  uint32_t PWK18:2;
1362  uint32_t PWK17:2;
1363  uint32_t PWK16:2;
1364  } B;
1365  } PWKENH; /* PIN WAKEUP ENABLE HIGH REGISTER */
1366 
1367  union {
1368  uint32_t R;
1369  struct {
1370  uint32_t PWK15:2;
1371  uint32_t PWK14:2;
1372  uint32_t PWK13:2;
1373  uint32_t PWK12:2;
1374  uint32_t PWK11:2;
1375  uint32_t PWK10:2;
1376  uint32_t PWK9:2;
1377  uint32_t PWK8:2;
1378  uint32_t PWK7:2;
1379  uint32_t PWK6:2;
1380  uint32_t PWK5:2;
1381  uint32_t PWK4:2;
1382  uint32_t PWK3:2;
1383  uint32_t PWK2:2;
1384  uint32_t PWK1:2;
1385  uint32_t PWK0:2;
1386  } B;
1387  } PWKENL; /* PIN WAKEUP ENABLE LOW REGISTER */
1388 
1389  union {
1390  uint32_t R;
1391  struct {
1392  uint32_t PWKSRCIE31:1;
1393  uint32_t PWKSRCIE30:1;
1394  uint32_t PWKSRCIE29:1;
1395  uint32_t PWKSRCIE28:1;
1396  uint32_t PWKSRCIE27:1;
1397  uint32_t PWKSRCIE26:1;
1398  uint32_t PWKSRCIE25:1;
1399  uint32_t PWKSRCIE24:1;
1400  uint32_t PWKSRCIE23:1;
1401  uint32_t PWKSRCIE22:1;
1402  uint32_t PWKSRCIE21:1;
1403  uint32_t PWKSRCIE20:1;
1404  uint32_t PWKSRCIE19:1;
1405  uint32_t PWKSRCIE18:1;
1406  uint32_t PWKSRCIE17:1;
1407  uint32_t PWKSRCIE16:1;
1408  uint32_t PWKSRCIE15:1;
1409  uint32_t PWKSRCIE14:1;
1410  uint32_t PWKSRCIE13:1;
1411  uint32_t PWKSRCIE12:1;
1412  uint32_t PWKSRCIE11:1;
1413  uint32_t PWKSRCIE10:1;
1414  uint32_t PWKSRCIE9:1;
1415  uint32_t PWKSRCIE8:1;
1416  uint32_t PWKSRCIE7:1;
1417  uint32_t PWKSRCIE6:1;
1418  uint32_t PWKSRCIE5:1;
1419  uint32_t PWKSRCIE4:1;
1420  uint32_t PWKSRCIE3:1;
1421  uint32_t PWKSRCIE2:1;
1422  uint32_t PWKSRCIE1:1;
1423  uint32_t PWKSRCIE0:1;
1424  } B;
1425  } PWKSRCIE; /* PIN WAKEUP SOURCE INTERRUPT ENABLE REGISTER */
1426 
1427  union {
1428  uint32_t R;
1429  struct {
1430  uint32_t PWKSRCIE31:1;
1431  uint32_t PWKSRCIE30:1;
1432  uint32_t PWKSRCIE29:1;
1433  uint32_t PWKSRCIE28:1;
1434  uint32_t PWKSRCIE27:1;
1435  uint32_t PWKSRCIE26:1;
1436  uint32_t PWKSRCIE25:1;
1437  uint32_t PWKSRCIE24:1;
1438  uint32_t PWKSRCIE23:1;
1439  uint32_t PWKSRCIE22:1;
1440  uint32_t PWKSRCIE21:1;
1441  uint32_t PWKSRCIE20:1;
1442  uint32_t PWKSRCIE19:1;
1443  uint32_t PWKSRCIE18:1;
1444  uint32_t PWKSRCIE17:1;
1445  uint32_t PWKSRCIE16:1;
1446  uint32_t PWKSRCIE15:1;
1447  uint32_t PWKSRCIE14:1;
1448  uint32_t PWKSRCIE13:1;
1449  uint32_t PWKSRCIE12:1;
1450  uint32_t PWKSRCIE11:1;
1451  uint32_t PWKSRCIE10:1;
1452  uint32_t PWKSRCIE9:1;
1453  uint32_t PWKSRCIE8:1;
1454  uint32_t PWKSRCIE7:1;
1455  uint32_t PWKSRCIE6:1;
1456  uint32_t PWKSRCIE5:1;
1457  uint32_t PWKSRCIE4:1;
1458  uint32_t PWKSRCIE3:1;
1459  uint32_t PWKSRCIE2:1;
1460  uint32_t PWKSRCIE1:1;
1461  uint32_t PWKSRCIE0:1;
1462  } B;
1463  } PWKSRCF; /* PIN WAKEUP SOURCE FLAG REGISTER */
1464 
1465  union {
1466  uint32_t R;
1467  struct {
1468  uint32_t Z6VECB:20;
1469  uint32_t:10;
1470  uint32_t Z6RST:1;
1471  uint32_t VLE:1;
1472  } B;
1473  } Z6VEC; /* Z6 RESET VECTOR REGISTER */
1474 
1475  union {
1476  uint32_t R;
1477  struct {
1478  uint32_t Z0VECB:30;
1479  uint32_t Z0RST:1;
1480  uint32_t:1;
1481  } B;
1482  } Z0VEC; /* Z0 RESET VECTOR REGISTER */
1483 
1484  union {
1485  uint32_t R;
1486  struct {
1487  uint32_t RECPTR:30;
1488  uint32_t FASTREC:1;
1489  uint32_t:1;
1490  } B;
1491  } RECPTR; /* RESET RECOVERY POINTER REGISTER */
1492 
1493  uint32_t crp_reserved3;
1494 
1495  union {
1496  uint32_t R;
1497  struct {
1498  uint32_t SLEEPF:1;
1499  uint32_t:12;
1500  uint32_t RTCOVRWKF:1;
1501  uint32_t RTCWKF:1;
1502  uint32_t APIWKF:1;
1503  uint32_t SLEEP:1;
1504  uint32_t:4;
1505  uint32_t RAMSEL:3;
1506  uint32_t:4;
1507  uint32_t WKCLKSEL:1;
1508  uint32_t RTCOVRWKEN:1;
1509  uint32_t RTCWKEN:1;
1510  uint32_t APIWKEN:1;
1511  } B;
1512  } PSCR; /* POWER STATUS AND CONTROL REGISTER */
1513 
1514  uint32_t crp_reserved4[3];
1515 
1516  union {
1517  uint32_t R;
1518  struct {
1519  uint32_t LVI5LOCK:1;
1520  uint32_t LVI5RE:1;
1521  uint32_t:7;
1522  uint32_t LVI5HIE:1;
1523  uint32_t LVI5NIE:1;
1524  uint32_t LVI5IE:1;
1525  uint32_t:2;
1526  uint32_t FRIE:1;
1527  uint32_t FDIS:1;
1528  uint32_t:9;
1529  uint32_t LVI5HIF:1;
1530  uint32_t LVI5NF:1;
1531  uint32_t LVI5F:1;
1532  uint32_t:2;
1533  uint32_t FRF:1;
1534  uint32_t FRDY:1;
1535  } B;
1536  } SOCSC; /* LVI Status and Control Register */
1537 
1538  }; /* end of CRP_tag */
1539 /*************************************************************************/
1540 /* MODULE : CTU */
1541 /*************************************************************************/
1542  struct CTU_tag {
1543 
1544  union {
1545  uint32_t R;
1546  struct {
1547  uint32_t:24;
1548  uint32_t TRGIEN:1;
1549  uint32_t TRGI:1;
1550  uint32_t:2;
1551  uint32_t PRESC_CONF:4;
1552  } B;
1553  } CSR; /* Control Status Register */
1554 
1555  union {
1556  uint32_t R;
1557  struct {
1558  uint32_t:23;
1559  uint32_t SV:9;
1560  } B;
1561  } SVR[7]; /* Start Value Register */
1562 
1563  union {
1564  uint32_t R;
1565  struct {
1566  uint32_t:23;
1567  uint32_t CV:9;
1568  } B;
1569  } CVR[4]; /* Current Value Register */
1570 
1571  union {
1572  uint32_t R;
1573  struct {
1574  uint32_t:16;
1575  uint32_t TM:1;
1576  uint32_t:1;
1577  uint32_t COUNT_GROUP:2;
1578  uint32_t:1;
1579  uint32_t DELAY_INDEX:3;
1580  uint32_t CLR_FG:1;
1581  uint32_t:1;
1582  uint32_t CHANNEL_VALUE:6;
1583  } B;
1584  } EVTCFGR[33]; /* Event Configuration Register */
1585 
1586  }; /* end of CTU_tag */
1587 /*************************************************************************/
1588 /* MODULE : DMAMUX */
1589 /*************************************************************************/
1590  struct DMAMUX_tag {
1591  union {
1592  uint8_t R;
1593  struct {
1594  uint8_t ENBL:1;
1595  uint8_t TRIG:1;
1596  uint8_t SOURCE:6;
1597  } B;
1598  } CHCONFIG[32]; /* DMA Channel Configuration Register */
1599 
1600  }; /* end of DMAMUX_tag */
1601 /*************************************************************************/
1602 /* MODULE : DSPI */
1603 /*************************************************************************/
1604  struct DSPI_tag {
1605  union DSPI_MCR_tag {
1606  uint32_t R;
1607  struct {
1608  uint32_t MSTR:1;
1609  uint32_t CONT_SCKE:1;
1610  uint32_t DCONF:2;
1611  uint32_t FRZ:1;
1612  uint32_t MTFE:1;
1613  uint32_t PCSSE:1;
1614  uint32_t ROOE:1;
1615  uint32_t:2;
1616  uint32_t PCSIS5:1;
1617  uint32_t PCSIS4:1;
1618  uint32_t PCSIS3:1;
1619  uint32_t PCSIS2:1;
1620  uint32_t PCSIS1:1;
1621  uint32_t PCSIS0:1;
1622  uint32_t:1;
1623  uint32_t MDIS:1;
1624  uint32_t DIS_TXF:1;
1625  uint32_t DIS_RXF:1;
1626  uint32_t CLR_TXF:1;
1627  uint32_t CLR_RXF:1;
1628  uint32_t SMPL_PT:2;
1629  uint32_t:7;
1630  uint32_t HALT:1;
1631  } B;
1632  } MCR; /* Module Configuration Register */
1633 
1634  uint32_t dspi_reserved1;
1635 
1636  union {
1637  uint32_t R;
1638  struct {
1639  uint32_t SPI_TCNT:16;
1640  uint32_t:16;
1641  } B;
1642  } TCR;
1643 
1644  union DSPI_CTAR_tag {
1645  uint32_t R;
1646  struct {
1647  uint32_t DBR:1;
1648  uint32_t FMSZ:4;
1649  uint32_t CPOL:1;
1650  uint32_t CPHA:1;
1651  uint32_t LSBFE:1;
1652  uint32_t PCSSCK:2;
1653  uint32_t PASC:2;
1654  uint32_t PDT:2;
1655  uint32_t PBR:2;
1656  uint32_t CSSCK:4;
1657  uint32_t ASC:4;
1658  uint32_t DT:4;
1659  uint32_t BR:4;
1660  } B;
1661  } CTAR[8]; /* Clock and Transfer Attributes Registers */
1662 
1663  union DSPI_SR_tag {
1664  uint32_t R;
1665  struct {
1666  uint32_t TCF:1;
1667  uint32_t TXRXS:1;
1668  uint32_t:1;
1669  uint32_t EOQF:1;
1670  uint32_t TFUF:1;
1671  uint32_t:1;
1672  uint32_t TFFF:1;
1673  uint32_t:5;
1674  uint32_t RFOF:1;
1675  uint32_t:1;
1676  uint32_t RFDF:1;
1677  uint32_t:1;
1678  uint32_t TXCTR:4;
1679  uint32_t TXNXTPTR:4;
1680  uint32_t RXCTR:4;
1681  uint32_t POPNXTPTR:4;
1682  } B;
1683  } SR; /* Status Register */
1684 
1685  union DSPI_RSER_tag {
1686  uint32_t R;
1687  struct {
1688  uint32_t TCFRE:1;
1689  uint32_t:2;
1690  uint32_t EOQFRE:1;
1691  uint32_t TFUFRE:1;
1692  uint32_t:1;
1693  uint32_t TFFFRE:1;
1694  uint32_t TFFFDIRS:1;
1695  uint32_t:4;
1696  uint32_t RFOFRE:1;
1697  uint32_t:1;
1698  uint32_t RFDFRE:1;
1699  uint32_t RFDFDIRS:1;
1700  uint32_t:16;
1701  } B;
1702  } RSER; /* DMA/Interrupt Request Select and Enable Register */
1703 
1704  union DSPI_PUSHR_tag {
1705  uint32_t R;
1706  struct {
1707  uint32_t CONT:1;
1708  uint32_t CTAS:3;
1709  uint32_t EOQ:1;
1710  uint32_t CTCNT:1;
1711  uint32_t:4;
1712  uint32_t PCS5:1;
1713  uint32_t PCS4:1;
1714  uint32_t PCS3:1;
1715  uint32_t PCS2:1;
1716  uint32_t PCS1:1;
1717  uint32_t PCS0:1;
1718  uint32_t TXDATA:16;
1719  } B;
1720  } PUSHR; /* PUSH TX FIFO Register */
1721 
1722  union DSPI_POPR_tag {
1723  uint32_t R;
1724  struct {
1725  uint32_t:16;
1726  uint32_t RXDATA:16;
1727  } B;
1728  } POPR; /* POP RX FIFO Register */
1729 
1730  union {
1731  uint32_t R;
1732  struct {
1733  uint32_t TXCMD:16;
1734  uint32_t TXDATA:16;
1735  } B;
1736  } TXFR[4]; /* Transmit FIFO Registers */
1737 
1738  uint32_t DSPI_reserved_txf[12];
1739 
1740  union {
1741  uint32_t R;
1742  struct {
1743  uint32_t:16;
1744  uint32_t RXDATA:16;
1745  } B;
1746  } RXFR[4]; /* Transmit FIFO Registers */
1747 
1748  uint32_t DSPI_reserved_rxf[12];
1749 
1750  union {
1751  uint32_t R;
1752  struct {
1753  uint32_t:11;
1754  uint32_t TSBC:1;
1755  uint32_t TXSS:1;
1756  uint32_t:2;
1757  uint32_t CID:1;
1758  uint32_t DCONT:1;
1759  uint32_t DSICTAS:3;
1760  uint32_t:6;
1761  uint32_t DPCS5:1;
1762  uint32_t DPCS4:1;
1763  uint32_t DPCS3:1;
1764  uint32_t DPCS2:1;
1765  uint32_t DPCS1:1;
1766  uint32_t DPCS0:1;
1767  } B;
1768  } DSICR; /* DSI Configuration Register */
1769 
1770  union {
1771  uint32_t R;
1772  struct {
1773  uint32_t SER_DATA:32;
1774  } B;
1775  } SDR; /* DSI Serialization Data Register */
1776 
1777  union {
1778  uint32_t R;
1779  struct {
1780  uint32_t ASER_DATA:32;
1781  } B;
1782  } ASDR; /* DSI Alternate Serialization Data Register */
1783 
1784  union {
1785  uint32_t R;
1786  struct {
1787  uint32_t COMP_DATA:32;
1788  } B;
1789  } COMPR; /* DSI Transmit Comparison Register */
1790 
1791  union {
1792  uint32_t R;
1793  struct {
1794  uint32_t DESER_DATA:32;
1795  } B;
1796  } DDR; /* DSI deserialization Data Register */
1797 
1798  union {
1799  uint32_t R;
1800  struct {
1801  uint32_t:3;
1802  uint32_t TSBCNT:5;
1803  uint32_t:16;
1804  uint32_t DPCS1_7:1;
1805  uint32_t DPCS1_6:1;
1806  uint32_t DPCS1_5:1;
1807  uint32_t DPCS1_4:1;
1808  uint32_t DPCS1_3:1;
1809  uint32_t DPCS1_2:1;
1810  uint32_t DPCS1_1:1;
1811  uint32_t DPCS1_0:1;
1812  } B;
1813  } DSICR1; /* DSI Configuration Register 1 */
1814 
1815  }; /* end of DSPI_tag */
1816 /*************************************************************************/
1817 /* MODULE : ECSM */
1818 /*************************************************************************/
1819  struct ECSM_tag {
1820 
1821  uint32_t ecsm_reserved1[9];
1822 
1823  union {
1824  uint32_t R;
1825  struct {
1826  uint32_t FXSBE0:1;
1827  uint32_t FXSBE1:1;
1828  uint32_t FXSBE2:1;
1829  uint32_t FXSBE3:1;
1830  uint32_t:2;
1831  uint32_t FXSBE6:1;
1832  uint32_t FXSBE7:1;
1833  uint32_t RBEN:1;
1834  uint32_t WBEN:1;
1835  uint32_t ACCERR:1;
1836  uint32_t:21;
1837  } B;
1838  } FBOMCR; /* FEC Burst Optimisation Master Control Register */
1839 
1840  uint8_t ecsm_reserved2[27];
1841 
1842  union {
1843  uint8_t R;
1844  struct {
1845  uint8_t:2;
1846  uint8_t EPR1BR:1;
1847  uint8_t EPF1BR:1;
1848  uint8_t:2;
1849  uint8_t EPRNCR:1;
1850  uint8_t EPFNCR:1;
1851  } B;
1852  } ECR; /* ECC Configuration Register */
1853 
1854  uint8_t ecsm_reserved3[3];
1855 
1856  union {
1857  uint8_t R;
1858  struct {
1859  uint8_t:2;
1860  uint8_t PR1BC:1;
1861  uint8_t PF1BC:1;
1862  uint8_t:2;
1863  uint8_t PRNCE:1;
1864  uint8_t PFNCE:1;
1865  } B;
1866  } ESR; /* ECC Status Register */
1867 
1868  uint16_t ecsm_reserved4;
1869 
1870  union {
1871  uint16_t R;
1872  struct {
1873  uint16_t:2;
1874  uint16_t FRC1BI:1;
1875  uint16_t FR11BI:1;
1876  uint16_t:2;
1877  uint16_t FRCNCI:1;
1878  uint16_t FR1NCI:1;
1879  uint16_t PREI_SEL:1;
1880  uint16_t ERRBIT:7;
1881  } B;
1882  } EEGR; /* ECC Error Generation Register */
1883 
1884  uint32_t ecsm_reserved5;
1885 
1886  union {
1887  uint32_t R;
1888  struct {
1889  uint32_t PFEAR:32;
1890  } B;
1891  } PFEAR; /* Platform Flash ECC Address Register */
1892 
1893  uint16_t ecsm_reserved6;
1894 
1895  union {
1896  uint8_t R;
1897  struct {
1898  uint8_t:4;
1899  uint8_t PFEMR:4;
1900  } B;
1901  } PFEMR; /* Platform Flash ECC Address Register */
1902 
1903  union {
1904  uint8_t R;
1905  struct {
1906  uint8_t WRITE:1;
1907  uint8_t SIZE:3;
1908  uint8_t PROTECTION:4;
1909  } B;
1910  } PFEAT; /* Flash ECC Attributes Register */
1911 
1912  union {
1913  uint32_t R;
1914  struct {
1915  uint32_t PFEDRH:32;
1916  } B;
1917  } PFEDRH; /* Flash ECC Data High Register */
1918 
1919  union {
1920  uint32_t R;
1921  struct {
1922  uint32_t PFEDRL:32;
1923  } B;
1924  } PFEDRL; /* Flash ECC Data Low Register */
1925 
1926  union {
1927  uint32_t R;
1928  struct {
1929  uint32_t PREAR:32;
1930  } B;
1931  } PREAR; /* Platform RAM ECC Address Register */
1932 
1933  uint16_t ecsm_reserved8;
1934 
1935  union {
1936  uint8_t R;
1937  struct {
1938  uint8_t:4;
1939  uint8_t PREMR:4;
1940  } B;
1941  } PREMR; /* RAM ECC Attributes Register */
1942 
1943  union {
1944  uint8_t R;
1945  struct {
1946  uint8_t WRITE:1;
1947  uint8_t SIZE:3;
1948  uint8_t PROTECTION:4;
1949  } B;
1950  } PREAT; /* Platform RAM ECC Attributes Register */
1951 
1952  union {
1953  uint32_t R;
1954  struct {
1955  uint32_t PREDR:32;
1956  } B;
1957  } PREDRH; /* Platform RAM ECC Data Low Register High */
1958 
1959  union {
1960  uint32_t R;
1961  struct {
1962  uint32_t PREDR:32;
1963  } B;
1964  } PREDRL; /* Platform RAM ECC Data Low Register Low */
1965 
1966  }; /* end of ECSM_tag */
1967 /*************************************************************************/
1968 /* MODULE : EMIOS */
1969 /*************************************************************************/
1970  struct EMIOS_tag {
1971  union EMIOS_MCR_tag {
1972  uint32_t R;
1973  struct {
1974  uint32_t:1;
1975  uint32_t MDIS:1;
1976  uint32_t FRZ:1;
1977  uint32_t GTBE:1;
1978  uint32_t:1;
1979  uint32_t GPREN:1;
1980  uint32_t:10;
1981  uint32_t GPRE:8;
1982  uint32_t:8;
1983  } B;
1984  } MCR; /* Module Configuration Register */
1985 
1986  union {
1987  uint32_t R;
1988  struct {
1989  uint32_t F31:1;
1990  uint32_t F30:1;
1991  uint32_t F29:1;
1992  uint32_t F28:1;
1993  uint32_t F27:1;
1994  uint32_t F26:1;
1995  uint32_t F25:1;
1996  uint32_t F24:1;
1997  uint32_t F23:1;
1998  uint32_t F22:1;
1999  uint32_t F21:1;
2000  uint32_t F20:1;
2001  uint32_t F19:1;
2002  uint32_t F18:1;
2003  uint32_t F17:1;
2004  uint32_t F16:1;
2005  uint32_t F15:1;
2006  uint32_t F14:1;
2007  uint32_t F13:1;
2008  uint32_t F12:1;
2009  uint32_t F11:1;
2010  uint32_t F10:1;
2011  uint32_t F9:1;
2012  uint32_t F8:1;
2013  uint32_t F7:1;
2014  uint32_t F6:1;
2015  uint32_t F5:1;
2016  uint32_t F4:1;
2017  uint32_t F3:1;
2018  uint32_t F2:1;
2019  uint32_t F1:1;
2020  uint32_t F0:1;
2021  } B;
2022  } GFR; /* Global FLAG Register */
2023 
2024  union {
2025  uint32_t R;
2026  struct {
2027  uint32_t OU31:1;
2028  uint32_t OU30:1;
2029  uint32_t OU29:1;
2030  uint32_t OU28:1;
2031  uint32_t OU27:1;
2032  uint32_t OU26:1;
2033  uint32_t OU25:1;
2034  uint32_t OU24:1;
2035  uint32_t OU23:1;
2036  uint32_t OU22:1;
2037  uint32_t OU21:1;
2038  uint32_t OU20:1;
2039  uint32_t OU19:1;
2040  uint32_t OU18:1;
2041  uint32_t OU17:1;
2042  uint32_t OU16:1;
2043  uint32_t OU15:1;
2044  uint32_t OU14:1;
2045  uint32_t OU13:1;
2046  uint32_t OU12:1;
2047  uint32_t OU11:1;
2048  uint32_t OU10:1;
2049  uint32_t OU9:1;
2050  uint32_t OU8:1;
2051  uint32_t OU7:1;
2052  uint32_t OU6:1;
2053  uint32_t OU5:1;
2054  uint32_t OU4:1;
2055  uint32_t OU3:1;
2056  uint32_t OU2:1;
2057  uint32_t OU1:1;
2058  uint32_t OU0:1;
2059  } B;
2060  } OUDR; /* Output Update Disable Register */
2061 
2062  union {
2063  uint32_t R;
2064  struct {
2065  uint32_t UC31:1;
2066  uint32_t UC30:1;
2067  uint32_t UC29:1;
2068  uint32_t UC28:1;
2069  uint32_t UC27:1;
2070  uint32_t UC26:1;
2071  uint32_t UC25:1;
2072  uint32_t UC24:1;
2073  uint32_t UC23:1;
2074  uint32_t UC22:1;
2075  uint32_t UC21:1;
2076  uint32_t UC20:1;
2077  uint32_t UC19:1;
2078  uint32_t UC18:1;
2079  uint32_t UC17:1;
2080  uint32_t UC16:1;
2081  uint32_t UC15:1;
2082  uint32_t UC14:1;
2083  uint32_t UC13:1;
2084  uint32_t UC12:1;
2085  uint32_t UC11:1;
2086  uint32_t UC10:1;
2087  uint32_t UC9:1;
2088  uint32_t UC8:1;
2089  uint32_t UC7:1;
2090  uint32_t UC6:1;
2091  uint32_t UC5:1;
2092  uint32_t UC4:1;
2093  uint32_t UC3:1;
2094  uint32_t UC2:1;
2095  uint32_t UC1:1;
2096  uint32_t UC0:1;
2097  } B;
2098  } UCDIS; /* Disable Channel Register */
2099 
2100  uint32_t emios_reserved1[4];
2101 
2102  struct EMIOS_CH_tag {
2103  union {
2104  uint32_t R;
2105  struct {
2106  uint32_t:16;
2107  uint32_t A:16; /* Channel A Data Register */
2108  } B;
2109  } CADR;
2110 
2111  union {
2112  uint32_t R;
2113  struct {
2114  uint32_t:16;
2115  uint32_t B:16; /* Channel B Data Register */
2116  } B;
2117  } CBDR;
2118 
2119  union {
2120  uint32_t R; /* Channel Counter Register */
2121  struct {
2122  uint32_t:16;
2123  uint32_t C:16; /* Channel C Data Register */
2124  } B;
2125  } CCNTR;
2126 
2127  union EMIOS_CCR_tag {
2128  uint32_t R;
2129  struct {
2130  uint32_t FREN:1;
2131  uint32_t ODIS:1;
2132  uint32_t ODISSL:2;
2133  uint32_t UCPRE:2;
2134  uint32_t UCPREN:1;
2135  uint32_t DMA:1;
2136  uint32_t:1;
2137  uint32_t IF:4;
2138  uint32_t FCK:1;
2139  uint32_t FEN:1;
2140  uint32_t:3;
2141  uint32_t FORCMA:1;
2142  uint32_t FORCMB:1;
2143  uint32_t:1;
2144  uint32_t BSL:2;
2145  uint32_t EDSEL:1;
2146  uint32_t EDPOL:1;
2147  uint32_t MODE:7;
2148  } B;
2149  } CCR; /* Channel Control Register */
2150 
2151  union EMIOS_CSR_tag {
2152  uint32_t R;
2153  struct {
2154  uint32_t OVR:1;
2155  uint32_t:15;
2156  uint32_t OVFL:1;
2157  uint32_t:12;
2158  uint32_t UCIN:1;
2159  uint32_t UCOUT:1;
2160  uint32_t FLAG:1;
2161  } B;
2162  } CSR; /* Channel Status Register */
2163 
2164  union {
2165  uint32_t R; /* Alternate Channel A Data Register */
2166  } ALTA;
2167 
2168  uint32_t emios_channel_reserved[2];
2169 
2170  } CH[32];
2171 
2172  }; /* end of EMIOS_tag */
2173 /*************************************************************************/
2174 /* MODULE : eSCI */
2175 /*************************************************************************/
2176  struct ESCI_tag {
2177  union ESCI_CR1_tag {
2178  uint32_t R;
2179  struct {
2180  uint32_t:3;
2181  uint32_t SBR:13;
2182  uint32_t LOOPS:1;
2183  uint32_t:1;
2184  uint32_t RSRC:1;
2185  uint32_t M:1;
2186  uint32_t WAKE:1;
2187  uint32_t ILT:1;
2188  uint32_t PE:1;
2189  uint32_t PT:1;
2190  uint32_t TIE:1;
2191  uint32_t TCIE:1;
2192  uint32_t RIE:1;
2193  uint32_t ILIE:1;
2194  uint32_t TE:1;
2195  uint32_t RE:1;
2196  uint32_t RWU:1;
2197  uint32_t SBK:1;
2198  } B;
2199  } CR1; /* Control Register 1 */
2200 
2201  union ESCI_CR2_tag {
2202  uint16_t R;
2203  struct {
2204  uint16_t MDIS:1;
2205  uint16_t FBR:1;
2206  uint16_t BSTP:1;
2207  uint16_t IEBERR:1;
2208  uint16_t RXDMA:1;
2209  uint16_t TXDMA:1;
2210  uint16_t BRK13:1;
2211  uint16_t TXDIR:1;
2212  uint16_t BESM13:1;
2213  uint16_t SBSTP:1;
2214  uint16_t RXPOL:1;
2215  uint16_t PMSK:1;
2216  uint16_t ORIE:1;
2217  uint16_t NFIE:1;
2218  uint16_t FEIE:1;
2219  uint16_t PFIE:1;
2220  } B;
2221  } CR2; /* Control Register 2 */
2222 
2223  union ESCI_DR_tag {
2224  uint16_t R;
2225  struct {
2226  uint16_t RN:1;
2227  uint16_t TN:1;
2228  uint16_t ERR:1;
2229  uint16_t:1;
2230  uint16_t RD_11:4;
2231  uint16_t D:8;
2232  } B;
2233  } DR; /* Data Register */
2234 
2235  union ESCI_SR_tag {
2236  uint32_t R;
2237  struct {
2238  uint32_t TDRE:1;
2239  uint32_t TC:1;
2240  uint32_t RDRF:1;
2241  uint32_t IDLE:1;
2242  uint32_t OR:1;
2243  uint32_t NF:1;
2244  uint32_t FE:1;
2245  uint32_t PF:1;
2246  uint32_t:3;
2247  uint32_t BERR:1;
2248  uint32_t:2;
2249  uint32_t TACT:1;
2250  uint32_t RACT:1;
2251  uint32_t RXRDY:1;
2252  uint32_t TXRDY:1;
2253  uint32_t LWAKE:1;
2254  uint32_t STO:1;
2255  uint32_t PBERR:1;
2256  uint32_t CERR:1;
2257  uint32_t CKERR:1;
2258  uint32_t FRC:1;
2259  uint32_t:6;
2260  uint32_t UREQ:1;
2261  uint32_t OVFL:1;
2262  } B;
2263  } SR; /* Status Register */
2264 
2265  union {
2266  uint32_t R;
2267  struct {
2268  uint32_t LRES:1;
2269  uint32_t WU:1;
2270  uint32_t WUD0:1;
2271  uint32_t WUD1:1;
2272  uint32_t:2;
2273  uint32_t PRTY:1;
2274  uint32_t LIN:1;
2275  uint32_t RXIE:1;
2276  uint32_t TXIE:1;
2277  uint32_t WUIE:1;
2278  uint32_t STIE:1;
2279  uint32_t PBIE:1;
2280  uint32_t CIE:1;
2281  uint32_t CKIE:1;
2282  uint32_t FCIE:1;
2283  uint32_t:6;
2284  uint32_t UQIE:1;
2285  uint32_t OFIE:1;
2286  uint32_t:8;
2287  } B;
2288  } LCR; /* LIN Control Register */
2289 
2290  union {
2291  uint8_t R;
2292  } LTR; /* LIN Transmit Register */
2293 
2294  uint8_t eSCI_reserved1[3];
2295 
2296  union {
2297  uint8_t R;
2298  } LRR; /* LIN Recieve Register */
2299 
2300  uint8_t eSCI_reserved2[3];
2301 
2302  union {
2303  uint16_t R;
2304  } LPR; /* LIN CRC Polynom Register */
2305 
2306  union {
2307  uint8_t R;
2308  struct {
2309  uint8_t:3;
2310  uint8_t SYNM:1;
2311  uint8_t EROE:1;
2312  uint8_t ERFE:1;
2313  uint8_t ERPE:1;
2314  uint8_t M2:1;
2315  } B;
2316  } CR3; /* Control Register 3 */
2317 
2318  uint8_t eSCI_reserved3[5];
2319  }; /* end of ESCI_tag */
2320 /*************************************************************************/
2321 /* MODULE : FEC */
2322 /*************************************************************************/
2323  struct FEC_tag {
2324 
2325  uint32_t fec_reserved_start;
2326 
2327  union {
2328  uint32_t R;
2329  struct {
2330  uint32_t HBERR:1;
2331  uint32_t BABR:1;
2332  uint32_t BABT:1;
2333  uint32_t GRA:1;
2334  uint32_t TXF:1;
2335  uint32_t TXB:1;
2336  uint32_t RXF:1;
2337  uint32_t RXB:1;
2338  uint32_t MII:1;
2339  uint32_t EBERR:1;
2340  uint32_t LC:1;
2341  uint32_t RL:1;
2342  uint32_t UN:1;
2343  uint32_t:19;
2344  } B;
2345  } EIR; /* Interrupt Event Register */
2346 
2347  union {
2348  uint32_t R;
2349  struct {
2350  uint32_t HBERR:1;
2351  uint32_t BABR:1;
2352  uint32_t BABT:1;
2353  uint32_t GRA:1;
2354  uint32_t TXF:1;
2355  uint32_t TXB:1;
2356  uint32_t RXF:1;
2357  uint32_t RXB:1;
2358  uint32_t MII:1;
2359  uint32_t EBERR:1;
2360  uint32_t LC:1;
2361  uint32_t RL:1;
2362  uint32_t UN:1;
2363  uint32_t:19;
2364  } B;
2365  } EIMR; /* Interrupt Mask Register */
2366 
2367  uint32_t fec_reserved_eimr;
2368 
2369  union {
2370  uint32_t R;
2371  struct {
2372  uint32_t:7;
2373  uint32_t R_DES_ACTIVE:1;
2374  uint32_t:24;
2375  } B;
2376  } RDAR; /* Receive Descriptor Active Register */
2377 
2378  union {
2379  uint32_t R;
2380  struct {
2381  uint32_t:7;
2382  uint32_t X_DES_ACTIVE:1;
2383  uint32_t:24;
2384  } B;
2385  } TDAR; /* Transmit Descriptor Active Register */
2386 
2387  uint32_t fec_reserved_tdar[3];
2388 
2389  union {
2390  uint32_t R;
2391  struct {
2392  uint32_t:30;
2393  uint32_t ETHER_EN:1;
2394  uint32_t RESET:1;
2395  } B;
2396  } ECR; /* Ethernet Control Register */
2397 
2398  uint32_t fec_reserved_ecr[6];
2399 
2400  union {
2401  uint32_t R;
2402  struct {
2403  uint32_t ST:2;
2404  uint32_t OP:2;
2405  uint32_t PA:5;
2406  uint32_t RA:5;
2407  uint32_t TA:2;
2408  uint32_t DATA:16;
2409  } B;
2410  } MMFR; /* MII Data Register */
2411 
2412  union {
2413  uint32_t R;
2414  struct {
2415  uint32_t:24;
2416  uint32_t DIS_PREAMBLE:1;
2417  uint32_t MII_SPEED:6;
2418  uint32_t:1;
2419  } B;
2420  } MSCR; /* MII Speed Control Register */
2421 
2422  uint32_t fec_reserved_mscr[7];
2423 
2424  union {
2425  uint32_t R;
2426  struct {
2427  uint32_t MIB_DISABLE:1;
2428  uint32_t MIB_IDLE:1;
2429  uint32_t:30;
2430  } B;
2431  } MIBC; /* MIB Control Register */
2432 
2433  uint32_t fec_reserved_mibc[7];
2434 
2435  union {
2436  uint32_t R;
2437  struct {
2438  uint32_t:5;
2439  uint32_t MAX_FL:11;
2440  uint32_t:10;
2441  uint32_t FCE:1;
2442  uint32_t BC_REJ:1;
2443  uint32_t PROM:1;
2444  uint32_t MII_MODE:1;
2445  uint32_t DRT:1;
2446  uint32_t LOOP:1;
2447  } B;
2448  } RCR; /* Receive Control Register */
2449 
2450  uint32_t fec_reserved_rcr[15];
2451 
2452  union {
2453  uint32_t R;
2454  struct {
2455  uint32_t:27;
2456  uint32_t RFC_PAUSE:1;
2457  uint32_t TFC_PAUSE:1;
2458  uint32_t FDEN:1;
2459  uint32_t HBC:1;
2460  uint32_t GTS:1;
2461  } B;
2462  } TCR; /* Transmit Control Register */
2463 
2464  uint32_t fec_reserved_tcr[7];
2465 
2466  union {
2467  uint32_t R;
2468  struct {
2469  uint32_t PADDR1:32;
2470  } B;
2471  } PALR; /* Physical Address Low Register */
2472 
2473  union {
2474  uint32_t R;
2475  struct {
2476  uint32_t PADDR2:16;
2477  uint32_t TYPE:16;
2478  } B;
2479  } PAUR; /* Physical Address High + Type Register */
2480 
2481  union {
2482  uint32_t R;
2483  struct {
2484  uint32_t OPCODE:16;
2485  uint32_t PAUSE_DUR:16;
2486  } B;
2487  } OPD; /* Opcode/Pause Duration Register */
2488 
2489  uint32_t fec_reserved_opd[10];
2490 
2491  union {
2492  uint32_t R;
2493  struct {
2494  uint32_t IADDR1:32;
2495  } B;
2496  } IAUR; /* Descriptor Individual Upper Address Register */
2497 
2498  union {
2499  uint32_t R;
2500  struct {
2501  uint32_t IADDR2:32;
2502  } B;
2503  } IALR; /* Descriptor Individual Lower Address Register */
2504 
2505  union {
2506  uint32_t R;
2507  struct {
2508  uint32_t GADDR1:32;
2509  } B;
2510  } GAUR; /* Descriptor Group Upper Address Register */
2511 
2512  union {
2513  uint32_t R;
2514  struct {
2515  uint32_t GADDR2:32;
2516  } B;
2517  } GALR; /* Descriptor Group Lower Address Register */
2518 
2519  uint32_t fec_reserved_galr[7];
2520 
2521  union {
2522  uint32_t R;
2523  struct {
2524  uint32_t:30;
2525  uint32_t X_WMRK:2;
2526  } B;
2527  } TFWR; /* FIFO Transmit FIFO Watermark Register */
2528 
2529  uint32_t fec_reserved_tfwr;
2530 
2531  union {
2532  uint32_t R;
2533  struct {
2534  uint32_t:22;
2535  uint32_t R_BOUND:8;
2536  uint32_t:2;
2537  } B;
2538  } FRBR; /* FIFO Receive Bound Register */
2539 
2540  union {
2541  uint32_t R;
2542  struct {
2543  uint32_t:22;
2544  uint32_t R_FSTART:8;
2545  uint32_t:2;
2546  } B;
2547  } FRSR; /* FIFO Receive Start Register */
2548 
2549  uint32_t fec_reserved_frsr[11];
2550 
2551  union {
2552  uint32_t R;
2553  struct {
2554  uint32_t R_DES_START:30;
2555  uint32_t:2;
2556  } B;
2557  } ERDSR; /* Receive Descriptor Ring Start Register */
2558 
2559  union {
2560  uint32_t R;
2561  struct {
2562  uint32_t X_DES_START:30;
2563  uint32_t:2;
2564  } B;
2565  } ETDSR; /* Transmit Descriptor Ring Start Register */
2566 
2567  union {
2568  uint32_t R;
2569  struct {
2570  uint32_t:21;
2571  uint32_t R_BUF_SIZE:7;
2572  uint32_t:4;
2573  } B;
2574  } EMRBR; /* Receive Buffer Size Register */
2575 
2576  uint32_t fec_reserved_emrbr[29];
2577 
2578  union {
2579  uint32_t R;
2580  } RMON_T_DROP; /* Count of frames not counted correctly */
2581 
2582  union {
2583  uint32_t R;
2584  } RMON_T_PACKETS; /* RMON Tx packet count */
2585 
2586  union {
2587  uint32_t R;
2588  } RMON_T_BC_PKT; /* RMON Tx Broadcast Packets */
2589 
2590  union {
2591  uint32_t R;
2592  } RMON_T_MC_PKT; /* RMON Tx Multicast Packets */
2593 
2594  union {
2595  uint32_t R;
2596  } RMON_T_CRC_ALIGN; /* RMON Tx Packets w CRC/Align error */
2597 
2598  union {
2599  uint32_t R;
2600  } RMON_T_UNDERSIZE; /* RMON Tx Packets < 64 bytes, good crc */
2601 
2602  union {
2603  uint32_t R;
2604  } RMON_T_OVERSIZE; /* RMON Tx Packets > MAX_FL bytes, good crc */
2605 
2606  union {
2607  uint32_t R;
2608  } RMON_T_FRAG; /* RMON Tx Packets < 64 bytes, bad crc */
2609 
2610  union {
2611  uint32_t R;
2612  } RMON_T_JAB; /* RMON Tx Packets > MAX_FL bytes, bad crc */
2613 
2614  union {
2615  uint32_t R;
2616  } RMON_T_COL; /* RMON Tx collision count */
2617 
2618  union {
2619  uint32_t R;
2620  } RMON_T_P64; /* RMON Tx 64 byte packets */
2621 
2622  union {
2623  uint32_t R;
2624  } RMON_T_P65TO127; /* RMON Tx 65 to 127 byte packets */
2625 
2626  union {
2627  uint32_t R;
2628  } RMON_T_P128TO255; /* RMON Tx 128 to 255 byte packets */
2629 
2630  union {
2631  uint32_t R;
2632  } RMON_T_P256TO511; /* RMON Tx 256 to 511 byte packets */
2633 
2634  union {
2635  uint32_t R;
2636  } RMON_T_P512TO1023; /* RMON Tx 512 to 1023 byte packets */
2637 
2638  union {
2639  uint32_t R;
2640  } RMON_T_P1024TO2047; /* RMON Tx 1024 to 2047 byte packets */
2641 
2642  union {
2643  uint32_t R;
2644  } RMON_T_P_GTE2048; /* RMON Tx packets w > 2048 bytes */
2645 
2646  union {
2647  uint32_t R;
2648  } RMON_T_OCTETS; /* RMON Tx Octets */
2649 
2650  union {
2651  uint32_t R;
2652  } IEEE_T_DROP; /* Count of frames not counted correctly */
2653 
2654  union {
2655  uint32_t R;
2656  } IEEE_T_FRAME_OK; /* Frames Transmitted OK */
2657 
2658  union {
2659  uint32_t R;
2660  } IEEE_T_1COL; /* Frames Transmitted with Single Collision */
2661 
2662  union {
2663  uint32_t R;
2664  } IEEE_T_MCOL; /* Frames Transmitted with Multiple Collisions */
2665 
2666  union {
2667  uint32_t R;
2668  } IEEE_T_DEF; /* Frames Transmitted after Deferral Delay */
2669 
2670  union {
2671  uint32_t R;
2672  } IEEE_T_LCOL; /* Frames Transmitted with Late Collision */
2673 
2674  union {
2675  uint32_t R;
2676  } IEEE_T_EXCOL; /* Frames Transmitted with Excessive Collisions */
2677 
2678  union {
2679  uint32_t R;
2680  } IEEE_T_MACERR; /* Frames Transmitted with Tx FIFO Underrun */
2681 
2682  union {
2683  uint32_t R;
2684  } IEEE_T_CSERR; /* Frames Transmitted with Carrier Sense Error */
2685 
2686  union {
2687  uint32_t R;
2688  } IEEE_T_SQE; /* Frames Transmitted with SQE Error */
2689 
2690  union {
2691  uint32_t R;
2692  } IEEE_T_FDXFC; /* Flow Control Pause frames transmitted */
2693 
2694  union {
2695  uint32_t R;
2696  } IEEE_T_OCTETS_OK; /* Octet count for Frames Transmitted w/o Error */
2697 
2698  uint32_t fec_reserved_rmon_t_octets_ok[2];
2699 
2700  union {
2701  uint32_t R;
2702  } RMON_R_DROP; /* Count of frames not counted correctly */
2703 
2704  union {
2705  uint32_t R;
2706  } RMON_R_PACKETS; /* RMON Rx packet count */
2707 
2708  union {
2709  uint32_t R;
2710  } RMON_R_BC_PKT; /* RMON Rx Broadcast Packets */
2711 
2712  union {
2713  uint32_t R;
2714  } RMON_R_MC_PKT; /* RMON Rx Multicast Packets */
2715 
2716  union {
2717  uint32_t R;
2718  } RMON_R_CRC_ALIGN; /* RMON Rx Packets w CRC/Align error */
2719 
2720  union {
2721  uint32_t R;
2722  } RMON_R_UNDERSIZE; /* RMON Rx Packets < 64 bytes, good crc */
2723 
2724  union {
2725  uint32_t R;
2726  } RMON_R_OVERSIZE; /* RMON Rx Packets > MAX_FL bytes, good crc */
2727 
2728  union {
2729  uint32_t R;
2730  } RMON_R_FRAG; /* RMON Rx Packets < 64 bytes, bad crc */
2731 
2732  union {
2733  uint32_t R;
2734  } RMON_R_JAB; /* RMON Rx Packets > MAX_FL bytes, bad crc */
2735 
2736  uint32_t fec_reserved_rmon_r_jab;
2737 
2738  union {
2739  uint32_t R;
2740  } RMON_R_P64; /* RMON Rx 64 byte packets */
2741 
2742  union {
2743  uint32_t R;
2744  } RMON_R_P65TO127; /* RMON Rx 65 to 127 byte packets */
2745 
2746  union {
2747  uint32_t R;
2748  } RMON_R_P128TO255; /* RMON Rx 128 to 255 byte packets */
2749 
2750  union {
2751  uint32_t R;
2752  } RMON_R_P256TO511; /* RMON Rx 256 to 511 byte packets */
2753 
2754  union {
2755  uint32_t R;
2756  } RMON_R_P512TO1023; /* RMON Rx 512 to 1023 byte packets */
2757 
2758  union {
2759  uint32_t R;
2760  } RMON_R_P1024TO2047; /* RMON Rx 1024 to 2047 byte packets */
2761 
2762  union {
2763  uint32_t R;
2764  } RMON_R_P_GTE2048; /* RMON Rx packets w > 2048 bytes */
2765 
2766  union {
2767  uint32_t R;
2768  } RMON_R_OCTETS; /* RMON Rx Octets */
2769 
2770  union {
2771  uint32_t R;
2772  } IEEE_R_DROP; /* Count of frames not counted correctly */
2773 
2774  union {
2775  uint32_t R;
2776  } IEEE_R_FRAME_OK; /* Frames Received OK */
2777 
2778  union {
2779  uint32_t R;
2780  } IEEE_R_CRC; /* Frames Received with CRC Error */
2781 
2782  union {
2783  uint32_t R;
2784  } IEEE_R_ALIGN; /* Frames Received with Alignment Error */
2785 
2786  union {
2787  uint32_t R;
2788  } IEEE_R_MACERR; /* Receive Fifo Overflow count */
2789 
2790  union {
2791  uint32_t R;
2792  } IEEE_R_FDXFC; /* Flow Control Pause frames received */
2793 
2794  union {
2795  uint32_t R;
2796  } IEEE_R_OCTETS_OK; /* Octet count for Frames Rcvd w/o Error */
2797 
2798  }; /* end of FEC_tag */
2799 /*************************************************************************/
2800 /* MODULE : FLASH */
2801 /*************************************************************************/
2802  struct FLASH_tag {
2803  union {
2804  uint32_t R;
2805  struct {
2806  uint32_t:5;
2807  uint32_t SIZE:3;
2808  uint32_t:1;
2809  uint32_t LAS:3;
2810  uint32_t:3;
2811  uint32_t MAS:1;
2812  uint32_t EER:1;
2813  uint32_t RWE:1;
2814  uint32_t SBC:1;
2815  uint32_t:1;
2816  uint32_t PEAS:1;
2817  uint32_t DONE:1;
2818  uint32_t PEG:1;
2819  uint32_t:4;
2820  uint32_t PGM:1;
2821  uint32_t PSUS:1;
2822  uint32_t ERS:1;
2823  uint32_t ESUS:1;
2824  uint32_t EHV:1;
2825  } B;
2826  } MCR; /* Module Configuration Register */
2827 
2828  union {
2829  uint32_t R;
2830  struct {
2831  uint32_t LME:1;
2832  uint32_t:10;
2833  uint32_t SLOCK:1;
2834  uint32_t:2;
2835  uint32_t MLOCK:2;
2836  uint32_t:6;
2837  uint32_t LLOCK:10;
2838  } B;
2839  } LML; /* Low/Mid-address space block locking Register */
2840 
2841  union {
2842  uint32_t R;
2843  struct {
2844  uint32_t HBE:1;
2845  uint32_t:25;
2846  uint32_t HBLOCK:6;
2847  } B;
2848  } HBL; /* High-address space block locking Register */
2849 
2850  union {
2851  uint32_t R;
2852  struct {
2853  uint32_t SLE:1;
2854  uint32_t:10;
2855  uint32_t SSLOCK:1;
2856  uint32_t:2;
2857  uint32_t SMLOCK:2;
2858  uint32_t:6;
2859  uint32_t SLLOCK:10;
2860  } B;
2861  } SLL; /* Secondary low/mid-address space block locking Register */
2862 
2863  union {
2864  uint32_t R;
2865  struct {
2866  uint32_t:14;
2867  uint32_t MSEL:2;
2868  uint32_t:6;
2869  uint32_t LSEL:10;
2870  } B;
2871  } LMS; /* Low/Mid-address space block locking Register */
2872 
2873  union {
2874  uint32_t R;
2875  struct {
2876  uint32_t:26;
2877  uint32_t HBSEL:6;
2878  } B;
2879  } HBS; /* High-address space block locking Register */
2880 
2881  union {
2882  uint32_t R;
2883  struct {
2884  uint32_t SAD:1;
2885  uint32_t:10;
2886  uint32_t ADDR:18;
2887  uint32_t:3;
2888  } B;
2889  } ADR; /* Address Register */
2890 
2891  union {
2892  uint32_t R;
2893  struct {
2894  uint32_t LBCFG:4;
2895  uint32_t ARB:1;
2896  uint32_t PRI:1;
2897  uint32_t:1;
2898  uint32_t M8PFE:1;
2899  uint32_t:1;
2900  uint32_t M6PFE:1;
2901  uint32_t M5PFE:1;
2902  uint32_t M4PFE:1;
2903  uint32_t:1;
2904  uint32_t M2PFE:1;
2905  uint32_t M1PFE:1;
2906  uint32_t M0PFE:1;
2907  uint32_t APC:3;
2908  uint32_t WWSC:2;
2909  uint32_t RWSC:3;
2910  uint32_t:1;
2911  uint32_t DPFEN:1;
2912  uint32_t:1;
2913  uint32_t IPFEN:1;
2914  uint32_t:1;
2915  uint32_t PFLIM:2;
2916  uint32_t BFEN:1;
2917  } B;
2918  } PFCRP0; /* Platform Flash Configuration Register for Port 0 */
2919 
2920  union {
2921  uint32_t R;
2922  struct {
2923  uint32_t LBCFG:4;
2924  uint32_t:3;
2925  uint32_t M8PFE:1;
2926  uint32_t:1;
2927  uint32_t M6PFE:1;
2928  uint32_t M5PFE:1;
2929  uint32_t M4PFE:1;
2930  uint32_t:1;
2931  uint32_t M2PFE:1;
2932  uint32_t M1PFE:1;
2933  uint32_t M0PFE:1;
2934  uint32_t APC:3;
2935  uint32_t WWSC:2;
2936  uint32_t RWSC:3;
2937  uint32_t:1;
2938  uint32_t DPFEN:1;
2939  uint32_t:1;
2940  uint32_t IPFEN:1;
2941  uint32_t:1;
2942  uint32_t PFLIM:2;
2943  uint32_t BFEN:1;
2944  } B;
2945  } PFCRP1; /* Platform Flash Configuration Register for Port 1 */
2946 
2947  union {
2948  uint32_t R;
2949  struct {
2950  uint32_t M7AP:2;
2951  uint32_t M6AP:2;
2952  uint32_t M5AP:2;
2953  uint32_t M4AP:2;
2954  uint32_t M3AP:2;
2955  uint32_t M2AP:2;
2956  uint32_t M1AP:2;
2957  uint32_t M0AP:2;
2958  uint32_t SHSACC:4;
2959  uint32_t:4;
2960  uint32_t SHDACC:4;
2961  uint32_t:4;
2962  } B;
2963  } PFAPR; /* Platform Flash access protection Register */
2964 
2965  union {
2966  uint32_t R;
2967  struct {
2968  uint32_t:1;
2969  uint32_t SACC:31;
2970  } B;
2971  } PFSACC; /* PFlash Supervisor Access Control Register */
2972 
2973  union {
2974  uint32_t R;
2975  struct {
2976  uint32_t:1;
2977  uint32_t DACC:31;
2978  } B;
2979  } PFDACC; /* PFlash Data Access Control Register */
2980 
2981  uint32_t FLASH_reserved1[3];
2982 
2983  union {
2984  uint32_t R;
2985  struct {
2986  uint32_t UTE:1;
2987  uint32_t SCBE:1;
2988  uint32_t:6;
2989  uint32_t DSI:8;
2990  uint32_t:10;
2991  uint32_t MRE:1;
2992  uint32_t MRV:1;
2993  uint32_t EIE:1;
2994  uint32_t AIS:1;
2995  uint32_t AIE:1;
2996  uint32_t AID:1;
2997  } B;
2998  } UT0; /* User Test Register 0 */
2999 
3000  union {
3001  uint32_t R;
3002  struct {
3003  uint32_t DAI:32;
3004  } B;
3005  } UT1; /* User Test Register 1 */
3006 
3007  union {
3008  uint32_t R;
3009  struct {
3010  uint32_t DAI:32;
3011  } B;
3012  } UT2; /* User Test Register 2 */
3013 
3014  union {
3015  uint32_t R;
3016  struct {
3017  uint32_t MISR:32;
3018  } B;
3019  } MISR[5]; /* Multiple Input Signature Register */
3020 
3021  }; /* end of FLASH_tag */
3022 /*************************************************************************/
3023 /* MODULE : FlexCAN */
3024 /*************************************************************************/
3025  struct FLEXCAN_tag {
3026  union {
3027  uint32_t R;
3028  struct {
3029  uint32_t MDIS:1;
3030  uint32_t FRZ:1;
3031  uint32_t FEN:1;
3032  uint32_t HALT:1;
3033  uint32_t NOTRDY:1;
3034  uint32_t WAKMSK:1;
3035  uint32_t SOFTRST:1;
3036  uint32_t FRZACK:1;
3037  uint32_t SUPV:1;
3038  uint32_t SLFWAK:1;
3039  uint32_t WRNEN:1;
3040  uint32_t LPMACK:1;
3041  uint32_t WAKSRC:1;
3042  uint32_t DOZE:1;
3043  uint32_t SRXDIS:1;
3044  uint32_t BCC:1;
3045  uint32_t:2;
3046  uint32_t LPRIO_EN:1;
3047  uint32_t AEN:1;
3048  uint32_t:2;
3049  uint32_t IDAM:2;
3050  uint32_t:2;
3051  uint32_t MAXMB:6;
3052  } B;
3053  } MCR; /* Module Configuration Register */
3054 
3055  union {
3056  uint32_t R;
3057  struct {
3058  uint32_t PRESDIV:8;
3059  uint32_t RJW:2;
3060  uint32_t PSEG1:3;
3061  uint32_t PSEG2:3;
3062  uint32_t BOFFMSK:1;
3063  uint32_t ERRMSK:1;
3064  uint32_t CLKSRC:1;
3065  uint32_t LPB:1;
3066  uint32_t TWRNMSK:1;
3067  uint32_t RWRNMSK:1;
3068  uint32_t:2;
3069  uint32_t SMP:1;
3070  uint32_t BOFFREC:1;
3071  uint32_t TSYN:1;
3072  uint32_t LBUF:1;
3073  uint32_t LOM:1;
3074  uint32_t PROPSEG:3;
3075  } B;
3076  } CTRL; /* Control Register */
3077 
3078  union {
3079  uint32_t R;
3080  } TIMER; /* Free Running Timer */
3081 
3082  uint32_t FLEXCAN_reserved1;
3083 
3084  union {
3085  uint32_t R;
3086  struct {
3087  uint32_t MI:32;
3088  } B;
3089  } RXGMASK; /* RX Global Mask */
3090 
3091  union {
3092  uint32_t R;
3093  struct {
3094  uint32_t MI:32;
3095  } B;
3096  } RX14MASK; /* RX 14 Mask */
3097 
3098  union {
3099  uint32_t R;
3100  struct {
3101  uint32_t MI:32;
3102  } B;
3103  } RX15MASK; /* RX 15 Mask */
3104 
3105  union {
3106  uint32_t R;
3107  struct {
3108  uint32_t:16;
3109  uint32_t RXECNT:8;
3110  uint32_t TXECNT:8;
3111  } B;
3112  } ECR; /* Error Counter Register */
3113 
3114  union {
3115  uint32_t R;
3116  struct {
3117  uint32_t:14;
3118  uint32_t TWRNINT:1;
3119  uint32_t RWRNINT:1;
3120  uint32_t BIT1ERR:1;
3121  uint32_t BIT0ERR:1;
3122  uint32_t ACKERR:1;
3123  uint32_t CRCERR:1;
3124  uint32_t FRMERR:1;
3125  uint32_t STFERR:1;
3126  uint32_t TXWRN:1;
3127  uint32_t RXWRN:1;
3128  uint32_t IDLE:1;
3129  uint32_t TXRX:1;
3130  uint32_t FLTCONF:2;
3131  uint32_t:1;
3132  uint32_t BOFFINT:1;
3133  uint32_t ERRINT:1;
3134  uint32_t WAKINT:1;
3135  } B;
3136  } ESR; /* Error and Status Register */
3137 
3138  union {
3139  uint32_t R;
3140  struct {
3141  uint32_t BUF63M:1;
3142  uint32_t BUF62M:1;
3143  uint32_t BUF61M:1;
3144  uint32_t BUF60M:1;
3145  uint32_t BUF59M:1;
3146  uint32_t BUF58M:1;
3147  uint32_t BUF57M:1;
3148  uint32_t BUF56M:1;
3149  uint32_t BUF55M:1;
3150  uint32_t BUF54M:1;
3151  uint32_t BUF53M:1;
3152  uint32_t BUF52M:1;
3153  uint32_t BUF51M:1;
3154  uint32_t BUF50M:1;
3155  uint32_t BUF49M:1;
3156  uint32_t BUF48M:1;
3157  uint32_t BUF47M:1;
3158  uint32_t BUF46M:1;
3159  uint32_t BUF45M:1;
3160  uint32_t BUF44M:1;
3161  uint32_t BUF43M:1;
3162  uint32_t BUF42M:1;
3163  uint32_t BUF41M:1;
3164  uint32_t BUF40M:1;
3165  uint32_t BUF39M:1;
3166  uint32_t BUF38M:1;
3167  uint32_t BUF37M:1;
3168  uint32_t BUF36M:1;
3169  uint32_t BUF35M:1;
3170  uint32_t BUF34M:1;
3171  uint32_t BUF33M:1;
3172  uint32_t BUF32M:1;
3173  } B;
3174  } IMASK2; /* Interruput Masks Register */
3175 
3176  union {
3177  uint32_t R;
3178  struct {
3179  uint32_t BUF31M:1;
3180  uint32_t BUF30M:1;
3181  uint32_t BUF29M:1;
3182  uint32_t BUF28M:1;
3183  uint32_t BUF27M:1;
3184  uint32_t BUF26M:1;
3185  uint32_t BUF25M:1;
3186  uint32_t BUF24M:1;
3187  uint32_t BUF23M:1;
3188  uint32_t BUF22M:1;
3189  uint32_t BUF21M:1;
3190  uint32_t BUF20M:1;
3191  uint32_t BUF19M:1;
3192  uint32_t BUF18M:1;
3193  uint32_t BUF17M:1;
3194  uint32_t BUF16M:1;
3195  uint32_t BUF15M:1;
3196  uint32_t BUF14M:1;
3197  uint32_t BUF13M:1;
3198  uint32_t BUF12M:1;
3199  uint32_t BUF11M:1;
3200  uint32_t BUF10M:1;
3201  uint32_t BUF09M:1;
3202  uint32_t BUF08M:1;
3203  uint32_t BUF07M:1;
3204  uint32_t BUF06M:1;
3205  uint32_t BUF05M:1;
3206  uint32_t BUF04M:1;
3207  uint32_t BUF03M:1;
3208  uint32_t BUF02M:1;
3209  uint32_t BUF01M:1;
3210  uint32_t BUF00M:1;
3211  } B;
3212  } IMASK1; /* Interruput Masks Register */
3213 
3214  union {
3215  uint32_t R;
3216  struct {
3217  uint32_t BUF63I:1;
3218  uint32_t BUF62I:1;
3219  uint32_t BUF61I:1;
3220  uint32_t BUF60I:1;
3221  uint32_t BUF59I:1;
3222  uint32_t BUF58I:1;
3223  uint32_t BUF57I:1;
3224  uint32_t BUF56I:1;
3225  uint32_t BUF55I:1;
3226  uint32_t BUF54I:1;
3227  uint32_t BUF53I:1;
3228  uint32_t BUF52I:1;
3229  uint32_t BUF51I:1;
3230  uint32_t BUF50I:1;
3231  uint32_t BUF49I:1;
3232  uint32_t BUF48I:1;
3233  uint32_t BUF47I:1;
3234  uint32_t BUF46I:1;
3235  uint32_t BUF45I:1;
3236  uint32_t BUF44I:1;
3237  uint32_t BUF43I:1;
3238  uint32_t BUF42I:1;
3239  uint32_t BUF41I:1;
3240  uint32_t BUF40I:1;
3241  uint32_t BUF39I:1;
3242  uint32_t BUF38I:1;
3243  uint32_t BUF37I:1;
3244  uint32_t BUF36I:1;
3245  uint32_t BUF35I:1;
3246  uint32_t BUF34I:1;
3247  uint32_t BUF33I:1;
3248  uint32_t BUF32I:1;
3249  } B;
3250  } IFLAG2; /* Interruput Flag Register */
3251 
3252  union {
3253  uint32_t R;
3254  struct {
3255  uint32_t BUF31I:1;
3256  uint32_t BUF30I:1;
3257  uint32_t BUF29I:1;
3258  uint32_t BUF28I:1;
3259  uint32_t BUF27I:1;
3260  uint32_t BUF26I:1;
3261  uint32_t BUF25I:1;
3262  uint32_t BUF24I:1;
3263  uint32_t BUF23I:1;
3264  uint32_t BUF22I:1;
3265  uint32_t BUF21I:1;
3266  uint32_t BUF20I:1;
3267  uint32_t BUF19I:1;
3268  uint32_t BUF18I:1;
3269  uint32_t BUF17I:1;
3270  uint32_t BUF16I:1;
3271  uint32_t BUF15I:1;
3272  uint32_t BUF14I:1;
3273  uint32_t BUF13I:1;
3274  uint32_t BUF12I:1;
3275  uint32_t BUF11I:1;
3276  uint32_t BUF10I:1;
3277  uint32_t BUF09I:1;
3278  uint32_t BUF08I:1;
3279  uint32_t BUF07I:1;
3280  uint32_t BUF06I:1;
3281  uint32_t BUF05I:1;
3282  uint32_t BUF04I:1;
3283  uint32_t BUF03I:1;
3284  uint32_t BUF02I:1;
3285  uint32_t BUF01I:1;
3286  uint32_t BUF00I:1;
3287  } B;
3288  } IFLAG1; /* Interruput Flag Register */
3289 
3290  uint32_t FLEXCAN_reserved2[19];
3291 
3292  struct canbuf_t {
3293  union {
3294  uint32_t R;
3295  struct {
3296  uint32_t:4;
3297  uint32_t CODE:4;
3298  uint32_t:1;
3299  uint32_t SRR:1;
3300  uint32_t IDE:1;
3301  uint32_t RTR:1;
3302  uint32_t LENGTH:4;
3303  uint32_t TIMESTAMP:16;
3304  } B;
3305  } CS;
3306 
3307  union {
3308  uint32_t R;
3309  struct {
3310  uint32_t PRIO:3;
3311  uint32_t STD_ID:11;
3312  uint32_t EXT_ID:18;
3313  } B;
3314  } ID;
3315 
3316  union {
3317  /* uint8_t B[8]; Data buffer in Bytes (8 bits) */
3318  /* uint16_t H[4]; Data buffer in Half-words (16 bits) */
3319  uint32_t W[2]; /* Data buffer in words (32 bits) */
3320  /* uint32_t R[2]; Data buffer in words (32 bits) */
3321  } DATA;
3322 
3323  } BUF[64];
3324 
3325  uint32_t FLEXCAN_reserved3[256];
3326 
3327  union {
3328  uint32_t R;
3329  struct {
3330  uint32_t MI:32;
3331  } B;
3332  } RXIMR[64]; /* RX Individual Mask Registers */
3333 
3334  }; /* end of CTU_tag */
3335 /**************************************************************************/
3336 /* MODULE : FlexRay */
3337 /**************************************************************************/
3338 
3339  typedef union uMVR {
3340  uint16_t R;
3341  struct {
3342  uint16_t CHIVER:8; /* CHI Version Number */
3343  uint16_t PEVER:8; /* PE Version Number */
3344  } B;
3345  } MVR_t;
3346 
3347  typedef union uMCR {
3348  uint16_t R;
3349  struct {
3350  uint16_t MEN:1; /* module enable */
3351  uint16_t:1;
3352  uint16_t SCMD:1; /* single channel mode */
3353  uint16_t CHB:1; /* channel B enable */
3354  uint16_t CHA:1; /* channel A enable */
3355  uint16_t SFFE:1; /* synchronization frame filter enable */
3356  uint16_t:5;
3357  uint16_t CLKSEL:1; /* protocol engine clock source select */
3358  uint16_t PRESCALE:3; /* protocol engine clock prescaler */
3359  uint16_t:1;
3360  } B;
3361  } MCR_t;
3362  typedef union uSTBSCR {
3363  uint16_t R;
3364  struct {
3365  uint16_t WMD:1; /* write mode */
3366  uint16_t STBSSEL:7; /* strobe signal select */
3367  uint16_t:3;
3368  uint16_t ENB:1; /* strobe signal enable */
3369  uint16_t:2;
3370  uint16_t STBPSEL:2; /* strobe port select */
3371  } B;
3372  } STBSCR_t;
3373  typedef union uMBDSR {
3374  uint16_t R;
3375  struct {
3376  uint16_t:1;
3377  uint16_t MBSEG2DS:7; /* message buffer segment 2 data size */
3378  uint16_t:1;
3379  uint16_t MBSEG1DS:7; /* message buffer segment 1 data size */
3380  } B;
3381  } MBDSR_t;
3382 
3383  typedef union uMBSSUTR {
3384  uint16_t R;
3385  struct {
3386 
3387  uint16_t:2;
3388  uint16_t LAST_MB_SEG1:6; /* last message buffer control register for message buffer segment 1 */
3389  uint16_t:2;
3390  uint16_t LAST_MB_UTIL:6; /* last message buffer utilized */
3391  } B;
3392  } MBSSUTR_t;
3393 
3394  typedef union uPOCR {
3395  uint16_t R;
3396  uint8_t byte[2];
3397  struct {
3398  uint16_t WME:1; /* write mode external correction command */
3399  uint16_t:3;
3400  uint16_t EOC_AP:2; /* external offset correction application */
3401  uint16_t ERC_AP:2; /* external rate correction application */
3402  uint16_t BSY:1; /* command write busy / write mode command */
3403  uint16_t:3;
3404  uint16_t POCCMD:4; /* protocol command */
3405  } B;
3406  } POCR_t;
3407 /* protocol commands */
3408  typedef union uGIFER {
3409  uint16_t R;
3410  struct {
3411  uint16_t MIF:1; /* module interrupt flag */
3412  uint16_t PRIF:1; /* protocol interrupt flag */
3413  uint16_t CHIF:1; /* CHI interrupt flag */
3414  uint16_t WKUPIF:1; /* wakeup interrupt flag */
3415  uint16_t FNEBIF:1; /* receive FIFO channel B not empty interrupt flag */
3416  uint16_t FNEAIF:1; /* receive FIFO channel A not empty interrupt flag */
3417  uint16_t RBIF:1; /* receive message buffer interrupt flag */
3418  uint16_t TBIF:1; /* transmit buffer interrupt flag */
3419  uint16_t MIE:1; /* module interrupt enable */
3420  uint16_t PRIE:1; /* protocol interrupt enable */
3421  uint16_t CHIE:1; /* CHI interrupt enable */
3422  uint16_t WKUPIE:1; /* wakeup interrupt enable */
3423  uint16_t FNEBIE:1; /* receive FIFO channel B not empty interrupt enable */
3424  uint16_t FNEAIE:1; /* receive FIFO channel A not empty interrupt enable */
3425  uint16_t RBIE:1; /* receive message buffer interrupt enable */
3426  uint16_t TBIE:1; /* transmit buffer interrupt enable */
3427  } B;
3428  } GIFER_t;
3429  typedef union uPIFR0 {
3430  uint16_t R;
3431  struct {
3432  uint16_t FATLIF:1; /* fatal protocol error interrupt flag */
3433  uint16_t INTLIF:1; /* internal protocol error interrupt flag */
3434  uint16_t ILCFIF:1; /* illegal protocol configuration flag */
3435  uint16_t CSAIF:1; /* cold start abort interrupt flag */
3436  uint16_t MRCIF:1; /* missing rate correctio interrupt flag */
3437  uint16_t MOCIF:1; /* missing offset correctio interrupt flag */
3438  uint16_t CCLIF:1; /* clock correction limit reached interrupt flag */
3439  uint16_t MXSIF:1; /* max sync frames detected interrupt flag */
3440  uint16_t MTXIF:1; /* media access test symbol received flag */
3441  uint16_t LTXBIF:1; /* pdLatestTx violation on channel B interrupt flag */
3442  uint16_t LTXAIF:1; /* pdLatestTx violation on channel A interrupt flag */
3443  uint16_t TBVBIF:1; /* Transmission across boundary on channel B Interrupt Flag */
3444  uint16_t TBVAIF:1; /* Transmission across boundary on channel A Interrupt Flag */
3445  uint16_t TI2IF:1; /* timer 2 expired interrupt flag */
3446  uint16_t TI1IF:1; /* timer 1 expired interrupt flag */
3447  uint16_t CYSIF:1; /* cycle start interrupt flag */
3448  } B;
3449  } PIFR0_t;
3450  typedef union uPIFR1 {
3451  uint16_t R;
3452  struct {
3453  uint16_t EMCIF:1; /* error mode changed interrupt flag */
3454  uint16_t IPCIF:1; /* illegal protocol command interrupt flag */
3455  uint16_t PECFIF:1; /* protocol engine communication failure interrupt flag */
3456  uint16_t PSCIF:1; /* Protocol State Changed Interrupt Flag */
3457  uint16_t SSI3IF:1; /* slot status counter incremented interrupt flag */
3458  uint16_t SSI2IF:1; /* slot status counter incremented interrupt flag */
3459  uint16_t SSI1IF:1; /* slot status counter incremented interrupt flag */
3460  uint16_t SSI0IF:1; /* slot status counter incremented interrupt flag */
3461  uint16_t:2;
3462  uint16_t EVTIF:1; /* even cycle table written interrupt flag */
3463  uint16_t ODTIF:1; /* odd cycle table written interrupt flag */
3464  uint16_t:4;
3465  } B;
3466  } PIFR1_t;
3467  typedef union uPIER0 {
3468  uint16_t R;
3469  struct {
3470  uint16_t FATLIE:1; /* fatal protocol error interrupt enable */
3471  uint16_t INTLIE:1; /* internal protocol error interrupt interrupt enable */
3472  uint16_t ILCFIE:1; /* illegal protocol configuration interrupt enable */
3473  uint16_t CSAIE:1; /* cold start abort interrupt enable */
3474  uint16_t MRCIE:1; /* missing rate correctio interrupt enable */
3475  uint16_t MOCIE:1; /* missing offset correctio interrupt enable */
3476  uint16_t CCLIE:1; /* clock correction limit reached interrupt enable */
3477  uint16_t MXSIE:1; /* max sync frames detected interrupt enable */
3478  uint16_t MTXIE:1; /* media access test symbol received interrupt enable */
3479  uint16_t LTXBIE:1; /* pdLatestTx violation on channel B interrupt enable */
3480  uint16_t LTXAIE:1; /* pdLatestTx violation on channel A interrupt enable */
3481  uint16_t TBVBIE:1; /* Transmission across boundary on channel B Interrupt enable */
3482  uint16_t TBVAIE:1; /* Transmission across boundary on channel A Interrupt enable */
3483  uint16_t TI2IE:1; /* timer 2 expired interrupt enable */
3484  uint16_t TI1IE:1; /* timer 1 expired interrupt enable */
3485  uint16_t CYSIE:1; /* cycle start interrupt enable */
3486  } B;
3487  } PIER0_t;
3488  typedef union uPIER1 {
3489  uint16_t R;
3490  struct {
3491  uint16_t EMCIE:1; /* error mode changed interrupt enable */
3492  uint16_t IPCIE:1; /* illegal protocol command interrupt enable */
3493  uint16_t PECFIE:1; /* protocol engine communication failure interrupt enable */
3494  uint16_t PSCIE:1; /* Protocol State Changed Interrupt enable */
3495  uint16_t SSI3IE:1; /* slot status counter incremented interrupt enable */
3496  uint16_t SSI2IE:1; /* slot status counter incremented interrupt enable */
3497  uint16_t SSI1IE:1; /* slot status counter incremented interrupt enable */
3498  uint16_t SSI0IE:1; /* slot status counter incremented interrupt enable */
3499  uint16_t:2;
3500  uint16_t EVTIE:1; /* even cycle table written interrupt enable */
3501  uint16_t ODTIE:1; /* odd cycle table written interrupt enable */
3502  uint16_t:4;
3503  } B;
3504  } PIER1_t;
3505  typedef union uCHIERFR {
3506  uint16_t R;
3507  struct {
3508  uint16_t FRLBEF:1; /* flame lost channel B error flag */
3509  uint16_t FRLAEF:1; /* frame lost channel A error flag */
3510  uint16_t PCMIEF:1; /* command ignored error flag */
3511  uint16_t FOVBEF:1; /* receive FIFO overrun channel B error flag */
3512  uint16_t FOVAEF:1; /* receive FIFO overrun channel A error flag */
3513  uint16_t MSBEF:1; /* message buffer search error flag */
3514  uint16_t MBUEF:1; /* message buffer utilization error flag */
3515  uint16_t LCKEF:1; /* lock error flag */
3516  uint16_t DBLEF:1; /* double transmit message buffer lock error flag */
3517  uint16_t SBCFEF:1; /* system bus communication failure error flag */
3518  uint16_t FIDEF:1; /* frame ID error flag */
3519  uint16_t DPLEF:1; /* dynamic payload length error flag */
3520  uint16_t SPLEF:1; /* static payload length error flag */
3521  uint16_t NMLEF:1; /* network management length error flag */
3522  uint16_t NMFEF:1; /* network management frame error flag */
3523  uint16_t ILSAEF:1; /* illegal access error flag */
3524  } B;
3525  } CHIERFR_t;
3526  typedef union uMBIVEC {
3527  uint16_t R;
3528  struct {
3529 
3530  uint16_t:2;
3531  uint16_t TBIVEC:6; /* transmit buffer interrupt vector */
3532  uint16_t:2;
3533  uint16_t RBIVEC:6; /* receive buffer interrupt vector */
3534  } B;
3535  } MBIVEC_t;
3536 
3537  typedef union uPSR0 {
3538  uint16_t R;
3539  struct {
3540  uint16_t ERRMODE:2; /* error mode */
3541  uint16_t SLOTMODE:2; /* slot mode */
3542  uint16_t:1;
3543  uint16_t PROTSTATE:3; /* protocol state */
3544  uint16_t SUBSTATE:4; /* protocol sub state */
3545  uint16_t:1;
3546  uint16_t WAKEUPSTATUS:3; /* wakeup status */
3547  } B;
3548  } PSR0_t;
3549 
3550 /* protocol states */
3551 /* protocol sub-states */
3552 /* wakeup status */
3553  typedef union uPSR1 {
3554  uint16_t R;
3555  struct {
3556  uint16_t CSAA:1; /* cold start attempt abort flag */
3557  uint16_t SCP:1; /* cold start path */
3558  uint16_t:1;
3559  uint16_t REMCSAT:5; /* remanining coldstart attempts */
3560  uint16_t CPN:1; /* cold start noise path */
3561  uint16_t HHR:1; /* host halt request pending */
3562  uint16_t FRZ:1; /* freeze occured */
3563  uint16_t APTAC:5; /* allow passive to active counter */
3564  } B;
3565  } PSR1_t;
3566  typedef union uPSR2 {
3567  uint16_t R;
3568  struct {
3569  uint16_t NBVB:1; /* NIT boundary violation on channel B */
3570  uint16_t NSEB:1; /* NIT syntax error on channel B */
3571  uint16_t STCB:1; /* symbol window transmit conflict on channel B */
3572  uint16_t SBVB:1; /* symbol window boundary violation on channel B */
3573  uint16_t SSEB:1; /* symbol window syntax error on channel B */
3574  uint16_t MTB:1; /* media access test symbol MTS received on channel B */
3575  uint16_t NBVA:1; /* NIT boundary violation on channel A */
3576  uint16_t NSEA:1; /* NIT syntax error on channel A */
3577  uint16_t STCA:1; /* symbol window transmit conflict on channel A */
3578  uint16_t SBVA:1; /* symbol window boundary violation on channel A */
3579  uint16_t SSEA:1; /* symbol window syntax error on channel A */
3580  uint16_t MTA:1; /* media access test symbol MTS received on channel A */
3581  uint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */
3582  } B;
3583  } PSR2_t;
3584  typedef union uPSR3 {
3585  uint16_t R;
3586  struct {
3587  uint16_t:2;
3588  uint16_t WUB:1; /* wakeup symbol received on channel B */
3589  uint16_t ABVB:1; /* aggregated boundary violation on channel B */
3590  uint16_t AACB:1; /* aggregated additional communication on channel B */
3591  uint16_t ACEB:1; /* aggregated content error on channel B */
3592  uint16_t ASEB:1; /* aggregated syntax error on channel B */
3593  uint16_t AVFB:1; /* aggregated valid frame on channel B */
3594  uint16_t:2;
3595  uint16_t WUA:1; /* wakeup symbol received on channel A */
3596  uint16_t ABVA:1; /* aggregated boundary violation on channel A */
3597  uint16_t AACA:1; /* aggregated additional communication on channel A */
3598  uint16_t ACEA:1; /* aggregated content error on channel A */
3599  uint16_t ASEA:1; /* aggregated syntax error on channel A */
3600  uint16_t AVFA:1; /* aggregated valid frame on channel A */
3601  } B;
3602  } PSR3_t;
3603  typedef union uCIFRR {
3604  uint16_t R;
3605  struct {
3606  uint16_t:8;
3607  uint16_t MIFR:1; /* module interrupt flag */
3608  uint16_t PRIFR:1; /* protocol interrupt flag */
3609  uint16_t CHIFR:1; /* CHI interrupt flag */
3610  uint16_t WUPIFR:1; /* wakeup interrupt flag */
3611  uint16_t FNEBIFR:1; /* receive fifo channel B no empty interrupt flag */
3612  uint16_t FNEAIFR:1; /* receive fifo channel A no empty interrupt flag */
3613  uint16_t RBIFR:1; /* receive message buffer interrupt flag */
3614  uint16_t TBIFR:1; /* transmit buffer interrupt flag */
3615  } B;
3616  } CIFRR_t;
3617  typedef union uSYMATOR {
3618  uint16_t R;
3619  struct {
3620  uint16_t:11;
3621  uint16_t TIMEOUT:5; /* system memory time out value */
3622  } B;
3623  } SYMATOR_t;
3624 
3625  typedef union uSFCNTR {
3626  uint16_t R;
3627  struct {
3628  uint16_t SFEVB:4; /* sync frames channel B, even cycle */
3629  uint16_t SFEVA:4; /* sync frames channel A, even cycle */
3630  uint16_t SFODB:4; /* sync frames channel B, odd cycle */
3631  uint16_t SFODA:4; /* sync frames channel A, odd cycle */
3632  } B;
3633  } SFCNTR_t;
3634 
3635  typedef union uSFTCCSR {
3636  uint16_t R;
3637  struct {
3638  uint16_t ELKT:1; /* even cycle tables lock and unlock trigger */
3639  uint16_t OLKT:1; /* odd cycle tables lock and unlock trigger */
3640  uint16_t CYCNUM:6; /* cycle number */
3641  uint16_t ELKS:1; /* even cycle tables lock status */
3642  uint16_t OLKS:1; /* odd cycle tables lock status */
3643  uint16_t EVAL:1; /* even cycle tables valid */
3644  uint16_t OVAL:1; /* odd cycle tables valid */
3645  uint16_t:1;
3646  uint16_t OPT:1; /*one pair trigger */
3647  uint16_t SDVEN:1; /* sync frame deviation table enable */
3648  uint16_t SIDEN:1; /* sync frame ID table enable */
3649  } B;
3650  } SFTCCSR_t;
3651  typedef union uSFIDRFR {
3652  uint16_t R;
3653  struct {
3654  uint16_t:6;
3655  uint16_t SYNFRID:10; /* sync frame rejection ID */
3656  } B;
3657  } SFIDRFR_t;
3658 
3659  typedef union uTICCR {
3660  uint16_t R;
3661  struct {
3662  uint16_t:2;
3663  uint16_t T2CFG:1; /* timer 2 configuration */
3664  uint16_t T2REP:1; /* timer 2 repetitive mode */
3665  uint16_t:1;
3666  uint16_t T2SP:1; /* timer 2 stop */
3667  uint16_t T2TR:1; /* timer 2 trigger */
3668  uint16_t T2ST:1; /* timer 2 state */
3669  uint16_t:3;
3670  uint16_t T1REP:1; /* timer 1 repetitive mode */
3671  uint16_t:1;
3672  uint16_t T1SP:1; /* timer 1 stop */
3673  uint16_t T1TR:1; /* timer 1 trigger */
3674  uint16_t T1ST:1; /* timer 1 state */
3675 
3676  } B;
3677  } TICCR_t;
3678  typedef union uTI1CYSR {
3679  uint16_t R;
3680  struct {
3681  uint16_t:2;
3682  uint16_t TI1CYCVAL:6; /* timer 1 cycle filter value */
3683  uint16_t:2;
3684  uint16_t TI1CYCMSK:6; /* timer 1 cycle filter mask */
3685 
3686  } B;
3687  } TI1CYSR_t;
3688 
3689  typedef union uSSSR {
3690  uint16_t R;
3691  struct {
3692  uint16_t WMD:1; /* write mode */
3693  uint16_t:1;
3694  uint16_t SEL:2; /* static slot number */
3695  uint16_t:1;
3696  uint16_t SLOTNUMBER:11; /* selector */
3697  } B;
3698  } SSSR_t;
3699 
3700  typedef union uSSCCR {
3701  uint16_t R;
3702  struct {
3703  uint16_t WMD:1; /* write mode */
3704  uint16_t:1;
3705  uint16_t SEL:2; /* selector */
3706  uint16_t:1;
3707  uint16_t CNTCFG:2; /* counter configuration */
3708  uint16_t MCY:1; /* multi cycle selection */
3709  uint16_t VFR:1; /* valid frame selection */
3710  uint16_t SYF:1; /* sync frame selection */
3711  uint16_t NUF:1; /* null frame selection */
3712  uint16_t SUF:1; /* startup frame selection */
3713  uint16_t STATUSMASK:4; /* slot status mask */
3714  } B;
3715  } SSCCR_t;
3716  typedef union uSSR {
3717  uint16_t R;
3718  struct {
3719  uint16_t VFB:1; /* valid frame on channel B */
3720  uint16_t SYB:1; /* valid sync frame on channel B */
3721  uint16_t NFB:1; /* valid null frame on channel B */
3722  uint16_t SUB:1; /* valid startup frame on channel B */
3723  uint16_t SEB:1; /* syntax error on channel B */
3724  uint16_t CEB:1; /* content error on channel B */
3725  uint16_t BVB:1; /* boundary violation on channel B */
3726  uint16_t TCB:1; /* tx conflict on channel B */
3727  uint16_t VFA:1; /* valid frame on channel A */
3728  uint16_t SYA:1; /* valid sync frame on channel A */
3729  uint16_t NFA:1; /* valid null frame on channel A */
3730  uint16_t SUA:1; /* valid startup frame on channel A */
3731  uint16_t SEA:1; /* syntax error on channel A */
3732  uint16_t CEA:1; /* content error on channel A */
3733  uint16_t BVA:1; /* boundary violation on channel A */
3734  uint16_t TCA:1; /* tx conflict on channel A */
3735  } B;
3736  } SSR_t;
3737  typedef union uMTSCFR {
3738  uint16_t R;
3739  struct {
3740  uint16_t MTE:1; /* media access test symbol transmission enable */
3741  uint16_t:1;
3742  uint16_t CYCCNTMSK:6; /* cycle counter mask */
3743  uint16_t:2;
3744  uint16_t CYCCNTVAL:6; /* cycle counter value */
3745  } B;
3746  } MTSCFR_t;
3747 
3748  typedef union uRSBIR {
3749  uint16_t R;
3750  struct {
3751  uint16_t WMD:1; /* write mode */
3752  uint16_t:1;
3753  uint16_t SEL:2; /* selector */
3754  uint16_t:5;
3755  uint16_t RSBIDX:7; /* receive shadow buffer index */
3756  } B;
3757  } RSBIR_t;
3758 
3759  typedef union uRFDSR {
3760  uint16_t R;
3761  struct {
3762  uint16_t FIFODEPTH:8; /* fifo depth */
3763  uint16_t:1;
3764  uint16_t ENTRYSIZE:7; /* entry size */
3765  } B;
3766  } RFDSR_t;
3767 
3768  typedef union uRFRFCFR {
3769  uint16_t R;
3770  struct {
3771  uint16_t WMD:1; /* write mode */
3772  uint16_t IBD:1; /* interval boundary */
3773  uint16_t SEL:2; /* filter number */
3774  uint16_t:1;
3775  uint16_t SID:11; /* slot ID */
3776  } B;
3777  } RFRFCFR_t;
3778 
3779  typedef union uRFRFCTR {
3780  uint16_t R;
3781  struct {
3782  uint16_t:4;
3783  uint16_t F3MD:1; /* filter mode */
3784  uint16_t F2MD:1; /* filter mode */
3785  uint16_t F1MD:1; /* filter mode */
3786  uint16_t F0MD:1; /* filter mode */
3787  uint16_t:4;
3788  uint16_t F3EN:1; /* filter enable */
3789  uint16_t F2EN:1; /* filter enable */
3790  uint16_t F1EN:1; /* filter enable */
3791  uint16_t F0EN:1; /* filter enable */
3792  } B;
3793  } RFRFCTR_t;
3794  typedef union uPCR0 {
3795  uint16_t R;
3796  struct {
3797  uint16_t ACTION_POINT_OFFSET:6;
3798  uint16_t STATIC_SLOT_LENGTH:10;
3799  } B;
3800  } PCR0_t;
3801 
3802  typedef union uPCR1 {
3803  uint16_t R;
3804  struct {
3805  uint16_t:2;
3806  uint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;
3807  } B;
3808  } PCR1_t;
3809 
3810  typedef union uPCR2 {
3811  uint16_t R;
3812  struct {
3813  uint16_t MINISLOT_AFTER_ACTION_POINT:6;
3814  uint16_t NUMBER_OF_STATIC_SLOTS:10;
3815  } B;
3816  } PCR2_t;
3817 
3818  typedef union uPCR3 {
3819  uint16_t R;
3820  struct {
3821  uint16_t WAKEUP_SYMBOL_RX_LOW:6;
3822  uint16_t MINISLOT_ACTION_POINT_OFFSET:5;
3823  uint16_t COLDSTART_ATTEMPTS:5;
3824  } B;
3825  } PCR3_t;
3826 
3827  typedef union uPCR4 {
3828  uint16_t R;
3829  struct {
3830  uint16_t CAS_RX_LOW_MAX:7;
3831  uint16_t WAKEUP_SYMBOL_RX_WINDOW:9;
3832  } B;
3833  } PCR4_t;
3834 
3835  typedef union uPCR5 {
3836  uint16_t R;
3837  struct {
3838  uint16_t TSS_TRANSMITTER:4;
3839  uint16_t WAKEUP_SYMBOL_TX_LOW:6;
3840  uint16_t WAKEUP_SYMBOL_RX_IDLE:6;
3841  } B;
3842  } PCR5_t;
3843 
3844  typedef union uPCR6 {
3845  uint16_t R;
3846  struct {
3847  uint16_t:1;
3848  uint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;
3849  uint16_t MACRO_INITIAL_OFFSET_A:7;
3850  } B;
3851  } PCR6_t;
3852 
3853  typedef union uPCR7 {
3854  uint16_t R;
3855  struct {
3856  uint16_t DECODING_CORRECTION_B:9;
3857  uint16_t MICRO_PER_MACRO_NOM_HALF:7;
3858  } B;
3859  } PCR7_t;
3860 
3861  typedef union uPCR8 {
3862  uint16_t R;
3863  struct {
3864  uint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;
3865  uint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;
3866  uint16_t WAKEUP_SYMBOL_TX_IDLE:8;
3867  } B;
3868  } PCR8_t;
3869 
3870  typedef union uPCR9 {
3871  uint16_t R;
3872  struct {
3873  uint16_t MINISLOT_EXISTS:1;
3874  uint16_t SYMBOL_WINDOW_EXISTS:1;
3875  uint16_t OFFSET_CORRECTION_OUT:14;
3876  } B;
3877  } PCR9_t;
3878 
3879  typedef union uPCR10 {
3880  uint16_t R;
3881  struct {
3882  uint16_t SINGLE_SLOT_ENABLED:1;
3883  uint16_t WAKEUP_CHANNEL:1;
3884  uint16_t MACRO_PER_CYCLE:14;
3885  } B;
3886  } PCR10_t;
3887 
3888  typedef union uPCR11 {
3889  uint16_t R;
3890  struct {
3891  uint16_t KEY_SLOT_USED_FOR_STARTUP:1;
3892  uint16_t KEY_SLOT_USED_FOR_SYNC:1;
3893  uint16_t OFFSET_CORRECTION_START:14;
3894  } B;
3895  } PCR11_t;
3896 
3897  typedef union uPCR12 {
3898  uint16_t R;
3899  struct {
3900  uint16_t ALLOW_PASSIVE_TO_ACTIVE:5;
3901  uint16_t KEY_SLOT_HEADER_CRC:11;
3902  } B;
3903  } PCR12_t;
3904 
3905  typedef union uPCR13 {
3906  uint16_t R;
3907  struct {
3908  uint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;
3909  uint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;
3910  } B;
3911  } PCR13_t;
3912 
3913  typedef union uPCR14 {
3914  uint16_t R;
3915  struct {
3916  uint16_t RATE_CORRECTION_OUT:11;
3917  uint16_t LISTEN_TIMEOUT_H:5;
3918  } B;
3919  } PCR14_t;
3920 
3921  typedef union uPCR15 {
3922  uint16_t R;
3923  struct {
3924  uint16_t LISTEN_TIMEOUT_L:16;
3925  } B;
3926  } PCR15_t;
3927 
3928  typedef union uPCR16 {
3929  uint16_t R;
3930  struct {
3931  uint16_t MACRO_INITIAL_OFFSET_B:7;
3932  uint16_t NOISE_LISTEN_TIMEOUT_H:9;
3933  } B;
3934  } PCR16_t;
3935 
3936  typedef union uPCR17 {
3937  uint16_t R;
3938  struct {
3939  uint16_t NOISE_LISTEN_TIMEOUT_L:16;
3940  } B;
3941  } PCR17_t;
3942 
3943  typedef union uPCR18 {
3944  uint16_t R;
3945  struct {
3946  uint16_t WAKEUP_PATTERN:6;
3947  uint16_t KEY_SLOT_ID:10;
3948  } B;
3949  } PCR18_t;
3950 
3951  typedef union uPCR19 {
3952  uint16_t R;
3953  struct {
3954  uint16_t DECODING_CORRECTION_A:9;
3955  uint16_t PAYLOAD_LENGTH_STATIC:7;
3956  } B;
3957  } PCR19_t;
3958 
3959  typedef union uPCR20 {
3960  uint16_t R;
3961  struct {
3962  uint16_t MICRO_INITIAL_OFFSET_B:8;
3963  uint16_t MICRO_INITIAL_OFFSET_A:8;
3964  } B;
3965  } PCR20_t;
3966 
3967  typedef union uPCR21 {
3968  uint16_t R;
3969  struct {
3970  uint16_t EXTERN_RATE_CORRECTION:3;
3971  uint16_t LATEST_TX:13;
3972  } B;
3973  } PCR21_t;
3974 
3975  typedef union uPCR22 {
3976  uint16_t R;
3977  struct {
3978  uint16_t:1;
3979  uint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;
3980  uint16_t MICRO_PER_CYCLE_H:4;
3981  } B;
3982  } PCR22_t;
3983 
3984  typedef union uPCR23 {
3985  uint16_t R;
3986  struct {
3987  uint16_t micro_per_cycle_l:16;
3988  } B;
3989  } PCR23_t;
3990 
3991  typedef union uPCR24 {
3992  uint16_t R;
3993  struct {
3994  uint16_t CLUSTER_DRIFT_DAMPING:5;
3995  uint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;
3996  uint16_t MICRO_PER_CYCLE_MIN_H:4;
3997  } B;
3998  } PCR24_t;
3999 
4000  typedef union uPCR25 {
4001  uint16_t R;
4002  struct {
4003  uint16_t MICRO_PER_CYCLE_MIN_L:16;
4004  } B;
4005  } PCR25_t;
4006 
4007  typedef union uPCR26 {
4008  uint16_t R;
4009  struct {
4010  uint16_t ALLOW_HALT_DUE_TO_CLOCK:1;
4011  uint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;
4012  uint16_t MICRO_PER_CYCLE_MAX_H:4;
4013  } B;
4014  } PCR26_t;
4015 
4016  typedef union uPCR27 {
4017  uint16_t R;
4018  struct {
4019  uint16_t MICRO_PER_CYCLE_MAX_L:16;
4020  } B;
4021  } PCR27_t;
4022 
4023  typedef union uPCR28 {
4024  uint16_t R;
4025  struct {
4026  uint16_t DYNAMIC_SLOT_IDLE_PHASE:2;
4027  uint16_t MACRO_AFTER_OFFSET_CORRECTION:14;
4028  } B;
4029  } PCR28_t;
4030 
4031  typedef union uPCR29 {
4032  uint16_t R;
4033  struct {
4034  uint16_t EXTERN_OFFSET_CORRECTION:3;
4035  uint16_t MINISLOTS_MAX:13;
4036  } B;
4037  } PCR29_t;
4038 
4039  typedef union uPCR30 {
4040  uint16_t R;
4041  struct {
4042  uint16_t:12;
4043  uint16_t SYNC_NODE_MAX:4;
4044  } B;
4045  } PCR30_t;
4046 
4047  typedef struct uMSG_BUFF_CCS {
4048  union {
4049  uint16_t R;
4050  struct {
4051  uint16_t:1;
4052  uint16_t MCM:1; /* message buffer commit mode */
4053  uint16_t MBT:1; /* message buffer type */
4054  uint16_t MTD:1; /* message buffer direction */
4055  uint16_t CMT:1; /* commit for transmission */
4056  uint16_t EDT:1; /* enable / disable trigger */
4057  uint16_t LCKT:1; /* lock request trigger */
4058  uint16_t MBIE:1; /* message buffer interrupt enable */
4059  uint16_t:3;
4060  uint16_t DUP:1; /* data updated */
4061  uint16_t DVAL:1; /* data valid */
4062  uint16_t EDS:1; /* lock status */
4063  uint16_t LCKS:1; /* enable / disable status */
4064  uint16_t MBIF:1; /* message buffer interrupt flag */
4065  } B;
4066  } MBCCSR;
4067  union {
4068  uint16_t R;
4069  struct {
4070  uint16_t MTM:1; /* message buffer transmission mode */
4071  uint16_t CHNLA:1; /* channel assignement */
4072  uint16_t CHNLB:1; /* channel assignement */
4073  uint16_t CCFE:1; /* cycle counter filter enable */
4074  uint16_t CCFMSK:6; /* cycle counter filter mask */
4075  uint16_t CCFVAL:6; /* cycle counter filter value */
4076  } B;
4077  } MBCCFR;
4078  union {
4079  uint16_t R;
4080  struct {
4081  uint16_t:5;
4082  uint16_t FID:11; /* frame ID */
4083  } B;
4084  } MBFIDR;
4085 
4086  union {
4087  uint16_t R;
4088  struct {
4089  uint16_t:9;
4090  uint16_t MBIDX:7; /* message buffer index */
4091  } B;
4092  } MBIDXR;
4093  } MSG_BUFF_CCS_t;
4094  typedef union uSYSBADHR {
4095  uint16_t R;
4096  } SYSBADHR_t;
4097  typedef union uSYSBADLR {
4098  uint16_t R;
4099  } SYSBADLR_t;
4100  typedef union uPADR {
4101  uint16_t R;
4102  } PADR_t;
4103  typedef union uPDAR {
4104  uint16_t R;
4105  } PDAR_t;
4106  typedef union uCASERCR {
4107  uint16_t R;
4108  } CASERCR_t;
4109  typedef union uCBSERCR {
4110  uint16_t R;
4111  } CBSERCR_t;
4112  typedef union uCYCTR {
4113  uint16_t R;
4114  } CYCTR_t;
4115  typedef union uMTCTR {
4116  uint16_t R;
4117  } MTCTR_t;
4118  typedef union uSLTCTAR {
4119  uint16_t R;
4120  } SLTCTAR_t;
4121  typedef union uSLTCTBR {
4122  uint16_t R;
4123  } SLTCTBR_t;
4124  typedef union uRTCORVR {
4125  uint16_t R;
4126  } RTCORVR_t;
4127  typedef union uOFCORVR {
4128  uint16_t R;
4129  } OFCORVR_t;
4130  typedef union uSFTOR {
4131  uint16_t R;
4132  } SFTOR_t;
4133  typedef union uSFIDAFVR {
4134  uint16_t R;
4135  } SFIDAFVR_t;
4136  typedef union uSFIDAFMR {
4137  uint16_t R;
4138  } SFIDAFMR_t;
4139  typedef union uNMVR {
4140  uint16_t R;
4141  } NMVR_t;
4142  typedef union uNMVLR {
4143  uint16_t R;
4144  } NMVLR_t;
4145  typedef union uT1MTOR {
4146  uint16_t R;
4147  } T1MTOR_t;
4148  typedef union uTI2CR0 {
4149  uint16_t R;
4150  } TI2CR0_t;
4151  typedef union uTI2CR1 {
4152  uint16_t R;
4153  } TI2CR1_t;
4154  typedef union uSSCR {
4155  uint16_t R;
4156  } SSCR_t;
4157  typedef union uRFSR {
4158  uint16_t R;
4159  } RFSR_t;
4160  typedef union uRFSIR {
4161  uint16_t R;
4162  } RFSIR_t;
4163  typedef union uRFARIR {
4164  uint16_t R;
4165  } RFARIR_t;
4166  typedef union uRFBRIR {
4167  uint16_t R;
4168  } RFBRIR_t;
4169  typedef union uRFMIDAFVR {
4170  uint16_t R;
4171  } RFMIDAFVR_t;
4172  typedef union uRFMIAFMR {
4173  uint16_t R;
4174  } RFMIAFMR_t;
4175  typedef union uRFFIDRFVR {
4176  uint16_t R;
4177  } RFFIDRFVR_t;
4178  typedef union uRFFIDRFMR {
4179  uint16_t R;
4180  } RFFIDRFMR_t;
4181  typedef union uLDTXSLAR {
4182  uint16_t R;
4183  } LDTXSLAR_t;
4184  typedef union uLDTXSLBR {
4185  uint16_t R;
4186  } LDTXSLBR_t;
4187 
4188  typedef struct FR_tag {
4189  volatile MVR_t MVR; /*module version register *//*0 */
4190  volatile MCR_t MCR; /*module configuration register *//*2 */
4191  volatile SYSBADHR_t SYSBADHR; /*system memory base address high register *//*4 */
4192  volatile SYSBADLR_t SYSBADLR; /*system memory base address low register *//*6 */
4193  volatile STBSCR_t STBSCR; /*strobe signal control register *//*8 */
4194  uint16_t reserved0[1]; /*A */
4195  volatile MBDSR_t MBDSR; /*message buffer data size register *//*C */
4196  volatile MBSSUTR_t MBSSUTR; /*message buffer segment size and utilization register *//*E */
4197  uint16_t reserved1[1]; /*10 */
4198  uint16_t reserved2[1]; /*12 */
4199  volatile POCR_t POCR; /*Protocol operation control register *//*14 */
4200  volatile GIFER_t GIFER; /*global interrupt flag and enable register *//*16 */
4201  volatile PIFR0_t PIFR0; /*protocol interrupt flag register 0 *//*18 */
4202  volatile PIFR1_t PIFR1; /*protocol interrupt flag register 1 *//*1A */
4203  volatile PIER0_t PIER0; /*protocol interrupt enable register 0 *//*1C */
4204  volatile PIER1_t PIER1; /*protocol interrupt enable register 1 *//*1E */
4205  volatile CHIERFR_t CHIERFR; /*CHI error flag register *//*20 */
4206  volatile MBIVEC_t MBIVEC; /*message buffer interrupt vector register *//*22 */
4207  volatile CASERCR_t CASERCR; /*channel A status error counter register *//*24 */
4208  volatile CBSERCR_t CBSERCR; /*channel B status error counter register *//*26 */
4209  volatile PSR0_t PSR0; /*protocol status register 0 *//*28 */
4210  volatile PSR1_t PSR1; /*protocol status register 1 *//*2A */
4211  volatile PSR2_t PSR2; /*protocol status register 2 *//*2C */
4212  volatile PSR3_t PSR3; /*protocol status register 3 *//*2E */
4213  volatile MTCTR_t MTCTR; /*macrotick counter register *//*30 */
4214  volatile CYCTR_t CYCTR; /*cycle counter register *//*32 */
4215  volatile SLTCTAR_t SLTCTAR; /*slot counter channel A register *//*34 */
4216  volatile SLTCTBR_t SLTCTBR; /*slot counter channel B register *//*36 */
4217  volatile RTCORVR_t RTCORVR; /*rate correction value register *//*38 */
4218  volatile OFCORVR_t OFCORVR; /*offset correction value register *//*3A */
4219  volatile CIFRR_t CIFRR; /*combined interrupt flag register *//*3C */
4220  volatile SYMATOR_t SYMATOR; /*system memory acess time-out register *//*3E */
4221  volatile SFCNTR_t SFCNTR; /*sync frame counter register *//*40 */
4222  volatile SFTOR_t SFTOR; /*sync frame table offset register *//*42 */
4223  volatile SFTCCSR_t SFTCCSR; /*sync frame table configuration, control, status register *//*44 */
4224  volatile SFIDRFR_t SFIDRFR; /*sync frame ID rejection filter register *//*46 */
4225  volatile SFIDAFVR_t SFIDAFVR; /*sync frame ID acceptance filter value regiater *//*48 */
4226  volatile SFIDAFMR_t SFIDAFMR; /*sync frame ID acceptance filter mask register *//*4A */
4227  volatile NMVR_t NMVR[6]; /*network management vector registers (12 bytes) *//*4C */
4228  volatile NMVLR_t NMVLR; /*network management vector length register *//*58 */
4229  volatile TICCR_t TICCR; /*timer configuration and control register *//*5A */
4230  volatile TI1CYSR_t TI1CYSR; /*timer 1 cycle set register *//*5C */
4231  volatile T1MTOR_t T1MTOR; /*timer 1 macrotick offset register *//*5E */
4232  volatile TI2CR0_t TI2CR0; /*timer 2 configuration register 0 *//*60 */
4233  volatile TI2CR1_t TI2CR1; /*timer 2 configuration register 1 *//*62 */
4234  volatile SSSR_t SSSR; /*slot status selection register *//*64 */
4235  volatile SSCCR_t SSCCR; /*slot status counter condition register *//*66 */
4236  volatile SSR_t SSR[8]; /*slot status registers 0-7 *//*68 */
4237  volatile SSCR_t SSCR[4]; /*slot status counter registers 0-3 *//*78 */
4238  volatile MTSCFR_t MTSACFR; /*mts a config register *//*80 */
4239  volatile MTSCFR_t MTSBCFR; /*mts b config register *//*82 */
4240  volatile RSBIR_t RSBIR; /*receive shadow buffer index register *//*84 */
4241  volatile RFSR_t RFSR; /*receive fifo selection register *//*86 */
4242  volatile RFSIR_t RFSIR; /*receive fifo start index register *//*88 */
4243  volatile RFDSR_t RFDSR; /*receive fifo depth and size register *//*8A */
4244  volatile RFARIR_t RFARIR; /*receive fifo a read index register *//*8C */
4245  volatile RFBRIR_t RFBRIR; /*receive fifo b read index register *//*8E */
4246  volatile RFMIDAFVR_t RFMIDAFVR; /*receive fifo message ID acceptance filter value register *//*90 */
4247  volatile RFMIAFMR_t RFMIAFMR; /*receive fifo message ID acceptance filter mask register *//*92 */
4248  volatile RFFIDRFVR_t RFFIDRFVR; /*receive fifo frame ID rejection filter value register *//*94 */
4249  volatile RFFIDRFMR_t RFFIDRFMR; /*receive fifo frame ID rejection filter mask register *//*96 */
4250  volatile RFRFCFR_t RFRFCFR; /*receive fifo range filter configuration register *//*98 */
4251  volatile RFRFCTR_t RFRFCTR; /*receive fifo range filter control register *//*9A */
4252  volatile LDTXSLAR_t LDTXSLAR; /*last dynamic transmit slot channel A register *//*9C */
4253  volatile LDTXSLBR_t LDTXSLBR; /*last dynamic transmit slot channel B register *//*9E */
4254  volatile PCR0_t PCR0; /*protocol configuration register 0 *//*A0 */
4255  volatile PCR1_t PCR1; /*protocol configuration register 1 *//*A2 */
4256  volatile PCR2_t PCR2; /*protocol configuration register 2 *//*A4 */
4257  volatile PCR3_t PCR3; /*protocol configuration register 3 *//*A6 */
4258  volatile PCR4_t PCR4; /*protocol configuration register 4 *//*A8 */
4259  volatile PCR5_t PCR5; /*protocol configuration register 5 *//*AA */
4260  volatile PCR6_t PCR6; /*protocol configuration register 6 *//*AC */
4261  volatile PCR7_t PCR7; /*protocol configuration register 7 *//*AE */
4262  volatile PCR8_t PCR8; /*protocol configuration register 8 *//*B0 */
4263  volatile PCR9_t PCR9; /*protocol configuration register 9 *//*B2 */
4264  volatile PCR10_t PCR10; /*protocol configuration register 10 *//*B4 */
4265  volatile PCR11_t PCR11; /*protocol configuration register 11 *//*B6 */
4266  volatile PCR12_t PCR12; /*protocol configuration register 12 *//*B8 */
4267  volatile PCR13_t PCR13; /*protocol configuration register 13 *//*BA */
4268  volatile PCR14_t PCR14; /*protocol configuration register 14 *//*BC */
4269  volatile PCR15_t PCR15; /*protocol configuration register 15 *//*BE */
4270  volatile PCR16_t PCR16; /*protocol configuration register 16 *//*C0 */
4271  volatile PCR17_t PCR17; /*protocol configuration register 17 *//*C2 */
4272  volatile PCR18_t PCR18; /*protocol configuration register 18 *//*C4 */
4273  volatile PCR19_t PCR19; /*protocol configuration register 19 *//*C6 */
4274  volatile PCR20_t PCR20; /*protocol configuration register 20 *//*C8 */
4275  volatile PCR21_t PCR21; /*protocol configuration register 21 *//*CA */
4276  volatile PCR22_t PCR22; /*protocol configuration register 22 *//*CC */
4277  volatile PCR23_t PCR23; /*protocol configuration register 23 *//*CE */
4278  volatile PCR24_t PCR24; /*protocol configuration register 24 *//*D0 */
4279  volatile PCR25_t PCR25; /*protocol configuration register 25 *//*D2 */
4280  volatile PCR26_t PCR26; /*protocol configuration register 26 *//*D4 */
4281  volatile PCR27_t PCR27; /*protocol configuration register 27 *//*D6 */
4282  volatile PCR28_t PCR28; /*protocol configuration register 28 *//*D8 */
4283  volatile PCR29_t PCR29; /*protocol configuration register 29 *//*DA */
4284  volatile PCR30_t PCR30; /*protocol configuration register 30 *//*DC */
4285  uint16_t reserved3[17];
4286  volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */
4287  } FR_tag_t;
4288 
4289  typedef union uF_HEADER /* frame header */
4290  {
4291  struct {
4292  uint16_t:5;
4293  uint16_t HDCRC:11; /* Header CRC */
4294  uint16_t:2;
4295  uint16_t CYCCNT:6; /* Cycle Count */
4296  uint16_t:1;
4297  uint16_t PLDLEN:7; /* Payload Length */
4298  uint16_t:1;
4299  uint16_t PPI:1; /* Payload Preamble Indicator */
4300  uint16_t NUF:1; /* Null Frame Indicator */
4301  uint16_t SYF:1; /* Sync Frame Indicator */
4302  uint16_t SUF:1; /* Startup Frame Indicator */
4303  uint16_t FID:11; /* Frame ID */
4304  } B;
4305  uint16_t WORDS[3];
4306  } F_HEADER_t;
4307  typedef union uS_STSTUS /* slot status */
4308  {
4309  struct {
4310  uint16_t VFB:1; /* Valid Frame on channel B */
4311  uint16_t SYB:1; /* Sync Frame Indicator channel B */
4312  uint16_t NFB:1; /* Null Frame Indicator channel B */
4313  uint16_t SUB:1; /* Startup Frame Indicator channel B */
4314  uint16_t SEB:1; /* Syntax Error on channel B */
4315  uint16_t CEB:1; /* Content Error on channel B */
4316  uint16_t BVB:1; /* Boundary Violation on channel B */
4317  uint16_t CH:1; /* Channel */
4318  uint16_t VFA:1; /* Valid Frame on channel A */
4319  uint16_t SYA:1; /* Sync Frame Indicator channel A */
4320  uint16_t NFA:1; /* Null Frame Indicator channel A */
4321  uint16_t SUA:1; /* Startup Frame Indicator channel A */
4322  uint16_t SEA:1; /* Syntax Error on channel A */
4323  uint16_t CEA:1; /* Content Error on channel A */
4324  uint16_t BVA:1; /* Boundary Violation on channel A */
4325  uint16_t:1;
4326  } RX;
4327  struct {
4328  uint16_t VFB:1; /* Valid Frame on channel B */
4329  uint16_t SYB:1; /* Sync Frame Indicator channel B */
4330  uint16_t NFB:1; /* Null Frame Indicator channel B */
4331  uint16_t SUB:1; /* Startup Frame Indicator channel B */
4332  uint16_t SEB:1; /* Syntax Error on channel B */
4333  uint16_t CEB:1; /* Content Error on channel B */
4334  uint16_t BVB:1; /* Boundary Violation on channel B */
4335  uint16_t TCB:1; /* Tx Conflict on channel B */
4336  uint16_t VFA:1; /* Valid Frame on channel A */
4337  uint16_t SYA:1; /* Sync Frame Indicator channel A */
4338  uint16_t NFA:1; /* Null Frame Indicator channel A */
4339  uint16_t SUA:1; /* Startup Frame Indicator channel A */
4340  uint16_t SEA:1; /* Syntax Error on channel A */
4341  uint16_t CEA:1; /* Content Error on channel A */
4342  uint16_t BVA:1; /* Boundary Violation on channel A */
4343  uint16_t TCA:1; /* Tx Conflict on channel A */
4344  } TX;
4345  uint16_t R;
4346  } S_STATUS_t;
4347 
4348  typedef struct uMB_HEADER /* message buffer header */
4349  {
4350  F_HEADER_t FRAME_HEADER;
4351  uint16_t DATA_OFFSET;
4352  S_STATUS_t SLOT_STATUS;
4353  } MB_HEADER_t;
4354 /**************************************************************************/
4355 /* MODULE : FMPLL */
4356 /**************************************************************************/
4357  struct FMPLL_tag {
4358 
4359  uint32_t FMPLL_reserved0;
4360 
4361  union FMPLL_SYNSR_tag { /* Synthesiser Status Register */
4362  uint32_t R;
4363  struct {
4364  uint32_t:22;
4365  uint32_t LOLF:1;
4366  uint32_t LOC:1;
4367  uint32_t MODE:1;
4368  uint32_t PLLSEL:1;
4369  uint32_t PLLREF:1;
4370  uint32_t LOCKS:1;
4371  uint32_t LOCK:1;
4372  uint32_t LOCF:1;
4373  uint32_t CALDONE:1;
4374  uint32_t CALPASS:1;
4375  } B;
4376  } SYNSR;
4377 
4378  union FMPLL_ESYNCR1_tag {
4379  uint32_t R;
4380  struct {
4381  uint32_t:1;
4382  uint32_t CLKCFG:3;
4383  uint32_t:8;
4384  uint32_t EPREDIV:4;
4385  uint32_t:8;
4386  uint32_t EMFD:8;
4387  } B;
4388  } ESYNCR1;
4389 
4390  union FMPLL_ESYNCR2_tag {
4391  uint32_t R;
4392  struct {
4393  uint32_t:8;
4394  uint32_t LOCEN:1;
4395  uint32_t LOLRE:1;
4396  uint32_t LOCRE:1;
4397  uint32_t LOLIRQ:1;
4398  uint32_t LOCIRQ:1;
4399  uint32_t:1;
4400  uint32_t ERATE:2;
4401  uint32_t:5;
4402  uint32_t EDEPTH:3;
4403  uint32_t:2;
4404  uint32_t ERFD:6;
4405  } B;
4406  } ESYNCR2;
4407 
4408  };
4409 /*************************************************************************/
4410 /* MODULE : i2c */
4411 /*************************************************************************/
4412  struct I2C_tag {
4413  union {
4414  uint8_t R;
4415  struct {
4416  uint8_t AD:7;
4417  uint8_t:1;
4418  } B;
4419  } IBAD; /* Module Bus Address Register */
4420 
4421  union {
4422  uint8_t R;
4423  struct {
4424  uint8_t MULT:2;
4425  uint8_t ICR:6;
4426  } B;
4427  } IBFD; /* Module Bus Frequency Register */
4428 
4429  union {
4430  uint8_t R;
4431  struct {
4432  uint8_t MDIS:1;
4433  uint8_t IBIE:1;
4434  uint8_t MS:1;
4435  uint8_t TX:1;
4436  uint8_t NOACK:1;
4437  uint8_t RSTA:1;
4438  uint8_t DMAEN:1;
4439  uint8_t:1;
4440  } B;
4441  } IBCR; /* Module Bus Control Register */
4442 
4443  union {
4444  uint8_t R;
4445  struct {
4446  uint8_t TCF:1;
4447  uint8_t IAAS:1;
4448  uint8_t IBB:1;
4449  uint8_t IBAL:1;
4450  uint8_t:1;
4451  uint8_t SRW:1;
4452  uint8_t IBIF:1;
4453  uint8_t RXAK:1;
4454  } B;
4455  } IBSR; /* Module Status Register */
4456 
4457  union {
4458  uint8_t R;
4459  struct {
4460  uint8_t DATA:8;
4461  } B;
4462  } IBDR; /* Module Data Register */
4463 
4464  union {
4465  uint8_t R;
4466  struct {
4467  uint8_t BIIE:1;
4468  uint8_t:7;
4469  } B;
4470  } IBIC; /* Module Interrupt Configuration Register */
4471 
4472  }; /* end of i2c_tag */
4473 /*************************************************************************/
4474 /* MODULE : INTC */
4475 /*************************************************************************/
4476  struct INTC_tag {
4477  union {
4478  uint32_t R;
4479  struct {
4480  uint32_t:18;
4481  uint32_t VTES_PRC1:1;
4482  uint32_t:4;
4483  uint32_t HVEN_PRC1:1;
4484  uint32_t:2;
4485  uint32_t VTES:1;
4486  uint32_t:4;
4487  uint32_t HVEN:1;
4488  } B;
4489  } MCR; /* Module Configuration Register */
4490 
4491  int32_t INTC_reserved1;
4492 
4493  union {
4494  uint32_t R;
4495  struct {
4496  uint32_t:28;
4497  uint32_t PRI:4;
4498  } B;
4499  } CPR; /* Processor 0 (Z6) Current Priority Register */
4500 
4501  union {
4502  uint32_t R;
4503  struct {
4504  uint32_t:28;
4505  uint32_t PRI:4;
4506  } B;
4507  } CPR_PRC1; /* Processor 1 (Z0) Current Priority Register */
4508 
4509  union {
4510  uint32_t R;
4511  struct {
4512  uint32_t VTBA:21;
4513  uint32_t INTVEC:9;
4514  uint32_t:2;
4515  } B;
4516  } IACKR; /* Processor 0 (Z6) Interrupt Acknowledge Register */
4517 
4518  union {
4519  uint32_t R;
4520  struct {
4521  uint32_t VTBA_PRC1:21;
4522  uint32_t INTVEC_PRC1:9;
4523  uint32_t:2;
4524  } B;
4525  } IACKR_PRC1; /* Processor 1 (Z0) Interrupt Acknowledge Register */
4526 
4527  union {
4528  uint32_t R;
4529  struct {
4530  uint32_t:32;
4531  } B;
4532  } EOIR; /* Processor 0 End of Interrupt Register */
4533 
4534  union {
4535  uint32_t R;
4536  struct {
4537  uint32_t:32;
4538  } B;
4539  } EOIR_PRC1; /* Processor 1 End of Interrupt Register */
4540 
4541  union {
4542  uint8_t R;
4543  struct {
4544  uint8_t:6;
4545  uint8_t SET:1;
4546  uint8_t CLR:1;
4547  } B;
4548  } SSCIR[8]; /* Software Set/Clear Interruput Register */
4549 
4550  uint32_t intc_reserved2[6];
4551 
4552  union {
4553  uint8_t R;
4554  struct {
4555  uint8_t PRC_SEL:2;
4556  uint8_t:2;
4557  uint8_t PRI:4;
4558  } B;
4559  } PSR[316]; /* Software Set/Clear Interrupt Register */
4560 
4561  }; /* end of INTC_tag */
4562 /*************************************************************************/
4563 /* MODULE : MLB */
4564 /*************************************************************************/
4565  struct MLB_tag {
4566 
4567  union {
4568  uint32_t R;
4569  struct {
4570  uint32_t MDE:1;
4571  uint32_t LBM:1;
4572  uint32_t MCS:2;
4573  uint32_t:1;
4574  uint32_t MLK:1;
4575  uint32_t MLE:1;
4576  uint32_t MHRE:1;
4577  uint32_t MRS:1;
4578  uint32_t:15;
4579  uint32_t MDA:8;
4580  } B;
4581  } DCCR; /* Device Control Configuration Register */
4582 
4583  union {
4584  uint32_t R;
4585  struct {
4586  uint32_t:24;
4587  uint32_t SSRE:1;
4588  uint32_t SDMU:1;
4589  uint32_t SDML:1;
4590  uint32_t SDSC:1;
4591  uint32_t SDCS:1;
4592  uint32_t SDNU:1;
4593  uint32_t SDNL:1;
4594  uint32_t SDR:1;
4595  } B;
4596  } SSCR; /* MLB Blank Register */
4597 
4598  union {
4599  uint32_t R;
4600  struct {
4601  uint32_t MSD:32;
4602  } B;
4603  } SDCR; /* MLB Status Register */
4604 
4605  union {
4606  uint32_t R;
4607  struct {
4608  uint32_t:25;
4609  uint32_t SMMU:1;
4610  uint32_t SMML:1;
4611  uint32_t SMSC:1;
4612  uint32_t SMCS:1;
4613  uint32_t SMNU:1;
4614  uint32_t SMNL:1;
4615  uint32_t SMR:1;
4616  } B;
4617  } SMCR; /* RX Control Channel Address Register */
4618 
4619  uint32_t MLB_reserved1[3];
4620 
4621  union {
4622  uint32_t R;
4623  struct {
4624  uint32_t UMA:8;
4625  uint32_t UMI:8;
4626  uint32_t MMA:8;
4627  uint32_t MMI:8;
4628  } B;
4629  } VCCR; /* Version Control Configuration Register */
4630 
4631  union {
4632  uint32_t R;
4633  struct {
4634  uint32_t SRBA:16;
4635  uint32_t STBA:16;
4636  } B;
4637  } SBCR; /* Sync Base Address Config Register */
4638 
4639  union {
4640  uint32_t R;
4641  struct {
4642  uint32_t ARBA:16;
4643  uint32_t ATBA:16;
4644  } B;
4645  } ABCR; /* Async Base Address Channel Config Register */
4646 
4647  union {
4648  uint32_t R;
4649  struct {
4650  uint32_t CRBA:16;
4651  uint32_t CTBA:16;
4652  } B;
4653  } CBCR; /* Control Base Address Config Register */
4654 
4655  union {
4656  uint32_t R;
4657  struct {
4658  uint32_t IRBA:16;
4659  uint32_t ITBA:16;
4660  } B;
4661  } IBCR; /* Isochronous Base Address Config Register */
4662 
4663  union {
4664  uint32_t R;
4665  struct {
4666  uint32_t:16;
4667  uint32_t CSU:16;
4668  } B;
4669  } CICR; /* Channel Interrupt Config Register */
4670 
4671  uint32_t MLB_reserved2[3];
4672 
4673  struct mlbch_t {
4674 
4675  union {
4676  uint32_t R;
4677  struct {
4678  uint32_t CE:1;
4679  uint32_t TR:1;
4680  uint32_t CT:2;
4681  uint32_t FSE_FCE:1;
4682  uint32_t MDS:2;
4683  uint32_t:2;
4684  uint32_t MLFS:1;
4685  uint32_t:1;
4686  uint32_t MBE:1;
4687  uint32_t MBS:1;
4688  uint32_t MBD:1;
4689  uint32_t MDB:1;
4690  uint32_t MPE:1;
4691  uint32_t FSCD_IPL:1;
4692  uint32_t IPL:2;
4693  uint32_t FSPC_IPL:5;
4694  uint32_t CA:8;
4695  } B;
4696  } CECR; /* Channel Entry Config Register */
4697 
4698  union {
4699  uint32_t R;
4700  struct {
4701  uint32_t BM:1;
4702  uint32_t BF:1;
4703  uint32_t:10;
4704  uint32_t IVB:2;
4705  uint32_t GIRB_GB:1;
4706  uint32_t RDY:1;
4707  uint32_t:4;
4708  uint32_t PBS:1;
4709  uint32_t PBD:1;
4710  uint32_t PBDB:1;
4711  uint32_t PBPE:1;
4712  uint32_t:1;
4713  uint32_t LFS:1;
4714  uint32_t HBE:1;
4715  uint32_t BE:1;
4716  uint32_t CBS:1;
4717  uint32_t CBD:1;
4718  uint32_t CBDB:1;
4719  uint32_t CBPE:1;
4720  } B;
4721  } CSCR; /* Channel Status Config Register */
4722 
4723  union {
4724  uint32_t R;
4725  struct {
4726  uint32_t BCA:16;
4727  uint32_t BFA:16;
4728  } B;
4729  } CCBCR; /* Channel Current Buffer Config Register */
4730 
4731  union {
4732  uint32_t R;
4733  struct {
4734  uint32_t BSA:16;
4735  uint32_t BEA:16;
4736  } B;
4737  } CNBCR; /* Channel Next Buffer Config Register */
4738 
4739  } CH[16];
4740 
4741  uint32_t MLB_reserved3[80];
4742 
4743  union {
4744  uint32_t R;
4745  struct {
4746  uint32_t BSA:16;
4747  uint32_t BEA:16;
4748  } B;
4749  } LCBCR[16]; /* Local Channel Buffer Config Register */
4750 
4751  }; /* end of MLB_tag */
4752 /*************************************************************************/
4753 /* MODULE : MPU */
4754 /*************************************************************************/
4755  struct MPU_tag {
4756  union {
4757  uint32_t R;
4758  struct {
4759  uint32_t MPERR:8;
4760  uint32_t:4;
4761  uint32_t HRL:4;
4762  uint32_t NSP:4;
4763  uint32_t NGRD:4;
4764  uint32_t:7;
4765  uint32_t VLD:1;
4766  } B;
4767  } CESR; /* Module Control/Error Status Register */
4768 
4769  uint32_t mpu_reserved1[3];
4770 
4771  union {
4772  uint32_t R;
4773  struct {
4774  uint32_t EADDR:32;
4775  } B;
4776  } EAR0; /* Error Address Register */
4777 
4778  union {
4779  uint32_t R;
4780  struct {
4781  uint32_t EACD:16;
4782  uint32_t EPID:8;
4783  uint32_t EMN:4;
4784  uint32_t EATTR:3;
4785  uint32_t ERW:1;
4786  } B;
4787  } EDR0; /* Error Detail Register */
4788 
4789  union {
4790  uint32_t R;
4791  struct {
4792  uint32_t EADDR:32;
4793  } B;
4794  } EAR1;
4795 
4796  union {
4797  uint32_t R;
4798  struct {
4799  uint32_t EACD:16;
4800  uint32_t EPID:8;
4801  uint32_t EMN:4;
4802  uint32_t EATTR:3;
4803  uint32_t ERW:1;
4804  } B;
4805  } EDR1;
4806 
4807  union {
4808  uint32_t R;
4809  struct {
4810  uint32_t EADDR:32;
4811  } B;
4812  } EAR2;
4813 
4814  union {
4815  uint32_t R;
4816  struct {
4817  uint32_t EACD:16;
4818  uint32_t EPID:8;
4819  uint32_t EMN:4;
4820  uint32_t EATTR:3;
4821  uint32_t ERW:1;
4822  } B;
4823  } EDR3;
4824 
4825  union {
4826  uint32_t R;
4827  struct {
4828  uint32_t EADDR:32;
4829  } B;
4830  } EAR3;
4831 
4832  union {
4833  uint32_t R;
4834  struct {
4835  uint32_t EACD:16;
4836  uint32_t EPID:8;
4837  uint32_t EMN:4;
4838  uint32_t EATTR:3;
4839  uint32_t ERW:1;
4840  } B;
4841  } EDR2;
4842 
4843  uint32_t mpu_reserved2[244];
4844 
4845  struct {
4846  union {
4847  uint32_t R;
4848  struct {
4849  uint32_t SRTADDR:27;
4850  uint32_t:5;
4851  } B;
4852  } WORD0; /* Region Descriptor n Word 0 */
4853 
4854  union {
4855  uint32_t R;
4856  struct {
4857  uint32_t ENDADDR:27;
4858  uint32_t:5;
4859  } B;
4860  } WORD1; /* Region Descriptor n Word 1 */
4861 
4862  union {
4863  uint32_t R;
4864  struct {
4865  uint32_t:2;
4866  uint32_t M6RE:1;
4867  uint32_t M6WE:1;
4868  uint32_t M5RE:1;
4869  uint32_t M5WE:1;
4870  uint32_t M4RE:1;
4871  uint32_t M4WE:1;
4872  uint32_t:6;
4873  uint32_t M2PE:1;
4874  uint32_t M2SM:2;
4875  uint32_t M2UM:3;
4876  uint32_t M1PE:1;
4877  uint32_t M1SM:2;
4878  uint32_t M1UM:3;
4879  uint32_t M0PE:1;
4880  uint32_t M0SM:2;
4881  uint32_t M0UM:3;
4882  } B;
4883  } WORD2; /* Region Descriptor n Word 2 */
4884 
4885  union {
4886  uint32_t R;
4887  struct {
4888  uint32_t PID:8;
4889  uint32_t PIDMASK:8;
4890  uint32_t:15;
4891  uint32_t VLD:1;
4892  } B;
4893  } WORD3; /* Region Descriptor n Word 3 */
4894 
4895  } RGD[16];
4896 
4897  uint32_t mpu_reserved3[192];
4898 
4899  union {
4900  uint32_t R;
4901  struct {
4902  uint32_t:2;
4903  uint32_t M6RE:1;
4904  uint32_t M6WE:1;
4905  uint32_t M5RE:1;
4906  uint32_t M5WE:1;
4907  uint32_t M4RE:1;
4908  uint32_t M4WE:1;
4909  uint32_t:6;
4910  uint32_t M2PE:1;
4911  uint32_t M2SM:2;
4912  uint32_t M2UM:3;
4913  uint32_t M1PE:1;
4914  uint32_t M1SM:2;
4915  uint32_t M1UM:3;
4916  uint32_t M0PE:1;
4917  uint32_t M0SM:2;
4918  uint32_t M0UM:3;
4919  } B;
4920  } RGDAAC[16]; /* Region Descriptor Alternate Access Control n */
4921  };
4922 /**************************************************************************/
4923 /* MODULE : pit */
4924 /**************************************************************************/
4925  struct PIT_tag {
4926 
4927  union PIT_MCR_tag {
4928  uint32_t R;
4929  struct {
4930  uint32_t:30;
4931  uint32_t MDIS:1;
4932  uint32_t FRZ:1;
4933  } B;
4934  } PITMCR;
4935 
4936  uint32_t pit_reserved1[59];
4937 
4938  struct PIT_CHANNEL_tag {
4939  union {
4940  uint32_t R;
4941  struct {
4942  uint32_t TSV:32;
4943  } B;
4944  } LDVAL;
4945 
4946  union {
4947  uint32_t R;
4948  struct {
4949  uint32_t TVL:32;
4950  } B;
4951  } CVAL;
4952 
4953  union PIT_TCTRL_tag {
4954  uint32_t R;
4955  struct {
4956  uint32_t:30;
4957  uint32_t TIE:1;
4958  uint32_t TEN:1;
4959  } B;
4960  } TCTRL;
4961 
4962  union PIT_TFLG_tag {
4963  uint32_t R;
4964  struct {
4965  uint32_t:31;
4966  uint32_t TIF:1;
4967  } B;
4968  } TFLG;
4969  } CHANNEL[9];
4970  };
4971 
4972  /* Compatibility with MPC5643L */
4973  typedef struct PIT_CHANNEL_tag PIT_RTI_CHANNEL_tag;
4974  typedef union PIT_MCR_tag PIT_RTI_PITMCR_32B_tag;
4975  typedef union PIT_TCTRL_tag PIT_RTI_TCTRL_32B_tag;
4976  typedef union PIT_TFLG_tag PIT_RTI_TFLG_32B_tag;
4977 /**************************************************************************/
4978 /* MODULE : sem4 */
4979 /**************************************************************************/
4980  struct SEMA4_tag {
4981  union {
4982  uint8_t R;
4983  struct {
4984  uint8_t:6;
4985  uint8_t GTFSM:2;
4986  } B;
4987  } GATE[16]; /* Gate n Register */
4988 
4989  uint32_t sema4_reserved1[12]; /* {0x40-0x10}/4 = 0x0C */
4990 
4991  union {
4992  uint16_t R;
4993  struct {
4994  uint16_t INE0:1;
4995  uint16_t INE1:1;
4996  uint16_t INE2:1;
4997  uint16_t INE3:1;
4998  uint16_t INE4:1;
4999  uint16_t INE5:1;
5000  uint16_t INE6:1;
5001  uint16_t INE7:1;
5002  uint16_t INE8:1;
5003  uint16_t INE9:1;
5004  uint16_t INE10:1;
5005  uint16_t INE11:1;
5006  uint16_t INE12:1;
5007  uint16_t INE13:1;
5008  uint16_t INE14:1;
5009  uint16_t INE15:1;
5010  } B;
5011  } CP0INE;
5012 
5013  uint16_t sema4_reserved2[3]; /* {0x48-0x42}/2 = 0x03 */
5014 
5015  union {
5016  uint16_t R;
5017  struct {
5018  uint16_t INE0:1;
5019  uint16_t INE1:1;
5020  uint16_t INE2:1;
5021  uint16_t INE3:1;
5022  uint16_t INE4:1;
5023  uint16_t INE5:1;
5024  uint16_t INE6:1;
5025  uint16_t INE7:1;
5026  uint16_t INE8:1;
5027  uint16_t INE9:1;
5028  uint16_t INE10:1;
5029  uint16_t INE11:1;
5030  uint16_t INE12:1;
5031  uint16_t INE13:1;
5032  uint16_t INE14:1;
5033  uint16_t INE15:1;
5034  } B;
5035  } CP1INE;
5036 
5037  uint16_t sema4_reserved3[27]; /* {0x80-0x4A}/2 = 0x1B */
5038 
5039  union {
5040  uint16_t R;
5041  struct {
5042  uint16_t GN0:1;
5043  uint16_t GN1:1;
5044  uint16_t GN2:1;
5045  uint16_t GN3:1;
5046  uint16_t GN4:1;
5047  uint16_t GN5:1;
5048  uint16_t GN6:1;
5049  uint16_t GN7:1;
5050  uint16_t GN8:1;
5051  uint16_t GN9:1;
5052  uint16_t GN10:1;
5053  uint16_t GN11:1;
5054  uint16_t GN12:1;
5055  uint16_t GN13:1;
5056  uint16_t GN14:1;
5057  uint16_t GN15:1;
5058  } B;
5059  } CP0NTF;
5060 
5061  uint16_t sema4_reserved4[3]; /* {0x88-0x82}/2 = 0x03 */
5062 
5063  union {
5064  uint16_t R;
5065  struct {
5066  uint16_t GN0:1;
5067  uint16_t GN1:1;
5068  uint16_t GN2:1;
5069  uint16_t GN3:1;
5070  uint16_t GN4:1;
5071  uint16_t GN5:1;
5072  uint16_t GN6:1;
5073  uint16_t GN7:1;
5074  uint16_t GN8:1;
5075  uint16_t GN9:1;
5076  uint16_t GN10:1;
5077  uint16_t GN11:1;
5078  uint16_t GN12:1;
5079  uint16_t GN13:1;
5080  uint16_t GN14:1;
5081  uint16_t GN15:1;
5082  } B;
5083  } CP1NTF;
5084 
5085  uint16_t sema4_reserved5[59]; /* {0x100-0x8A}/2 = 0x3B */
5086 
5087  union {
5088  uint16_t R;
5089  struct {
5090  uint16_t:2;
5091  uint16_t RSTGSM:2;
5092  uint16_t:1;
5093  uint16_t RSTGMS:3;
5094  uint16_t RSTGTN:8;
5095  } B;
5096  } RSTGT;
5097 
5098  uint16_t sema4_reserved6;
5099 
5100  union {
5101  uint16_t R;
5102  struct {
5103  uint16_t:2;
5104  uint16_t RSTNSM:2;
5105  uint16_t:1;
5106  uint16_t RSTNMS:3;
5107  uint16_t RSTNTN:8;
5108  } B;
5109  } RSTNTF;
5110  };
5111 /*************************************************************************/
5112 /* MODULE : SIU */
5113 /*************************************************************************/
5114  struct SIU_tag {
5115 
5116  int32_t SIU_reserved0;
5117 
5118  union {
5119  uint32_t R;
5120  struct {
5121  uint32_t PARTNUM:16;
5122  uint32_t CSP:1;
5123  uint32_t PKG:5;
5124  uint32_t:2;
5125  uint32_t MASKNUM_MAJOR:4;
5126  uint32_t MASKNUM_MINOR:4;
5127  } B;
5128  } MIDR; /* MCU ID Register */
5129 
5130  int32_t SIU_reserved1;
5131 
5132  union {
5133  uint32_t R;
5134  struct {
5135  uint32_t PORS:1;
5136  uint32_t ERS:1;
5137  uint32_t LLRS:1;
5138  uint32_t LCRS:1;
5139  uint32_t WDRS:1;
5140  uint32_t CRS:1;
5141  uint32_t:8;
5142  uint32_t SSRS:1;
5143  uint32_t:15;
5144  uint32_t BOOTCFG:1;
5145  uint32_t:1;
5146  } B;
5147  } RSR; /* Reset Status Register */
5148 
5149  union {
5150  uint32_t R;
5151  struct {
5152  uint32_t SSR:1;
5153  uint32_t:15;
5154  uint32_t CRE0:1;
5155  uint32_t CRE1:1;
5156  uint32_t:6;
5157  uint32_t SSRL:1;
5158  uint32_t:7;
5159  } B;
5160  } SRCR; /* System Reset Control Register */
5161 
5162  union {
5163  uint32_t R;
5164  struct {
5165  uint32_t NMI0:1;
5166  uint32_t NMI1:1;
5167  uint32_t:14;
5168  uint32_t EIF15:1;
5169  uint32_t EIF14:1;
5170  uint32_t EIF13:1;
5171  uint32_t EIF12:1;
5172  uint32_t EIF11:1;
5173  uint32_t EIF10:1;
5174  uint32_t EIF9:1;
5175  uint32_t EIF8:1;
5176  uint32_t EIF7:1;
5177  uint32_t EIF6:1;
5178  uint32_t EIF5:1;
5179  uint32_t EIF4:1;
5180  uint32_t EIF3:1;
5181  uint32_t EIF2:1;
5182  uint32_t EIF1:1;
5183  uint32_t EIF0:1;
5184  } B;
5185  } EISR; /* External Interrupt Status Register */
5186 
5187  union SIU_DIRER_tag {
5188  uint32_t R;
5189  struct {
5190  uint32_t:16;
5191  uint32_t EIRE15:1;
5192  uint32_t EIRE14:1;
5193  uint32_t EIRE13:1;
5194  uint32_t EIRE12:1;
5195  uint32_t EIRE11:1;
5196  uint32_t EIRE10:1;
5197  uint32_t EIRE9:1;
5198  uint32_t EIRE8:1;
5199  uint32_t EIRE7:1;
5200  uint32_t EIRE6:1;
5201  uint32_t EIRE5:1;
5202  uint32_t EIRE4:1;
5203  uint32_t EIRE3:1;
5204  uint32_t EIRE2:1;
5205  uint32_t EIRE1:1;
5206  uint32_t EIRE0:1;
5207  } B;
5208  } DIRER; /* DMA/Interrupt Request Enable Register */
5209 
5210  union SIU_DIRSR_tag {
5211  uint32_t R;
5212  struct {
5213  uint32_t:30;
5214  uint32_t DIRS1:1;
5215  uint32_t DIRS0:1;
5216  } B;
5217  } DIRSR; /* DMA/Interrupt Select Register */
5218 
5219  union {
5220  uint32_t R;
5221  struct {
5222  uint32_t:16;
5223  uint32_t OVF15:1;
5224  uint32_t OVF14:1;
5225  uint32_t OVF13:1;
5226  uint32_t OVF12:1;
5227  uint32_t OVF11:1;
5228  uint32_t OVF10:1;
5229  uint32_t OVF9:1;
5230  uint32_t OVF8:1;
5231  uint32_t OVF7:1;
5232  uint32_t OVF6:1;
5233  uint32_t OVF5:1;
5234  uint32_t OVF4:1;
5235  uint32_t OVF3:1;
5236  uint32_t OVF2:1;
5237  uint32_t OVF1:1;
5238  uint32_t OVF0:1;
5239  } B;
5240  } OSR; /* Overrun Status Register */
5241 
5242  union SIU_ORER_tag {
5243  uint32_t R;
5244  struct {
5245  uint32_t:16;
5246  uint32_t ORE15:1;
5247  uint32_t ORE14:1;
5248  uint32_t ORE13:1;
5249  uint32_t ORE12:1;
5250  uint32_t ORE11:1;
5251  uint32_t ORE10:1;
5252  uint32_t ORE9:1;
5253  uint32_t ORE8:1;
5254  uint32_t ORE7:1;
5255  uint32_t ORE6:1;
5256  uint32_t ORE5:1;
5257  uint32_t ORE4:1;
5258  uint32_t ORE3:1;
5259  uint32_t ORE2:1;
5260  uint32_t ORE1:1;
5261  uint32_t ORE0:1;
5262  } B;
5263  } ORER; /* Overrun Request Enable Register */
5264 
5265  union SIU_IREER_tag {
5266  uint32_t R;
5267  struct {
5268  uint32_t NREE0:1;
5269  uint32_t NREE1:1;
5270  uint32_t:14;
5271  uint32_t IREE15:1;
5272  uint32_t IREE14:1;
5273  uint32_t IREE13:1;
5274  uint32_t IREE12:1;
5275  uint32_t IREE11:1;
5276  uint32_t IREE10:1;
5277  uint32_t IREE9:1;
5278  uint32_t IREE8:1;
5279  uint32_t IREE7:1;
5280  uint32_t IREE6:1;
5281  uint32_t IREE5:1;
5282  uint32_t IREE4:1;
5283  uint32_t IREE3:1;
5284  uint32_t IREE2:1;
5285  uint32_t IREE1:1;
5286  uint32_t IREE0:1;
5287  } B;
5288  } IREER; /* External IRQ Rising-Edge Event Enable Register */
5289 
5290  union SIU_IFEER_tag {
5291  uint32_t R;
5292  struct {
5293  uint32_t NFEE0:1;
5294  uint32_t NFEE1:1;
5295  uint32_t:14;
5296  uint32_t IFEE15:1;
5297  uint32_t IFEE14:1;
5298  uint32_t IFEE13:1;
5299  uint32_t IFEE12:1;
5300  uint32_t IFEE11:1;
5301  uint32_t IFEE10:1;
5302  uint32_t IFEE9:1;
5303  uint32_t IFEE8:1;
5304  uint32_t IFEE7:1;
5305  uint32_t IFEE6:1;
5306  uint32_t IFEE5:1;
5307  uint32_t IFEE4:1;
5308  uint32_t IFEE3:1;
5309  uint32_t IFEE2:1;
5310  uint32_t IFEE1:1;
5311  uint32_t IFEE0:1;
5312  } B;
5313  } IFEER; /* External IRQ Falling-Edge Event Enable Register */
5314 
5315  union SIU_IDFR_tag {
5316  uint32_t R;
5317  struct {
5318  uint32_t:28;
5319  uint32_t DFL:4;
5320  } B;
5321  } IDFR; /* External IRQ Digital Filter Register */
5322 
5323  union {
5324  uint32_t R;
5325  struct {
5326  uint32_t FNMI0:1;
5327  uint32_t FNMI1:1;
5328  uint32_t:14;
5329  uint32_t FI15:1;
5330  uint32_t FI14:1;
5331  uint32_t FI13:1;
5332  uint32_t FI12:1;
5333  uint32_t FI11:1;
5334  uint32_t FI10:1;
5335  uint32_t FI9:1;
5336  uint32_t FI8:1;
5337  uint32_t FI7:1;
5338  uint32_t FI6:1;
5339  uint32_t FI5:1;
5340  uint32_t FI4:1;
5341  uint32_t FI3:1;
5342  uint32_t FI2:1;
5343  uint32_t FI1:1;
5344  uint32_t FI0:1;
5345  } B;
5346  } IFIR; /* External IRQ Filtered Input Register */
5347 
5348  int32_t SIU_reserved2[2];
5349 
5350  union SIU_PCR_tag {
5351  uint16_t R;
5352  struct {
5353  uint16_t:4;
5354  uint16_t PA:2;
5355  uint16_t OBE:1;
5356  uint16_t IBE:1;
5357  uint16_t DSC:2;
5358  uint16_t ODE:1;
5359  uint16_t HYS:1;
5360  uint16_t SRC:2;
5361  uint16_t WPE:1;
5362  uint16_t WPS:1;
5363  } B;
5364  } PCR[155]; /* Pad Configuration Registers */
5365 
5366  int32_t SIU_reserved3[290];
5367 
5368  union {
5369  uint8_t R;
5370  struct {
5371  uint8_t:7;
5372  uint8_t PDO:1;
5373  } B;
5374  } GPDO[155]; /* GPIO Pin Data Output Registers */
5375 
5376  int8_t SIU_reserved4[357];
5377 
5378  union {
5379  uint8_t R;
5380  struct {
5381  uint8_t:7;
5382  uint8_t PDI:1;
5383  } B;
5384  } GPDI[155]; /* GPIO Pin Data Input Registers */
5385 
5386  int32_t SIU_reserved5[26];
5387 
5388  union {
5389  uint32_t R;
5390  struct {
5391  uint32_t ESEL15:2;
5392  uint32_t ESEL14:2;
5393  uint32_t ESEL13:2;
5394  uint32_t ESEL12:2;
5395  uint32_t ESEL11:2;
5396  uint32_t ESEL10:2;
5397  uint32_t ESEL9:2;
5398  uint32_t ESEL8:2;
5399  uint32_t ESEL7:2;
5400  uint32_t ESEL6:2;
5401  uint32_t ESEL5:2;
5402  uint32_t ESEL4:2;
5403  uint32_t ESEL3:2;
5404  uint32_t ESEL2:2;
5405  uint32_t ESEL1:2;
5406  uint32_t ESEL0:2;
5407  } B;
5408  } ISEL1; /* IMUX Register */
5409 
5410  union {
5411  uint32_t R;
5412  struct {
5413  uint32_t ESEL15:2;
5414  uint32_t ESEL14:2;
5415  uint32_t ESEL13:2;
5416  uint32_t ESEL12:2;
5417  uint32_t ESEL11:2;
5418  uint32_t ESEL10:2;
5419  uint32_t ESEL9:2;
5420  uint32_t ESEL8:2;
5421  uint32_t ESEL7:2;
5422  uint32_t ESEL6:2;
5423  uint32_t ESEL5:2;
5424  uint32_t ESEL4:2;
5425  uint32_t ESEL3:2;
5426  uint32_t ESEL2:2;
5427  uint32_t ESEL1:2;
5428  uint32_t ESEL0:2;
5429  } B;
5430  } ISEL2; /* IMUX Register */
5431 
5432  int32_t SIU_reserved6;
5433 
5434  union {
5435  uint32_t R;
5436  struct {
5437  uint32_t:17;
5438  uint32_t TSEL1:7;
5439  uint32_t:1;
5440  uint32_t TSEL0:7;
5441  } B;
5442  } ISEL4; /* IMUX Register */
5443 
5444  int32_t SIU_reserved7[27];
5445 
5446  union {
5447  uint32_t R;
5448  struct {
5449  uint32_t:14;
5450  uint32_t MATCH:1;
5451  uint32_t DISNEX:1;
5452  uint32_t:8;
5453  uint32_t TESTLOCK:1;
5454  uint32_t:7;
5455  } B;
5456  } CCR; /* Chip Configuration Register Register */
5457 
5458  union {
5459  uint32_t R;
5460  struct {
5461  uint32_t:28;
5462  uint32_t ECEN:1;
5463  uint32_t:1;
5464  uint32_t ECDF:2;
5465  } B;
5466  } ECCR; /* External Clock Configuration Register Register */
5467 
5468  union {
5469  uint32_t R;
5470  } GPR0; /* General Purpose Register 0 */
5471 
5472  union {
5473  uint32_t R;
5474  } GPR1; /* General Purpose Register 1 */
5475 
5476  union {
5477  uint32_t R;
5478  } GPR2; /* General Purpose Register 2 */
5479 
5480  union {
5481  uint32_t R;
5482  } GPR3; /* General Purpose Register 3 */
5483 
5484  int32_t SIU_reserved8[2];
5485 
5486  union {
5487  uint32_t R;
5488  struct {
5489  uint32_t SYSCLKSEL:2;
5490  uint32_t SYSCLKDIV:3;
5491  uint32_t:19;
5492  uint32_t LPCLKDIV3:2;
5493  uint32_t LPCLKDIV2:2;
5494  uint32_t LPCLKDIV1:2;
5495  uint32_t LPCLKDIV0:2;
5496  } B;
5497  } SYSCLK; /* System CLock Register */
5498 
5499  union {
5500  uint32_t R;
5501  struct {
5502  uint32_t:6;
5503  uint32_t HLT6:1;
5504  uint32_t HLT7:1;
5505  uint32_t:1;
5506  uint32_t HLT9:1;
5507  uint32_t HLT10:1;
5508  uint32_t HLT11:1;
5509  uint32_t HLT12:1;
5510  uint32_t HLT13:1;
5511  uint32_t HLT14:1;
5512  uint32_t HLT15:1;
5513  uint32_t HLT16:1;
5514  uint32_t HLT17:1;
5515  uint32_t HLT18:1;
5516  uint32_t HLT19:1;
5517  uint32_t HLT20:1;
5518  uint32_t HLT21:1;
5519  uint32_t HLT22:1;
5520  uint32_t HLT23:1;
5521  uint32_t:2;
5522  uint32_t HLT26:1;
5523  uint32_t HLT27:1;
5524  uint32_t HLT28:1;
5525  uint32_t HLT29:1;
5526  uint32_t:1;
5527  uint32_t HLT31:1;
5528  } B;
5529  } HLT0; /* Halt Register 0 */
5530 
5531  union {
5532  uint32_t R;
5533  struct {
5534  uint32_t:3;
5535  uint32_t HLT3:1;
5536  uint32_t HLT4:1;
5537  uint32_t:15;
5538  uint32_t HLT20:1;
5539  uint32_t HLT21:1;
5540  uint32_t HLT22:1;
5541  uint32_t HLT23:1;
5542  uint32_t:2;
5543  uint32_t HLT26:1;
5544  uint32_t HLT27:1;
5545  uint32_t HLT28:1;
5546  uint32_t HLT29:1;
5547  uint32_t:2;
5548  } B;
5549  } HLT1; /* Halt Register 1 */
5550 
5551  union {
5552  uint32_t R;
5553  struct {
5554  uint32_t:6;
5555  uint32_t HLTACK6:1;
5556  uint32_t HLTACK7:1;
5557  uint32_t:1;
5558  uint32_t HLTACK9:1;
5559  uint32_t HLTACK10:1;
5560  uint32_t HLTACK11:1;
5561  uint32_t HLTACK12:1;
5562  uint32_t HLTACK13:1;
5563  uint32_t HLTACK14:1;
5564  uint32_t HLTACK15:1;
5565  uint32_t HLTACK16:1;
5566  uint32_t HLTACK17:1;
5567  uint32_t HLTACK18:1;
5568  uint32_t HLTACK19:1;
5569  uint32_t HLTACK20:1;
5570  uint32_t HLTACK21:1;
5571  uint32_t HLTACK22:1;
5572  uint32_t HLTACK23:1;
5573  uint32_t:2;
5574  uint32_t HLTACK26:1;
5575  uint32_t HLTACK27:1;
5576  uint32_t HLTACK28:1;
5577  uint32_t HLTACK29:1;
5578  uint32_t:1;
5579  uint32_t HLTACK31:1;
5580  } B;
5581  } HLTACK0; /* Halt Acknowledge Register 0 */
5582 
5583  union {
5584  uint32_t R;
5585  struct {
5586  uint32_t HLTACK0:1;
5587  uint32_t HLTACK1:1;
5588  uint32_t:1;
5589  uint32_t HLTACK3:1;
5590  uint32_t HLTACK4:1;
5591  uint32_t:11;
5592  uint32_t HLTACK20:1;
5593  uint32_t HLTACK21:1;
5594  uint32_t HLTACK22:1;
5595  uint32_t HLTACK23:1;
5596  uint32_t:2;
5597  uint32_t HLTACK26:1;
5598  uint32_t HLTACK27:1;
5599  uint32_t HLTACK28:1;
5600  uint32_t HLTACK29:1;
5601  uint32_t:2;
5602  } B;
5603  } HLTACK1; /* Halt Acknowledge Register 0 */
5604 
5605  union {
5606  uint32_t R;
5607  struct {
5608  uint32_t EMIOSSEL31:4;
5609  uint32_t EMIOSSEL30:4;
5610  uint32_t EMIOSSEL29:4;
5611  uint32_t EMIOSSEL28:4;
5612  uint32_t EMIOSSEL27:4;
5613  uint32_t EMIOSSEL26:4;
5614  uint32_t EMIOSSEL25:4;
5615  uint32_t EMIOSSEL24:4;
5616  } B;
5617  } EMIOS_SEL0; /* eMIOS Select Register 0 */
5618 
5619  union {
5620  uint32_t R;
5621  struct {
5622  uint32_t EMIOSSEL23:4;
5623  uint32_t EMIOSSEL22:4;
5624  uint32_t EMIOSSEL21:4;
5625  uint32_t EMIOSSEL20:4;
5626  uint32_t EMIOSSEL19:4;
5627  uint32_t EMIOSSEL18:4;
5628  uint32_t EMIOSSEL17:4;
5629  uint32_t EMIOSSEL16:4;
5630  } B;
5631  } EMIOS_SEL1; /* eMIOS Select Register 1 */
5632 
5633  union {
5634  uint32_t R;
5635  struct {
5636  uint32_t EMIOSSEL15:4;
5637  uint32_t EMIOSSEL14:4;
5638  uint32_t EMIOSSEL13:4;
5639  uint32_t EMIOSSEL12:4;
5640  uint32_t EMIOSSEL11:4;
5641  uint32_t EMIOSSEL10:4;
5642  uint32_t EMIOSSEL9:4;
5643  uint32_t EMIOSSEL8:4;
5644  } B;
5645  } EMIOS_SEL2; /* eMIOS Select Register 2 */
5646 
5647  union {
5648  uint32_t R;
5649  struct {
5650  uint32_t EMIOSSEL7:4;
5651  uint32_t EMIOSSEL6:4;
5652  uint32_t EMIOSSEL5:4;
5653  uint32_t EMIOSSEL4:4;
5654  uint32_t EMIOSSEL3:4;
5655  uint32_t EMIOSSEL2:4;
5656  uint32_t EMIOSSEL1:4;
5657  uint32_t EMIOSSEL0:4;
5658  } B;
5659  } EMIOS_SEL3; /* eMIOS Select Register 3 */
5660 
5661  union {
5662  uint32_t R;
5663  struct {
5664  uint32_t ESEL15:2;
5665  uint32_t ESEL14:2;
5666  uint32_t ESEL13:2;
5667  uint32_t ESEL12:2;
5668  uint32_t ESEL11:2;
5669  uint32_t ESEL10:2;
5670  uint32_t ESEL9:2;
5671  uint32_t ESEL8:2;
5672  uint32_t ESEL7:2;
5673  uint32_t ESEL6:2;
5674  uint32_t ESEL5:2;
5675  uint32_t ESEL4:2;
5676  uint32_t ESEL3:2;
5677  uint32_t ESEL2:2;
5678  uint32_t ESEL1:2;
5679  uint32_t ESEL0:2;
5680  } B;
5681  } ISEL2A; /* External Interrupt Select Register 2A */
5682 
5683  int32_t SIU_reserved9[142];
5684 
5685  union {
5686  uint32_t R;
5687  struct {
5688  uint32_t:16;
5689  uint32_t PB:16;
5690  } B;
5691  } PGPDO0; /* Parallel GPIO Pin Data Output Register */
5692 
5693  union {
5694  uint32_t R;
5695  struct {
5696  uint32_t PC:16;
5697  uint32_t PD:16;
5698  } B;
5699  } PGPDO1; /* Parallel GPIO Pin Data Output Register */
5700 
5701  union {
5702  uint32_t R;
5703  struct {
5704  uint32_t PE:16;
5705  uint32_t PF:16;
5706  } B;
5707  } PGPDO2; /* Parallel GPIO Pin Data Output Register */
5708 
5709  union {
5710  uint32_t R;
5711  struct {
5712  uint32_t PG:16;
5713  uint32_t PH:16;
5714  } B;
5715  } PGPDO3; /* Parallel GPIO Pin Data Output Register */
5716 
5717  union {
5718  uint32_t R;
5719  struct {
5720  uint32_t PJ:16;
5721  uint32_t PK:11;
5722  uint32_t:5;
5723  } B;
5724  } PGPDO4; /* Parallel GPIO Pin Data Output Register */
5725 
5726  int32_t SIU_reserved10[11];
5727 
5728  union {
5729  uint32_t R;
5730  struct {
5731  uint32_t PA:16;
5732  uint32_t PB:16;
5733  } B;
5734  } PGPDI0; /* Parallel GPIO Pin Data Input Register */
5735 
5736  union {
5737  uint32_t R;
5738  struct {
5739  uint32_t PC:16;
5740  uint32_t PD:16;
5741  } B;
5742  } PGPDI1; /* Parallel GPIO Pin Data Input Register */
5743 
5744  union {
5745  uint32_t R;
5746  struct {
5747  uint32_t PE:16;
5748  uint32_t PF:16;
5749  } B;
5750  } PGPDI2; /* Parallel GPIO Pin Data Input Register */
5751 
5752  union {
5753  uint32_t R;
5754  struct {
5755  uint32_t PG:16;
5756  uint32_t PH:16;
5757  } B;
5758  } PGPDI3; /* Parallel GPIO Pin Data Input Register */
5759 
5760  union {
5761  uint32_t R;
5762  struct {
5763  uint32_t PJ:16;
5764  uint32_t PK:11;
5765  uint32_t:5;
5766  } B;
5767  } PGPDI4; /* Parallel GPIO Pin Data Input Register */
5768 
5769  int32_t SIU_reserved11[12];
5770 
5771  union {
5772  uint32_t R;
5773  struct {
5774  uint32_t PB_MASK:16;
5775  uint32_t PB:16;
5776  } B;
5777  } MPGPDO1; /* Masked Parallel GPIO Pin Data Input Register */
5778 
5779  union {
5780  uint32_t R;
5781  struct {
5782  uint32_t PC_MASK:16;
5783  uint32_t PC:16;
5784  } B;
5785  } MPGPDO2; /* Masked Parallel GPIO Pin Data Input Register */
5786 
5787  union {
5788  uint32_t R;
5789  struct {
5790  uint32_t PD_MASK:16;
5791  uint32_t PD:16;
5792  } B;
5793  } MPGPDO3; /* Masked Parallel GPIO Pin Data Input Register */
5794 
5795  union {
5796  uint32_t R;
5797  struct {
5798  uint32_t PE_MASK:16;
5799  uint32_t PE:16;
5800  } B;
5801  } MPGPDO4; /* Masked Parallel GPIO Pin Data Input Register */
5802 
5803  union {
5804  uint32_t R;
5805  struct {
5806  uint32_t PF_MASK:16;
5807  uint32_t PF:16;
5808  } B;
5809  } MPGPDO5; /* Masked Parallel GPIO Pin Data Input Register */
5810 
5811  union {
5812  uint32_t R;
5813  struct {
5814  uint32_t PG_MASK:16;
5815  uint32_t PG:16;
5816  } B;
5817  } MPGPDO6; /* Masked Parallel GPIO Pin Data Input Register */
5818 
5819  union {
5820  uint32_t R;
5821  struct {
5822  uint32_t PH_MASK:16;
5823  uint32_t PH:16;
5824  } B;
5825  } MPGPDO7; /* Masked Parallel GPIO Pin Data Input Register */
5826 
5827  union {
5828  uint32_t R;
5829  struct {
5830  uint32_t PJ_MASK:16;
5831  uint32_t PJ:16;
5832  } B;
5833  } MPGPDO8; /* Masked Parallel GPIO Pin Data Input Register */
5834 
5835  union {
5836  uint32_t R;
5837  struct {
5838  uint32_t PK_MASK:11;
5839  uint32_t:5;
5840  uint32_t PK:11;
5841  uint32_t:5;
5842  } B;
5843  } MPGPDO9; /* Masked Parallel GPIO Pin Data Input Register */
5844 
5845  int32_t SIU_reserved12[22];
5846 
5847  union {
5848  uint32_t R;
5849  struct {
5850  uint32_t MASK31:1;
5851  uint32_t MASK30:1;
5852  uint32_t MASK29:1;
5853  uint32_t MASK28:1;
5854  uint32_t MASK27:1;
5855  uint32_t MASK26:1;
5856  uint32_t MASK25:1;
5857  uint32_t MASK24:1;
5858  uint32_t MASK23:1;
5859  uint32_t MASK22:1;
5860  uint32_t MASK21:1;
5861  uint32_t MASK20:1;
5862  uint32_t MASK19:1;
5863  uint32_t MASK18:1;
5864  uint32_t MASK17:1;
5865  uint32_t MASK16:1;
5866  uint32_t DATA31:1;
5867  uint32_t DATA30:1;
5868  uint32_t DATA29:1;
5869  uint32_t DATA28:1;
5870  uint32_t DATA27:1;
5871  uint32_t DATA26:1;
5872  uint32_t DATA25:1;
5873  uint32_t DATA24:1;
5874  uint32_t DATA23:1;
5875  uint32_t DATA22:1;
5876  uint32_t DATA21:1;
5877  uint32_t DATA20:1;
5878  uint32_t DATA19:1;
5879  uint32_t DATA18:1;
5880  uint32_t DATA17:1;
5881  uint32_t DATA16:1;
5882  } B;
5883  } DSPIAH; /* Masked Serial GPO for DSPI_A High Register */
5884 
5885  union {
5886  uint32_t R;
5887  struct {
5888  uint32_t MASK15:1;
5889  uint32_t MASK14:1;
5890  uint32_t MASK13:1;
5891  uint32_t MASK12:1;
5892  uint32_t MASK11:1;
5893  uint32_t MASK10:1;
5894  uint32_t MASK9:1;
5895  uint32_t MASK8:1;
5896  uint32_t MASK7:1;
5897  uint32_t MASK6:1;
5898  uint32_t MASK5:1;
5899  uint32_t MASK4:1;
5900  uint32_t MASK3:1;
5901  uint32_t MASK2:1;
5902  uint32_t MASK1:1;
5903  uint32_t MASK0:1;
5904  uint32_t DATA15:1;
5905  uint32_t DATA14:1;
5906  uint32_t DATA13:1;
5907  uint32_t DATA12:1;
5908  uint32_t DATA11:1;
5909  uint32_t DATA10:1;
5910  uint32_t DATA9:1;
5911  uint32_t DATA8:1;
5912  uint32_t DATA7:1;
5913  uint32_t DATA6:1;
5914  uint32_t DATA5:1;
5915  uint32_t DATA4:1;
5916  uint32_t DATA3:1;
5917  uint32_t DATA2:1;
5918  uint32_t DATA1:1;
5919  uint32_t DATA0:1;
5920  } B;
5921  } DSPIAL; /* Masked Serial GPO for DSPI_A Low Register */
5922 
5923  union {
5924  uint32_t R;
5925  struct {
5926  uint32_t MASK31:1;
5927  uint32_t MASK30:1;
5928  uint32_t MASK29:1;
5929  uint32_t MASK28:1;
5930  uint32_t MASK27:1;
5931  uint32_t MASK26:1;
5932  uint32_t MASK25:1;
5933  uint32_t MASK24:1;
5934  uint32_t MASK23:1;
5935  uint32_t MASK22:1;
5936  uint32_t MASK21:1;
5937  uint32_t MASK20:1;
5938  uint32_t MASK19:1;
5939  uint32_t MASK18:1;
5940  uint32_t MASK17:1;
5941  uint32_t MASK16:1;
5942  uint32_t DATA31:1;
5943  uint32_t DATA30:1;
5944  uint32_t DATA29:1;
5945  uint32_t DATA28:1;
5946  uint32_t DATA27:1;
5947  uint32_t DATA26:1;
5948  uint32_t DATA25:1;
5949  uint32_t DATA24:1;
5950  uint32_t DATA23:1;
5951  uint32_t DATA22:1;
5952  uint32_t DATA21:1;
5953  uint32_t DATA20:1;
5954  uint32_t DATA19:1;
5955  uint32_t DATA18:1;
5956  uint32_t DATA17:1;
5957  uint32_t DATA16:1;
5958  } B;
5959  } DSPIBH; /* Masked Serial GPO for DSPI_B High Register */
5960 
5961  union {
5962  uint32_t R;
5963  struct {
5964  uint32_t MASK15:1;
5965  uint32_t MASK14:1;
5966  uint32_t MASK13:1;
5967  uint32_t MASK12:1;
5968  uint32_t MASK11:1;
5969  uint32_t MASK10:1;
5970  uint32_t MASK9:1;
5971  uint32_t MASK8:1;
5972  uint32_t MASK7:1;
5973  uint32_t MASK6:1;
5974  uint32_t MASK5:1;
5975  uint32_t MASK4:1;
5976  uint32_t MASK3:1;
5977  uint32_t MASK2:1;
5978  uint32_t MASK1:1;
5979  uint32_t MASK0:1;
5980  uint32_t DATA15:1;
5981  uint32_t DATA14:1;
5982  uint32_t DATA13:1;
5983  uint32_t DATA12:1;
5984  uint32_t DATA11:1;
5985  uint32_t DATA10:1;
5986  uint32_t DATA9:1;
5987  uint32_t DATA8:1;
5988  uint32_t DATA7:1;
5989  uint32_t DATA6:1;
5990  uint32_t DATA5:1;
5991  uint32_t DATA4:1;
5992  uint32_t DATA3:1;
5993  uint32_t DATA2:1;
5994  uint32_t DATA1:1;
5995  uint32_t DATA0:1;
5996  } B;
5997  } DSPIBL; /* Masked Serial GPO for DSPI_B Low Register */
5998 
5999  union {
6000  uint32_t R;
6001  struct {
6002  uint32_t MASK31:1;
6003  uint32_t MASK30:1;
6004  uint32_t MASK29:1;
6005  uint32_t MASK28:1;
6006  uint32_t MASK27:1;
6007  uint32_t MASK26:1;
6008  uint32_t MASK25:1;
6009  uint32_t MASK24:1;
6010  uint32_t MASK23:1;
6011  uint32_t MASK22:1;
6012  uint32_t MASK21:1;
6013  uint32_t MASK20:1;
6014  uint32_t MASK19:1;
6015  uint32_t MASK18:1;
6016  uint32_t MASK17:1;
6017  uint32_t MASK16:1;
6018  uint32_t DATA31:1;
6019  uint32_t DATA30:1;
6020  uint32_t DATA29:1;
6021  uint32_t DATA28:1;
6022  uint32_t DATA27:1;
6023  uint32_t DATA26:1;
6024  uint32_t DATA25:1;
6025  uint32_t DATA24:1;
6026  uint32_t DATA23:1;
6027  uint32_t DATA22:1;
6028  uint32_t DATA21:1;
6029  uint32_t DATA20:1;
6030  uint32_t DATA19:1;
6031  uint32_t DATA18:1;
6032  uint32_t DATA17:1;
6033  uint32_t DATA16:1;
6034  } B;
6035  } DSPICH; /* Masked Serial GPO for DSPI_C High Register */
6036 
6037  union {
6038  uint32_t R;
6039  struct {
6040  uint32_t MASK15:1;
6041  uint32_t MASK14:1;
6042  uint32_t MASK13:1;
6043  uint32_t MASK12:1;
6044  uint32_t MASK11:1;
6045  uint32_t MASK10:1;
6046  uint32_t MASK9:1;
6047  uint32_t MASK8:1;
6048  uint32_t MASK7:1;
6049  uint32_t MASK6:1;
6050  uint32_t MASK5:1;
6051  uint32_t MASK4:1;
6052  uint32_t MASK3:1;
6053  uint32_t MASK2:1;
6054  uint32_t MASK1:1;
6055  uint32_t MASK0:1;
6056  uint32_t DATA15:1;
6057  uint32_t DATA14:1;
6058  uint32_t DATA13:1;
6059  uint32_t DATA12:1;
6060  uint32_t DATA11:1;
6061  uint32_t DATA10:1;
6062  uint32_t DATA9:1;
6063  uint32_t DATA8:1;
6064  uint32_t DATA7:1;
6065  uint32_t DATA6:1;
6066  uint32_t DATA5:1;
6067  uint32_t DATA4:1;
6068  uint32_t DATA3:1;
6069  uint32_t DATA2:1;
6070  uint32_t DATA1:1;
6071  uint32_t DATA0:1;
6072  } B;
6073  } DSPICL; /* Masked Serial GPO for DSPI_C Low Register */
6074 
6075  union {
6076  uint32_t R;
6077  struct {
6078  uint32_t MASK31:1;
6079  uint32_t MASK30:1;
6080  uint32_t MASK29:1;
6081  uint32_t MASK28:1;
6082  uint32_t MASK27:1;
6083  uint32_t MASK26:1;
6084  uint32_t MASK25:1;
6085  uint32_t MASK24:1;
6086  uint32_t MASK23:1;
6087  uint32_t MASK22:1;
6088  uint32_t MASK21:1;
6089  uint32_t MASK20:1;
6090  uint32_t MASK19:1;
6091  uint32_t MASK18:1;
6092  uint32_t MASK17:1;
6093  uint32_t MASK16:1;
6094  uint32_t DATA31:1;
6095  uint32_t DATA30:1;
6096  uint32_t DATA29:1;
6097  uint32_t DATA28:1;
6098  uint32_t DATA27:1;
6099  uint32_t DATA26:1;
6100  uint32_t DATA25:1;
6101  uint32_t DATA24:1;
6102  uint32_t DATA23:1;
6103  uint32_t DATA22:1;
6104  uint32_t DATA21:1;
6105  uint32_t DATA20:1;
6106  uint32_t DATA19:1;
6107  uint32_t DATA18:1;
6108  uint32_t DATA17:1;
6109  uint32_t DATA16:1;
6110  } B;
6111  } DSPIDH; /* Masked Serial GPO for DSPI_D High Register */
6112 
6113  union {
6114  uint32_t R;
6115  struct {
6116  uint32_t MASK15:1;
6117  uint32_t MASK14:1;
6118  uint32_t MASK13:1;
6119  uint32_t MASK12:1;
6120  uint32_t MASK11:1;
6121  uint32_t MASK10:1;
6122  uint32_t MASK9:1;
6123  uint32_t MASK8:1;
6124  uint32_t MASK7:1;
6125  uint32_t MASK6:1;
6126  uint32_t MASK5:1;
6127  uint32_t MASK4:1;
6128  uint32_t MASK3:1;
6129  uint32_t MASK2:1;
6130  uint32_t MASK1:1;
6131  uint32_t MASK0:1;
6132  uint32_t DATA15:1;
6133  uint32_t DATA14:1;
6134  uint32_t DATA13:1;
6135  uint32_t DATA12:1;
6136  uint32_t DATA11:1;
6137  uint32_t DATA10:1;
6138  uint32_t DATA9:1;
6139  uint32_t DATA8:1;
6140  uint32_t DATA7:1;
6141  uint32_t DATA6:1;
6142  uint32_t DATA5:1;
6143  uint32_t DATA4:1;
6144  uint32_t DATA3:1;
6145  uint32_t DATA2:1;
6146  uint32_t DATA1:1;
6147  uint32_t DATA0:1;
6148  } B;
6149  } DSPIDL; /* Masked Serial GPO for DSPI_D Low Register */
6150 
6151  int32_t SIU_reserved13[9];
6152 
6153  union {
6154  uint32_t R;
6155  struct {
6156  uint32_t EMIOS31:1;
6157  uint32_t EMIOS30:1;
6158  uint32_t EMIOS29:1;
6159  uint32_t EMIOS28:1;
6160  uint32_t EMIOS27:1;
6161  uint32_t EMIOS26:1;
6162  uint32_t EMIOS25:1;
6163  uint32_t EMIOS24:1;
6164  uint32_t EMIOS23:1;
6165  uint32_t EMIOS22:1;
6166  uint32_t EMIOS21:1;
6167  uint32_t EMIOS20:1;
6168  uint32_t EMIOS19:1;
6169  uint32_t EMIOS18:1;
6170  uint32_t EMIOS17:1;
6171  uint32_t EMIOS16:1;
6172  uint32_t EMIOS15:1;
6173  uint32_t EMIOS14:1;
6174  uint32_t EMIOS13:1;
6175  uint32_t EMIOS12:1;
6176  uint32_t EMIOS11:1;
6177  uint32_t EMIOS10:1;
6178  uint32_t EMIOS9:1;
6179  uint32_t EMIOS8:1;
6180  uint32_t EMIOS7:1;
6181  uint32_t EMIOS6:1;
6182  uint32_t EMIOS5:1;
6183  uint32_t EMIOS4:1;
6184  uint32_t EMIOS3:1;
6185  uint32_t EMIOS2:1;
6186  uint32_t EMIOS1:1;
6187  uint32_t EMIOS0:1;
6188  } B;
6189  } EMIOSA; /* EMIOS A Select Register */
6190 
6191  union {
6192  uint32_t R;
6193  struct {
6194  uint32_t DSPIAH31:1;
6195  uint32_t DSPIAH30:1;
6196  uint32_t DSPIAH29:1;
6197  uint32_t DSPIAH28:1;
6198  uint32_t DSPIAH27:1;
6199  uint32_t DSPIAH26:1;
6200  uint32_t DSPIAH25:1;
6201  uint32_t DSPIAH24:1;
6202  uint32_t DSPIAH23:1;
6203  uint32_t DSPIAH22:1;
6204  uint32_t DSPIAH21:1;
6205  uint32_t DSPIAH20:1;
6206  uint32_t DSPIAH19:1;
6207  uint32_t DSPIAH18:1;
6208  uint32_t DSPIAH17:1;
6209  uint32_t DSPIAH16:1;
6210  uint32_t DSPIAL15:1;
6211  uint32_t DSPIAL14:1;
6212  uint32_t DSPIAL13:1;
6213  uint32_t DSPIAL12:1;
6214  uint32_t DSPIAL11:1;
6215  uint32_t DSPIAL10:1;
6216  uint32_t DSPIAL9:1;
6217  uint32_t DSPIAL8:1;
6218  uint32_t DSPIAL7:1;
6219  uint32_t DSPIAL6:1;
6220  uint32_t DSPIAL5:1;
6221  uint32_t DSPIAL4:1;
6222  uint32_t DSPIAL3:1;
6223  uint32_t DSPIAL2:1;
6224  uint32_t DSPIAL1:1;
6225  uint32_t DSPIAL0:1;
6226  } B;
6227  } DSPIAHLA; /* DSPIAH/L Select Register for DSPI A */
6228 
6229  int32_t SIU_reserved14[2];
6230 
6231  union {
6232  uint32_t R;
6233  struct {
6234  uint32_t EMIOS31:1;
6235  uint32_t EMIOS30:1;
6236  uint32_t EMIOS29:1;
6237  uint32_t EMIOS28:1;
6238  uint32_t EMIOS27:1;
6239  uint32_t EMIOS26:1;
6240  uint32_t EMIOS25:1;
6241  uint32_t EMIOS24:1;
6242  uint32_t EMIOS23:1;
6243  uint32_t EMIOS22:1;
6244  uint32_t EMIOS21:1;
6245  uint32_t EMIOS20:1;
6246  uint32_t EMIOS19:1;
6247  uint32_t EMIOS18:1;
6248  uint32_t EMIOS17:1;
6249  uint32_t EMIOS16:1;
6250  uint32_t EMIOS15:1;
6251  uint32_t EMIOS14:1;
6252  uint32_t EMIOS13:1;
6253  uint32_t EMIOS12:1;
6254  uint32_t EMIOS11:1;
6255  uint32_t EMIOS10:1;
6256  uint32_t EMIOS9:1;
6257  uint32_t EMIOS8:1;
6258  uint32_t EMIOS7:1;
6259  uint32_t EMIOS6:1;
6260  uint32_t EMIOS5:1;
6261  uint32_t EMIOS4:1;
6262  uint32_t EMIOS3:1;
6263  uint32_t EMIOS2:1;
6264  uint32_t EMIOS1:1;
6265  uint32_t EMIOS0:1;
6266  } B;
6267  } EMIOSB; /* EMIOS B Select Register */
6268 
6269  union {
6270  uint32_t R;
6271  struct {
6272  uint32_t DSPIBH31:1;
6273  uint32_t DSPIBH30:1;
6274  uint32_t DSPIBH29:1;
6275  uint32_t DSPIBH28:1;
6276  uint32_t DSPIBH27:1;
6277  uint32_t DSPIBH26:1;
6278  uint32_t DSPIBH25:1;
6279  uint32_t DSPIBH24:1;
6280  uint32_t DSPIBH23:1;
6281  uint32_t DSPIBH22:1;
6282  uint32_t DSPIBH21:1;
6283  uint32_t DSPIBH20:1;
6284  uint32_t DSPIBH19:1;
6285  uint32_t DSPIBH18:1;
6286  uint32_t DSPIBH17:1;
6287  uint32_t DSPIBH16:1;
6288  uint32_t DSPIBL15:1;
6289  uint32_t DSPIBL14:1;
6290  uint32_t DSPIBL13:1;
6291  uint32_t DSPIBL12:1;
6292  uint32_t DSPIBL11:1;
6293  uint32_t DSPIBL10:1;
6294  uint32_t DSPIBL9:1;
6295  uint32_t DSPIBL8:1;
6296  uint32_t DSPIBL7:1;
6297  uint32_t DSPIBL6:1;
6298  uint32_t DSPIBL5:1;
6299  uint32_t DSPIBL4:1;
6300  uint32_t DSPIBL3:1;
6301  uint32_t DSPIBL2:1;
6302  uint32_t DSPIBL1:1;
6303  uint32_t DSPIBL0:1;
6304  } B;
6305  } DSPIBHLB; /* DSPIBH/L Select Register for DSPI B */
6306 
6307  int32_t SIU_reserved115[2];
6308 
6309  union {
6310  uint32_t R;
6311  struct {
6312  uint32_t EMIOS31:1;
6313  uint32_t EMIOS30:1;
6314  uint32_t EMIOS29:1;
6315  uint32_t EMIOS28:1;
6316  uint32_t EMIOS27:1;
6317  uint32_t EMIOS26:1;
6318  uint32_t EMIOS25:1;
6319  uint32_t EMIOS24:1;
6320  uint32_t EMIOS23:1;
6321  uint32_t EMIOS22:1;
6322  uint32_t EMIOS21:1;
6323  uint32_t EMIOS20:1;
6324  uint32_t EMIOS19:1;
6325  uint32_t EMIOS18:1;
6326  uint32_t EMIOS17:1;
6327  uint32_t EMIOS16:1;
6328  uint32_t EMIOS15:1;
6329  uint32_t EMIOS14:1;
6330  uint32_t EMIOS13:1;
6331  uint32_t EMIOS12:1;
6332  uint32_t EMIOS11:1;
6333  uint32_t EMIOS10:1;
6334  uint32_t EMIOS9:1;
6335  uint32_t EMIOS8:1;
6336  uint32_t EMIOS7:1;
6337  uint32_t EMIOS6:1;
6338  uint32_t EMIOS5:1;
6339  uint32_t EMIOS4:1;
6340  uint32_t EMIOS3:1;
6341  uint32_t EMIOS2:1;
6342  uint32_t EMIOS1:1;
6343  uint32_t EMIOS0:1;
6344  } B;
6345  } EMIOSC; /* EMIOS C Select Register */
6346 
6347  union {
6348  uint32_t R;
6349  struct {
6350  uint32_t DSPICH31:1;
6351  uint32_t DSPICH30:1;
6352  uint32_t DSPICH29:1;
6353  uint32_t DSPICH28:1;
6354  uint32_t DSPICH27:1;
6355  uint32_t DSPICH26:1;
6356  uint32_t DSPICH25:1;
6357  uint32_t DSPICH24:1;
6358  uint32_t DSPICH23:1;
6359  uint32_t DSPICH22:1;
6360  uint32_t DSPICH21:1;
6361  uint32_t DSPICH20:1;
6362  uint32_t DSPICH19:1;
6363  uint32_t DSPICH18:1;
6364  uint32_t DSPICH17:1;
6365  uint32_t DSPICH16:1;
6366  uint32_t DSPICL15:1;
6367  uint32_t DSPICL14:1;
6368  uint32_t DSPICL13:1;
6369  uint32_t DSPICL12:1;
6370  uint32_t DSPICL11:1;
6371  uint32_t DSPICL10:1;
6372  uint32_t DSPICL9:1;
6373  uint32_t DSPICL8:1;
6374  uint32_t DSPICL7:1;
6375  uint32_t DSPICL6:1;
6376  uint32_t DSPICL5:1;
6377  uint32_t DSPICL4:1;
6378  uint32_t DSPICL3:1;
6379  uint32_t DSPICL2:1;
6380  uint32_t DSPICL1:1;
6381  uint32_t DSPICL0:1;
6382  } B;
6383  } DSPICHLC; /* DSPIAH/L Select Register for DSPI C */
6384 
6385  int32_t SIU_reserved16[2];
6386 
6387  union {
6388  uint32_t R;
6389  struct {
6390  uint32_t EMIOS31:1;
6391  uint32_t EMIOS30:1;
6392  uint32_t EMIOS29:1;
6393  uint32_t EMIOS28:1;
6394  uint32_t EMIOS27:1;
6395  uint32_t EMIOS26:1;
6396  uint32_t EMIOS25:1;
6397  uint32_t EMIOS24:1;
6398  uint32_t EMIOS23:1;
6399  uint32_t EMIOS22:1;
6400  uint32_t EMIOS21:1;
6401  uint32_t EMIOS20:1;
6402  uint32_t EMIOS19:1;
6403  uint32_t EMIOS18:1;
6404  uint32_t EMIOS17:1;
6405  uint32_t EMIOS16:1;
6406  uint32_t EMIOS15:1;
6407  uint32_t EMIOS14:1;
6408  uint32_t EMIOS13:1;
6409  uint32_t EMIOS12:1;
6410  uint32_t EMIOS11:1;
6411  uint32_t EMIOS10:1;
6412  uint32_t EMIOS9:1;
6413  uint32_t EMIOS8:1;
6414  uint32_t EMIOS7:1;
6415  uint32_t EMIOS6:1;
6416  uint32_t EMIOS5:1;
6417  uint32_t EMIOS4:1;
6418  uint32_t EMIOS3:1;
6419  uint32_t EMIOS2:1;
6420  uint32_t EMIOS1:1;
6421  uint32_t EMIOS0:1;
6422  } B;
6423  } EMIOSD; /* EMIOS D Select Register */
6424 
6425  union {
6426  uint32_t R;
6427  struct {
6428  uint32_t DSPIDH31:1;
6429  uint32_t DSPIDH30:1;
6430  uint32_t DSPIDH29:1;
6431  uint32_t DSPIDH28:1;
6432  uint32_t DSPIDH27:1;
6433  uint32_t DSPIDH26:1;
6434  uint32_t DSPIDH25:1;
6435  uint32_t DSPIDH24:1;
6436  uint32_t DSPIDH23:1;
6437  uint32_t DSPIDH22:1;
6438  uint32_t DSPIDH21:1;
6439  uint32_t DSPIDH20:1;
6440  uint32_t DSPIDH19:1;
6441  uint32_t DSPIDH18:1;
6442  uint32_t DSPIDH17:1;
6443  uint32_t DSPIDH16:1;
6444  uint32_t DSPIDL15:1;
6445  uint32_t DSPIDL14:1;
6446  uint32_t DSPIDL13:1;
6447  uint32_t DSPIDL12:1;
6448  uint32_t DSPIDL11:1;
6449  uint32_t DSPIDL10:1;
6450  uint32_t DSPIDL9:1;
6451  uint32_t DSPIDL8:1;
6452  uint32_t DSPIDL7:1;
6453  uint32_t DSPIDL6:1;
6454  uint32_t DSPIDL5:1;
6455  uint32_t DSPIDL4:1;
6456  uint32_t DSPIDL3:1;
6457  uint32_t DSPIDL2:1;
6458  uint32_t DSPIDL1:1;
6459  uint32_t DSPIDL0:1;
6460  } B;
6461  } DSPIDHLD; /* DSPIAH/L Select Register for DSPI D */
6462 
6463  }; /* end of SIU_tag */
6464 /**************************************************************************/
6465 /* MODULE : STM */
6466 /**************************************************************************/
6467  struct STM_tag {
6468 
6469  union {
6470  uint32_t R;
6471  struct {
6472  uint32_t:16;
6473  uint32_t CPS:8;
6474  uint32_t:6;
6475  uint32_t FRZ:1;
6476  uint32_t TEN:1;
6477  } B;
6478  } CR; /* STM Control Register */
6479 
6480  union {
6481  uint32_t R;
6482  } CNT; /* STM Count Register */
6483 
6484  int32_t STM_reserved[2];
6485 
6486  union {
6487  uint32_t R;
6488  struct {
6489  uint32_t:31;
6490  uint32_t CEN:1;
6491  } B;
6492  } CCR0; /* STM Channel Control Register 0 */
6493 
6494  union {
6495  uint32_t R;
6496  struct {
6497  uint32_t:31;
6498  uint32_t CIF:1;
6499  } B;
6500  } CIR0; /* STM Channel Interrupt Register 0 */
6501 
6502  union {
6503  uint32_t R;
6504  } CMP0; /* STM Channel Compare Register 0 */
6505 
6506  int32_t STM_reserved1;
6507 
6508  union {
6509  uint32_t R;
6510  struct {
6511  uint32_t:31;
6512  uint32_t CEN:1;
6513  } B;
6514  } CCR1; /* STM Channel Control Register 1 */
6515 
6516  union {
6517  uint32_t R;
6518  struct {
6519  uint32_t:31;
6520  uint32_t CIF:1;
6521  } B;
6522  } CIR1; /* STM Channel Interrupt Register 1 */
6523 
6524  union {
6525  uint32_t R;
6526  } CMP1; /* STM Channel Compare Register 1 */
6527 
6528  int32_t STM_reserved2;
6529 
6530  union {
6531  uint32_t R;
6532  struct {
6533  uint32_t:31;
6534  uint32_t CEN:1;
6535  } B;
6536  } CCR2; /* STM Channel Control Register 2 */
6537 
6538  union {
6539  uint32_t R;
6540  struct {
6541  uint32_t:31;
6542  uint32_t CIF:1;
6543  } B;
6544  } CIR2; /* STM Channel Interrupt Register 2 */
6545 
6546  union {
6547  uint32_t R;
6548  } CMP2; /* STM Channel Compare Register 2 */
6549 
6550  int32_t STM_reserved3;
6551 
6552  union {
6553  uint32_t R;
6554  struct {
6555  uint32_t:31;
6556  uint32_t CEN:1;
6557  } B;
6558  } CCR3; /* STM Channel Control Register 3 */
6559 
6560  union {
6561  uint32_t R;
6562  struct {
6563  uint32_t:31;
6564  uint32_t CIF:1;
6565  } B;
6566  } CIR3; /* STM Channel Interrupt Register 3 */
6567 
6568  union {
6569  uint32_t R;
6570  } CMP3; /* STM Channel Compare Register 3 */
6571 
6572  }; /* end of STM_tag */
6573 /**************************************************************************/
6574 /* MODULE : SWT */
6575 /**************************************************************************/
6576  struct SWT_tag {
6577  union {
6578  uint32_t R;
6579  struct {
6580  uint32_t MAP0:1;
6581  uint32_t MAP1:1;
6582  uint32_t MAP2:1;
6583  uint32_t MAP3:1;
6584  uint32_t MAP4:1;
6585  uint32_t MAP5:1;
6586  uint32_t MAP6:1;
6587  uint32_t MAP7:1;
6588  uint32_t:14;
6589  uint32_t KEY:1;
6590  uint32_t RIA:1;
6591  uint32_t WND:1;
6592  uint32_t ITR:1;
6593  uint32_t HLK:1;
6594  uint32_t SLK:1;
6595  uint32_t:2;
6596  uint32_t FRZ:1;
6597  uint32_t WEN:1;
6598  } B;
6599  } CR; /* SWT Control Register */
6600 
6601  union {
6602  uint32_t R;
6603  struct {
6604  uint32_t:31;
6605  uint32_t TIF:1;
6606  } B;
6607  } IR; /* SWT Interrupt Register */
6608 
6609  union {
6610  uint32_t R;
6611  struct {
6612  uint32_t WTO:32;
6613  } B;
6614  } TO; /* SWT Time-Out Register */
6615 
6616  union {
6617  uint32_t R;
6618  struct {
6619  uint32_t WST:32;
6620  } B;
6621  } WN; /* SWT Window Register */
6622 
6623  union {
6624  uint32_t R;
6625  struct {
6626  uint32_t:16;
6627  uint32_t WSC:16;
6628  } B;
6629  } SR; /* SWT Service Register */
6630 
6631  union {
6632  uint32_t R;
6633  struct {
6634  uint32_t CNT:32;
6635  } B;
6636  } CO; /* SWT Counter Output Register */
6637 
6638  union {
6639  uint32_t R;
6640  struct {
6641  uint32_t:16;
6642  uint32_t SK:16;
6643  } B;
6644  } SK; /* SWT Service Key Register */
6645 
6646  }; /* end of SWT_tag */
6647 
6648 /* Define memories */
6649 
6650 #define SRAM0_START 0x40000000UL
6651 #define SRAM0_SIZE 0x80000UL
6652 #define SRAM0_END 0x4007FFFFUL
6653 
6654 #define SRAM1_START 0x40080000UL
6655 #define SRAM1_SIZE 0x14000UL
6656 #define SRAM1_END 0x40093FFFUL
6657 
6658 #define FLASH_START 0x0UL
6659 #define FLASH_SIZE 0x200000UL
6660 #define FLASH_END 0x1FFFFFUL
6661 
6662 /* Define instances of modules AIPS_A */
6663 #define MLB (*(volatile struct MLB_tag *) 0xC3F84000UL)
6664 #define I2C_C (*(volatile struct I2C_tag *) 0xC3F88000UL)
6665 #define I2C_D (*(volatile struct I2C_tag *) 0xC3F8C000UL)
6666 #define DSPI_C (*(volatile struct DSPI_tag *) 0xC3F90000UL)
6667 #define DSPI_D (*(volatile struct DSPI_tag *) 0xC3F94000UL)
6668 #define ESCI_J (*(volatile struct ESCI_tag *) 0xC3FA0000UL)
6669 #define ESCI_K (*(volatile struct ESCI_tag *) 0xC3FA4000UL)
6670 #define ESCI_L (*(volatile struct ESCI_tag *) 0xC3FA8000UL)
6671 #define ESCI_M (*(volatile struct ESCI_tag *) 0xC3FAC000UL)
6672 #define FR (*(volatile struct FR_tag *) 0xC3FDC000UL)
6673 
6674 /* Define instances of modules AIPS_B */
6675 #define XBAR (*(volatile struct XBAR_tag *) 0xFFF04000UL)
6676 #define SEMA4 (*(volatile struct SEMA4_tag *) 0xFFF10000UL)
6677 #define MPU (*(volatile struct MPU_tag *) 0xFFF14000UL)
6678 #define SWT (*(volatile struct SWT_tag *) 0xFFF38000UL)
6679 #define STM (*(volatile struct STM_tag *) 0xFFF3C000UL)
6680 #define ECSM (*(volatile struct ECSM_tag *) 0xFFF40000UL)
6681 #define EDMA (*(volatile struct EDMA_tag *) 0xFFF44000UL)
6682 #define INTC (*(volatile struct INTC_tag *) 0xFFF48000UL)
6683 #define FEC (*(volatile struct FEC_tag *) 0xFFF4C000UL)
6684 #define ADC (*(volatile struct ADC_tag *) 0xFFF80000UL)
6685 #define I2C_A (*(volatile struct I2C_tag *) 0xFFF88000UL)
6686 #define I2C_B (*(volatile struct I2C_tag *) 0xFFF8C000UL)
6687 #define DSPI_A (*(volatile struct DSPI_tag *) 0xFFF90000UL)
6688 #define DSPI_B (*(volatile struct DSPI_tag *) 0xFFF94000UL)
6689 #define ESCI_A (*(volatile struct ESCI_tag *) 0xFFFA0000UL)
6690 #define ESCI_B (*(volatile struct ESCI_tag *) 0xFFFA4000UL)
6691 #define ESCI_C (*(volatile struct ESCI_tag *) 0xFFFA8000UL)
6692 #define ESCI_D (*(volatile struct ESCI_tag *) 0xFFFAC000UL)
6693 #define ESCI_E (*(volatile struct ESCI_tag *) 0xFFFB0000UL)
6694 #define ESCI_F (*(volatile struct ESCI_tag *) 0xFFFB4000UL)
6695 #define ESCI_G (*(volatile struct ESCI_tag *) 0xFFFB8000UL)
6696 #define ESCI_H (*(volatile struct ESCI_tag *) 0xFFFBC000UL)
6697 #define CAN_A (*(volatile struct FLEXCAN_tag *) 0xFFFC0000UL)
6698 #define CAN_B (*(volatile struct FLEXCAN_tag *) 0xFFFC4000UL)
6699 #define CAN_C (*(volatile struct FLEXCAN_tag *) 0xFFFC8000UL)
6700 #define CAN_D (*(volatile struct FLEXCAN_tag *) 0xFFFCC000UL)
6701 #define CAN_E (*(volatile struct FLEXCAN_tag *) 0xFFFD0000UL)
6702 #define CAN_F (*(volatile struct FLEXCAN_tag *) 0xFFFD4000UL)
6703 #define CTU (*(volatile struct CTU_tag *) 0xFFFD8000UL)
6704 #define DMAMUX (*(volatile struct DMAMUX_tag *) 0xFFFDC000UL)
6705 #define PIT (*(volatile struct PIT_tag *) 0xFFFE0000UL)
6706 #define PIT_RTI (*(volatile struct PIT_tag *) 0xFFFE0000UL)
6707 #define EMIOS (*(volatile struct EMIOS_tag *) 0xFFFE4000UL)
6708 #define SIU (*(volatile struct SIU_tag *) 0xFFFE8000UL)
6709 #define CRP (*(volatile struct CRP_tag *) 0xFFFEC000UL)
6710 #define FMPLL (*(volatile struct FMPLL_tag *) 0xFFFF0000UL)
6711 #define FLASH (*(volatile struct FLASH_tag *) 0xFFFF8000UL)
6712 
6713 #ifdef __MWERKS__
6714 #pragma pop
6715 #endif
6716 
6717 #ifdef __cplusplus
6718 }
6719 #endif
6720 #endif /* ASM */
6721 #endif /* ifdef _MPC5668_H */
uTICCR
Definition: fsl-mpc551x.h:3093
uSLTCTAR
Definition: fsl-mpc551x.h:3552
uRSBIR
Definition: fsl-mpc551x.h:3182
uNMVLR
Definition: fsl-mpc551x.h:3576
uPCR8
Definition: fsl-mpc551x.h:3295
uRFFIDRFMR
Definition: fsl-mpc551x.h:3612
TCR
#define TCR
tx configuration reg
Definition: wd80x3.h:99
uSFIDAFMR
Definition: fsl-mpc551x.h:3570
uPCR23
Definition: fsl-mpc551x.h:3418
uRFRFCTR
Definition: fsl-mpc551x.h:3213
PE
#define PE
Parity Error.
Definition: uart.h:125
uRFMIDAFVR
Definition: fsl-mpc551x.h:3603
XBAR_tag
Definition: fsl-mpc555x.h:1982
uPCR15
Definition: fsl-mpc551x.h:3355
uPIFR1
Definition: fsl-mpc551x.h:2884
DR
#define DR
Bits definition of the Line Status Register (LSR)
Definition: uart.h:123
uPIER1
Definition: fsl-mpc551x.h:2922
PIT_tag::PIT_CHANNEL_tag::PIT_TFLG_tag
Definition: fsl-mpc5668.h:4962
RESET
#define RESET
Issue a read for reset.
Definition: wd80x3.h:31
uRFFIDRFVR
Definition: fsl-mpc551x.h:3609
ESCI_tag
Definition: fsl-mpc551x.h:899
uSFIDAFVR
Definition: fsl-mpc551x.h:3567
uSSCCR
Definition: fsl-mpc551x.h:3134
uSSCR
Definition: fsl-mpc551x.h:3588
uSFTCCSR
Definition: fsl-mpc551x.h:3069
uRFRFCFR
Definition: fsl-mpc551x.h:3202
uPCR28
Definition: fsl-mpc551x.h:3457
uSSSR
Definition: fsl-mpc551x.h:3123
DSPI_RSER_tag
Definition: fsl-mpc564xL.h:16627
uPCR4
Definition: fsl-mpc551x.h:3261
uCYCTR
Definition: fsl-mpc551x.h:3546
DMAMUX_tag
Definition: fsl-mpc551x.h:230
FEC_tag
Definition: fsl-mpc556x.h:2982
uPCR2
Definition: fsl-mpc551x.h:3244
uRFARIR
Definition: fsl-mpc551x.h:3597
uCASERCR
Definition: fsl-mpc551x.h:3540
FMPLL_tag
Definition: fsl-mpc551x.h:1484
uPSR2
Definition: fsl-mpc551x.h:3000
uPCR21
Definition: fsl-mpc551x.h:3401
uRFBRIR
Definition: fsl-mpc551x.h:3600
uPCR30
Definition: fsl-mpc551x.h:3473
DSPI_CTAR_tag
Definition: fsl-mpc564xL.h:16586
uS_STSTUS
Definition: fsl-mpc551x.h:3741
uPCR7
Definition: fsl-mpc551x.h:3287
SIU_PCR_tag
Definition: fsl-mpc564xL.h:966
uMBIVEC
Definition: fsl-mpc551x.h:2960
uRFSIR
Definition: fsl-mpc551x.h:3594
uPCR24
Definition: fsl-mpc551x.h:3425
uMCR
Definition: fsl-mpc551x.h:2781
SWT_tag
Definition: fsl-mpc5668.h:6576
uPCR16
Definition: fsl-mpc551x.h:3362
uGIFER
Definition: fsl-mpc551x.h:2842
uRFMIAFMR
Definition: fsl-mpc551x.h:3606
uPCR10
Definition: fsl-mpc551x.h:3313
uSSR
Definition: fsl-mpc551x.h:3150
uMTSCFR
Definition: fsl-mpc551x.h:3171
FR_tag
Definition: fsl-mpc551x.h:3622
uLDTXSLAR
Definition: fsl-mpc551x.h:3615
uPADR
Definition: fsl-mpc551x.h:3534
uPCR17
Definition: fsl-mpc551x.h:3370
uTI2CR0
Definition: fsl-mpc551x.h:3582
RCR
#define RCR
rx configuration reg
Definition: wd80x3.h:97
uPCR3
Definition: fsl-mpc551x.h:3252
DSPI_PUSHR_tag
Definition: fsl-mpc564xL.h:16678
uPCR1
Definition: fsl-mpc551x.h:3236
uPSR3
Definition: fsl-mpc551x.h:3018
uSLTCTBR
Definition: fsl-mpc551x.h:3555
PIT_tag::PIT_CHANNEL_tag
Definition: fsl-mpc5668.h:4938
uSYSBADLR
Definition: fsl-mpc551x.h:3531
uPSR1
Definition: fsl-mpc551x.h:2987
uPCR22
Definition: fsl-mpc551x.h:3409
uSTBSCR
Definition: fsl-mpc551x.h:2796
DACC
#define DACC
(DACC ) Base Address
Definition: same70j19.h:515
STM_tag
Definition: fsl-mpc5668.h:6467
uCHIERFR
Definition: fsl-mpc551x.h:2939
DSPI_SR_tag
Definition: fsl-mpc564xL.h:16605
DSPI_tag
Definition: fsl-mpc551x.h:244
uPCR29
Definition: fsl-mpc551x.h:3465
uMSG_BUFF_CCS
Definition: fsl-mpc551x.h:3481
uPCR13
Definition: fsl-mpc551x.h:3339
ADC_tag
Definition: fsl-mpc5668.h:73
uMBDSR
Definition: fsl-mpc551x.h:2807
SEMA4_tag
Definition: fsl-mpc551x.h:2087
uSFTOR
Definition: fsl-mpc551x.h:3564
uPCR18
Definition: fsl-mpc551x.h:3377
DSPI_POPR_tag
Definition: fsl-mpc564xL.h:16698
uRFDSR
Definition: fsl-mpc551x.h:3193
uPCR6
Definition: fsl-mpc551x.h:3278
SIU_tag
Definition: fsl-mpc551x.h:2221
uSYSBADHR
Definition: fsl-mpc551x.h:3528
uPCR25
Definition: fsl-mpc551x.h:3434
uCIFRR
Definition: fsl-mpc551x.h:3037
ECSM_tag
Definition: fsl-mpc555x.h:2179
uSYMATOR
Definition: fsl-mpc551x.h:3051
uMTCTR
Definition: fsl-mpc551x.h:3549
uTI1CYSR
Definition: fsl-mpc551x.h:3112
uPCR11
Definition: fsl-mpc551x.h:3322
LCR
#define LCR
Line Control Register.
Definition: uart.h:90
uPCR9
Definition: fsl-mpc551x.h:3304
I2C_tag
Definition: fsl-mpc551x.h:1539
uNMVR
Definition: fsl-mpc551x.h:3573
MLB_tag::mlbch_t
Definition: fsl-mpc5668.h:4673
uPCR14
Definition: fsl-mpc551x.h:3347
uTI2CR1
Definition: fsl-mpc551x.h:3585
uMBSSUTR
Definition: fsl-mpc551x.h:2817
uPDAR
Definition: fsl-mpc551x.h:3537
uPIFR0
Definition: fsl-mpc551x.h:2863
uPIER0
Definition: fsl-mpc551x.h:2901
uCBSERCR
Definition: fsl-mpc551x.h:3543
uPCR0
Definition: fsl-mpc551x.h:3228
uRFSR
Definition: fsl-mpc551x.h:3591
uPSR0
Definition: fsl-mpc551x.h:2971
uF_HEADER
Definition: fsl-mpc551x.h:3723
PIT_tag::PIT_MCR_tag
Definition: fsl-mpc5668.h:4927
CTU_tag
Definition: fsl-mpc5668.h:1542
uOFCORVR
Definition: fsl-mpc551x.h:3561
uT1MTOR
Definition: fsl-mpc551x.h:3579
FE
#define FE
Framing Error.
Definition: uart.h:126
INTC_tag
Definition: fsl-mpc551x.h:1603
uPCR5
Definition: fsl-mpc551x.h:3269
uMVR
Definition: fsl-mpc551x.h:2773
RSR
#define RSR
rx status reg for rd
Definition: wd80x3.h:63
FLEXCAN_tag
Definition: fsl-mpc551x.h:1171
uPCR26
Definition: fsl-mpc551x.h:3441
uPOCR
Definition: fsl-mpc551x.h:2828
MCR
#define MCR
Modem Control Register.
Definition: uart.h:91
CRP_tag
Definition: fsl-mpc551x.h:73
FLASH_tag
Definition: fsl-mpc551x.h:1027
uPCR20
Definition: fsl-mpc551x.h:3393
PIT_tag::PIT_CHANNEL_tag::PIT_TCTRL_tag
Definition: fsl-mpc5668.h:4953
MLB_tag
Definition: fsl-mpc551x.h:3791
uPCR12
Definition: fsl-mpc551x.h:3331
DSPI_MCR_tag
Definition: fsl-mpc564xL.h:16541
MPU_tag
Definition: fsl-mpc551x.h:1843
uLDTXSLBR
Definition: fsl-mpc551x.h:3618
uSFIDRFR
Definition: fsl-mpc551x.h:3085
PIT_tag
Definition: fsl-mpc551x.h:1991
uMB_HEADER
Definition: fsl-mpc551x.h:3782
uPCR27
Definition: fsl-mpc551x.h:3450
uRTCORVR
Definition: fsl-mpc551x.h:3558
uSFCNTR
Definition: fsl-mpc551x.h:3059
uPCR19
Definition: fsl-mpc551x.h:3385
EMIOS_tag
Definition: fsl-mpc551x.h:531
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